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Abstract: ,408·Id 0,17·Id 2·U2eff· 2 U2 0,408 · · Id 1,48·Pdi ²) 1,05·Pdi 1,26·Pdi U1 0,289·Id 0,17·Id , ,855 · Udi 0,58 · Id 4,2 300 0,74 · Udi 0,408 · Id 4,2 300 0,855 · Udi 0,289 , Bemessungs-Gleichspannung ( n. VDE 0588 ) Bemessungs-Anschlußspannung UNRMS Ipeff Ipar Uim 3,49·Pdi ²) 2,69·Pdi 3,1·Pdi 1,57·Id Id U2eff· 2 180°el 55V 100V 175V 220V U2 ·I U1 d 1,57·Pdi ²) 1,11·Pdi 1,34·Pdi 0,707·Id 0,5·Id 2·U2eff· 2 180°el 55V 100V 175V 220V U2 ·I ... Original
datasheet

2 pages,
39.6 Kb

230Veff PDI 408 datasheet abstract
datasheet frame
Abstract: ,408·Id 0,17·Id 2·U2eff· 2 U2 0,408 · · Id 1,48·Pdi ²) 1,05·Pdi 1,26·Pdi U1 0,289·Id 0,17·Id , ,855 · Udi 0,58 · Id 4,2 300 0,74 · Udi 0,408 · Id 4,2 300 0,855 · Udi 0,289 , Bemessungs-Gleichspannung ( n. VDE 0588 ) Bemessungs-Anschlußspannung UNRMS Ipeff Ipar Uim 3,49·Pdi ²) 2,69·Pdi 3,1·Pdi 1,57·Id Id U2eff· 2 180°el 55V 100V 175V 220V U2 ·I U1 d 1,57·Pdi ²) 1,11·Pdi 1,34·Pdi 0,707·Id 0,5·Id 2·U2eff· 2 180°el 55V 100V 175V 220V U2 ·I ... Original
datasheet

3 pages,
47.01 Kb

PDI 408 datasheet abstract
datasheet frame
Abstract: circuit Clocks and crystal oscillators JTAG and PDI USB LCD 8-bit Atmel Microcontrollers , unintended. When the PDI programming and debugging is used, the reset line is used as clock. The reset , overvoltage on the RESET pin when the switch is pressed. 3. Any reset capacitors should be removed if PDI , oscillator pins. 8 Atmel AVR1018 AVR1018 8414A-AVR-07/11 Atmel AVR1018 AVR1018 5 JTAG and PDI ports 5.1 JTAG , _ RESET Device external reset line 9 8414A-AVR-07/11 5.2 PDI port interface Figure 5-2. ... Original
datasheet

16 pages,
302.08 Kb

XMEGA Application Notes usb AVR4100 AVR1018 AVR1017 AVR1003 atmel 042 AVR atmel 16 kit schematic Xplain AVR1018 abstract
datasheet frame
Abstract: for XMEGA A3B Reset circuit Clocks and crystal oscillators External bus interface JTAG and PDI , does not go low unintended. When the PDI programming and debugging is used, the reset line is used as , be removed if PDI programming and debugging is used. Other external reset sources should be , 8278B-AVR-03/10 8278B-AVR-03/10 6 JTAG and PDI ports 6.1 JTAG port interface Figure 6-1. JTAG port interface example , , sampled on rising TCK. 14 AVR1012 AVR1012 8278B-AVR-03/10 8278B-AVR-03/10 AVR1012 AVR1012 6.2 PDI port interface Figure 6-2. ... Original
datasheet

17 pages,
314.95 Kb

xmega a3* pdi PDI 408 AVR1003 lpc interface sram AVR atmel 16 kit schematic 8278B-AVR ATAVRXPLAIN AVR1012 AVR1012 abstract
datasheet frame
Abstract: Overview of the XMEGA-A1 Xplained kit. ATxmega128A1 JTAG and PDI XMEGA PORT F USB (COM and PSU , programming/debugging tool to the JTAG and PDI header (J201). The header has a standard JTAG programmer , thus be connected directly to the header. If it is desired to use PDI programming/debugging, an , an opening below the JTAG and PDI header. This is to make room for the orientation tap on the JTAGICE mkII probe. Table 4-1. XMEGA programming and debugging interface ­ JTAG and PDI. J201 pin ... Original
datasheet

13 pages,
159.6 Kb

8MB SDRAM AVR1500 xmega usb atxmega AVR atmel 16 kit schematic atmel dac adc atmel application note atXMEGA128A AT32UC3B1256 Atmel jtag cable Schematic AVR1924 xmega a1 atxmega128a1 evaluation AVR1924 abstract
datasheet frame
Abstract: The chip is configured using a four-wire bus, comprising of PCLK, PDI, PDO and PSEL signals. Data , pins are required (one input and three output pins). The pins connected to PDI, PDO and PCLK can be , PDI PDO DIO DCLK Figure 1 CC1020 CC1020 ­ MCU hardware interface In power-down mode, the CC1020 CC1020 pins assume the following states: Pin PDI PDO PCLK PSEL DIO DCLK Pin state Input Output Input , 7 Application Note AN023 AN023 Configuration interface The CC1020 CC1020 is configured using the PCLK, PDI ... Original
datasheet

7 pages,
157.36 Kb

spi PIC16f876 mcu AN015 cc1020pic 74379 PIC16 PIC16F876 CC1020S PIC16 example code spi slave AN023 CC1020 AN023 abstract
datasheet frame
Abstract: PDI XMEGA" pin header (J100). The pin header is having a standard JTAG programmer pinout (refer to , directly to the header. If it is desired to use PDI programming/debugging an adapter must be used. 3 8203D-AVR-04/10 8203D-AVR-04/10 Table 4-1. XMEGA programming and debugging interface ­ JTAG and PDI. J100 pin JTAG(1) PDI(2) J100-1 J100-1 TCK - J100-2 J100-2 GND GND(3) J100-3 J100-3 TDO - J100-4 J100-4 VCC VCC , JTAG. Problem due to cross-talk contaminating the audio amplifier input. Use the PDI interface or ... Original
datasheet

8 pages,
506.33 Kb

U300 xmega ADC AT90USB1287 atxmega at90usb1287 evaluation board 45DB642 atmel jtag ice mkII A143EA 8MB SDRAM XMEGA Application Notes usb xmega xmega usb Xplain kit AT90USB1287 DAC AVR1907 AT90USB1287 AVR1907 abstract
datasheet frame
Abstract: number that starts with "B0" or be marked with "A09-0041 A09-0041" for PDI to work. 7 8169B-AVR-11/09 8169B-AVR-11/09 As , programming in chapter 5. Figure 5. AVRISP mkII supports PDI interface to do programming only. The AVR , supports PDI interface for the A4 subfamily. Figure 6. AVR DRAGONTM supports debugging and programming via JTAG / PDI. The most versatile alternative, AVR ONE! supports both JTAG and PDI programming , as well as faster PDI and JTAG interfaces. 5 In-system programming and debugging the XMEGA ... Original
datasheet

11 pages,
962.63 Kb

Programmer stk500 sample code adc store avr xmega ADC xmega a1 AVR1302 avr dragon AVR1001 MEGAAVR ATXMEGA128A1 XMEGA Application Notes xmega 128 A1 fuse XMEGA atxmega128a1 TWI AVR1005 AVR1005 abstract
datasheet frame
Abstract: 8397A-AVR-10/2011 4 Connectors The 90° angled, 6-pin, 100mil header is the PDI programming and debugging , debugged by connecting an external programming and debugging tool to the PDI header. The header has a standard PDI programmer pin-out (refer to online help in AVR Studio), and tools such as the Atmel JTAGICE 3, Atmel AVR ONE!, or Atmel AVR JTAGICE mkII can thus be connected to the PDI header. If it is desired to use PDI for programming and debugging, an adapter must be used: · (Dark blue) debugWIRE, SPI ... Original
datasheet

22 pages,
845.6 Kb

AT45DB XMEGA Application Notes usb avr JTAGICE atmel 731 AVR1912 A09-0412 4X40 LCD module Xplain components used to make ldr sensor AVR VOLTAGE REGULATOR Qtouch 320-122 thermistor SCK NTC AVR1912 abstract
datasheet frame
Abstract: not go low unintentionally. When PDI programming and debugging are used, the reset line is used as , reset capacitors should be removed if PDI programming and debugging are used. Other external reset , 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit ... Original
datasheet

9 pages,
183.72 Kb

AVR042 AT90PWM81 AVR178 avr schematic AVR atmel 16 kit schematic AVR178 abstract
datasheet frame

Extended Electronics Archive (Experimental)

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Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
-detector input (PDI) and connect the phase-detector output (PDO) to the input (FADJ) of the internal voltage frequencies equal to the sum and difference of the PDI frequency and the MAX038 MAX038 MAX038 MAX038 output frequency. These F pair at PDI limits that pin's rate of rise to 10ns. Figure 10. The SYNC output lets you approaches 50% when PDI and the output are in phase quadrature (90° out of phase). Otherwise, the duty cycle -detector input (PDI), as required by the slaved device (IC2). On the other hand, SYNC isn't available if a MAX038 MAX038 MAX038 MAX038
www.datasheetarchive.com/files/maxim/0007/view_096.htm
Maxim 04/04/2001 20.14 Kb HTM view_096.htm
. The internal oscillator can be synchronized to an external TTL clock connected to PDI ., Sunnyvale, CA 94086 USA 408-737-7600; info@maxim-ic.com ; http://www.maxim-ic.com/
www.datasheetarchive.com/files/maxim/0002/quick006.htm
Maxim 04/04/2001 6.48 Kb HTM quick006.htm
Parameter tPD tPDi + tBUF tS(D-type) tSS tS(T-type) tSST tH tHS tCO tCOSi + t .g. tPDi) represent internal delays. The output buffer delay tBUF is added to the internal delay Vantis at: Toll Free: 888-826-8471 USA: 408-616-8044 France: 0800-908521 Germany: 089
www.datasheetarchive.com/files/vantis/relnotes-v1.txt
Vantis 08/01/1999 11.86 Kb TXT relnotes-v1.txt
Parameter tPD tPDi + tBUF tS(D-type) tSS tS(T-type) tSST tH tHS tCO tCOSi + t .g. tPDi) represent internal delays. The output buffer delay tBUF is added to the internal delay Vantis at: Toll Free: 888-826-8471 USA: 408-616-8044 France: 0800-908521 Germany: 089
www.datasheetarchive.com/files/vantis/pc/ddirect/relnotes-v1.txt
Vantis 08/01/1999 11.86 Kb TXT relnotes-v1.txt
tPD tPDi + tBUF tS(D-type) tSS tS(T-type) tSST tH tHS tCO tCOSi + tBUF t .g. tPDi) represent internal delays. The output buffer delay tBUF is added to the internal delay = You can contact Vantis at: Toll Free: 888-826-8471 USA: 408-616-8044 France: 0800-908521 Germany
www.datasheetarchive.com/files/vantis/relnotes.txt
Vantis 16/04/1999 19.87 Kb TXT relnotes.txt
tPD tPDi + tBUF tS(D-type) tSS tS(T-type) tSST tH tHS tCO tCOSi + tBUF t .g. tPDi) represent internal delays. The output buffer delay tBUF is added to the internal delay = You can contact Vantis at: Toll Free: 888-826-8471 USA: 408-616-8044 France: 0800-908521 Germany
www.datasheetarchive.com/files/vantis/pc/ddirect/relnotes.txt
Vantis 16/04/1999 19.87 Kb TXT relnotes.txt
suppressor BZA408B - Quadruple bidirectional ESD transient voltage suppressor BZA420A BZA420A BZA420A BZA420A
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Philips 17/02/2002 627.82 Kb HTML 283.html
Product listing 74ABT00 74ABT00 74ABT00 74ABT00 - Quad 2-input NAND gate 74ABT02 74ABT02 74ABT02 74ABT02 - Quad 2-input NOR gate 74ABT04 74ABT04 74ABT04 74ABT04 - Hex inverter 74ABT08 74ABT08 74ABT08 74ABT08 - Quad 2-input AND gate 74ABT10 74ABT10 74ABT10 74ABT10 - Triple 3-input NAND gate 74ABT125 74ABT125 74ABT125 74ABT125 - Quad buffer (3-State) 74ABT126 74ABT126 74ABT126 74ABT126 - Quad buffer (3-State) 74ABT161543 74ABT161543 74ABT161543 74ABT161543 - 16-bit latched transceiver with dual enable and master reset (3-State) 74ABT162240 74ABT162240 74ABT162240 74ABT162240 - 16-Bit Inverting Buffer/D
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Philips 17/02/2002 359.13 Kb HTML 27063-v1.html
Product listing for Logic Products listing Product name PIP 74ABT00 74ABT00 74ABT00 74ABT00 - Quad 2-input NAND gate 74ABT02 74ABT02 74ABT02 74ABT02 - Quad 2-input NOR gate 74ABT04 74ABT04 74ABT04 74ABT04 - Hex inverter 7
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Philips 25/04/2003 448.77 Kb HTML 27063.html
Product listing for Logic Products listing Product name PIP 74ABT00 74ABT00 74ABT00 74ABT00 - Quad 2-input NAND gate 74ABT02 74ABT02 74ABT02 74ABT02 - Quad 2-input NOR gate 74ABT04 74ABT04 74ABT04 74ABT04 - Hex inverter 74AB
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Philips 01/06/2005 426.16 Kb HTML 27063-v2.html