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PB60A

Catalog Datasheet Results Type PDF Document Tags
Abstract: PR63A ;pb38a lrc_sq_vccrx2 pb64a;pb76b;pb65a pb66a;pb67b;pb60a;pb73a ... Original
datasheet

9 pages,
54.22 Kb

pt95a PT65A PR41B PB60B PR62A pb37a PR46B PR21A PR67A PT60A PB68B PR57A PL34B PR28B PT43B TN1159 TN1159 abstract
datasheet frame
Abstract: PB59B PB59B PB60A PB60B PB60B PB61A PB61A PB61B PB61B PB62A PB62A PB62B PB62B PB63A PB63A PB63B PB63B PB64A PB64A PB64B PB64B PB65A PB65A PB65B PB65B PB66A PB66A PB66B PB66B ... Original
datasheet

6 pages,
97 Kb

PL46A PL05 PL04A PR34A PB09B PB08B PR48A pr64a PB07A Mictor PR30A PL42B 3528 pins 20 PL08A PR09A datasheet abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.4, January 2009 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 583 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) / DD ... Original
datasheet

386 pages,
2474.41 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.1, April 2008 LatticeECP2/M Family Data Sheet Introduction August 2007 Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 583 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) / DD ... Original
datasheet

385 pages,
2445.97 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.9, January 2012 LatticeECP2/M Family Data Sheet Introduction January 2012 Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 583 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) / ... Original
datasheet

389 pages,
2877.96 Kb

16x4 sram DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 02.3, February 2007 LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 616 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1/DDR2 ... Original
datasheet

268 pages,
2132.48 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 02.7, July 2007 LatticeECP2/M Family Data Sheet Introduction July 2007 Advance Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 616 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) ... Original
datasheet

293 pages,
2230.33 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 02.5, March 2007 LatticeECP2/M Family Data Sheet Introduction March 2007 Advance Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 616 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MH 200MH ... Original
datasheet

288 pages,
2150.43 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 02.6, April 2007 LatticeECP2/M Family Data Sheet Introduction April 2007 Advance Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 616 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MH 200MH ... Original
datasheet

290 pages,
2153.63 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 02.9, September 2007 LatticeECP2/M Family Data Sheet Introduction August 2007 Advance Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 583 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 ( ... Original
datasheet

356 pages,
2367.87 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 02.8, August 2007 LatticeECP2/M Family Data Sheet Introduction August 2007 Advance Data Sheet DS1006 DS1006 Features High Logic Density for System Integration · 6K to 95K LUTs · 90 to 583 I/Os Pre-Engineered Source Synchronous I/O · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200 ... Original
datasheet

355 pages,
2366.14 Kb

DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.6, March 2010 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 DS1006 Pre-Engineered Source Synchronous I/O Features · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) / DDR2: 533 (266MHz) · Dedicated DQS support High Logic Density for ... Original
datasheet

393 pages,
2883.76 Kb

c 4161 DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.7, July 2010 LatticeECP2/M Family Data Sheet Introduction July 2010 Data Sheet DS1006 DS1006 Pre-Engineered Source Synchronous I/O Features · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) / DDR2: 533 (266MHz) · Dedicated DQS support High Logic Density for S ... Original
datasheet

393 pages,
2886.34 Kb

PR68A LFE2M20E-5FN484i LFE2M50E-5FN484C LFE2M50e lfe2m35se LFE2M50 DS1006 DS1006 abstract
datasheet frame
Abstract: LatticeECP2/M Family Data Sheet DS1006 DS1006 Version 03.3, August 2008 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 DS1006 Pre-Engineered Source Synchronous I/O Features · DDR registers in I/O cells · Dedicated gearing logic · Source synchronous standards support ­ SPI4.2, SFI4 (DDR Mode), XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1: 400 (200MHz) / DDR2: 533 (266MHz) · Dedicated DQS support High Logic Density for ... Original
datasheet

386 pages,
2472.67 Kb

socket 1156 pinout pr77a FFT 1024 point CEI 23-50 socket am3 socket pinout CEI 23-50 226 35K capacitor datasheet L33 thermal fuse LFE2M50 marking l33 LFE2M20SE-5FN484C M33 thermal fuse PB58 DS1006 DS1006 DS1006 abstract
datasheet frame