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PB21C

Catalog Datasheet Results Type PDF Document Tags
Abstract: 22 Pin 25 Pin 28 3.3V PB3C PB5C PB7C PB13A PB13A PB14A PB14A PB15C PB15C PB17C PB17C PB21C PB23A PB23A Pin 2 Pin ... Original
datasheet

24 pages,
144.58 Kb

LVDS connector 30 pin PB36D PB7D pl20c J47-J49 PL43D PT33C j33j 6-pin JTAG header 37-pin pinout J41-J46 LVDS display 30 pin connector PB36C transistor pt31C ORT8850 CON14 ORT8850 abstract
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Abstract: Preliminary Data Sheet December 2000 ORCA® Series 4 Field-Programmable Gate Arrays Programmable Features s s High-performance platform design. - 0.13 µm seven-level metal technology. - Internal performance of >250 MHz (four logic levels). - I/O performance of >416 MHz for all user I/Os. - Over 1.5 million usable system gates. - Meets multiple I/O interface standards. - 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. - Embedded ... Original
datasheet

124 pages,
1417.3 Kb

mux8x1 PT35c transistor PT36c transistor pt31c PR25D transistor pt31C transistor pt42c datasheet transistor pt36C transistor pt36c datasheet abstract
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Abstract: LatticeSC Family Data Sheet DS1004 DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.1 ... Original
datasheet

208 pages,
2317.62 Kb

DS1004 DS1004 abstract
datasheet frame
Abstract: LatticeSC Family Data Sheet DS1004 DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3. ... Original
datasheet

208 pages,
2317.59 Kb

DS1004 DS1004 abstract
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Abstract: Data Sheet January 15, 2002 ORCA® Series 4 FPGAs Introduction Traditional I/O selections: - LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time a ... Original
datasheet

174 pages,
880.2 Kb

K72 R8 CE1M K72 R1 CORE F5A INTEL Core i7 860 K72 v4 datasheet transistor pt36C transistor pt42c transistor pt36c datasheet abstract
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Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features ­ 1 to 7.8 Mbits memory ­ True Dual Port/Pseudo Dual Port/Single Port ­ Dedicated FIFO logic for all block RAM ­ 500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... Original
datasheet

243 pages,
1343.14 Kb

umi u26 SCM15 SC80 SC40 SC25 SC15 SC115 transistor pt42c transistor pt36c pt36C DS1004 DS1004 abstract
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Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125G ... Original
datasheet

237 pages,
2548.5 Kb

PB124A PL84C PR55D pr94a diode SC115 SC15 transistor pt42c SCM15 BA5 904 AF P SC80 SC40 SC25 pr82a PB110C umi u26 DS1004 DS1004 DS1004 abstract
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Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.2, December 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125Gbps) · ... Original
datasheet

237 pages,
2568.02 Kb

DS1004 DS1004 abstract
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Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.12 ... Original
datasheet

236 pages,
2407.29 Kb

DS1004 DS1004 abstract
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Abstract: Data Sheet April, 2002 ORCA® Series 4 FPGAs Introduction Built on the Series 4 reconfigurable embedded system-on-chip (SoC) architecture, Lattice introduces its new family of generic field-programmable gate arrays (FPGA). The high-performance and highly versatile architecture brings a new dimension to bringing network system designs to market in less time than ever before. This new device family offers many new features and architectural enhancements not available in any earlier FPGA genera ... Original
datasheet

151 pages,
782.81 Kb

CORE F5A datasheet abstract
datasheet frame
Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3 ... Original
datasheet

238 pages,
2481.87 Kb

DS1004 DS1004 abstract
datasheet frame