NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 22 Pin 25 Pin 28 3.3V PB3C PB5C PB7C PB13A PB13A PB14A PB14A PB15C PB15C PB17C PB17C PB21C PB23A PB23A Pin 2 Pin ... | Original |
24 pages, |
37-pin pinout j33j LVDS connector 30 pin MPC680 ORT8850 PB17C PB35C PB36D PB7D pl20c PT33C PB36C J41-J46 LVDS display 30 pin connector ORT8850 abstract |
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| Abstract: Preliminary Data Sheet December 2000 ORCA® Series 4 Field-Programmable Gate Arrays Programmable Features s s High-performance platform design. - 0.13 um seven-level metal technology. - Internal performance of >250 MHz (four logic levels). - I/O performance of >416 MHz for all user I/Os. - Over 1.5 million usable system gates. - Meets multiple I/O interface standards. - 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. - Embedded ... | Original |
124 pages, |
OR4E10 MUX21 PT42C diode k70 PL34C mux8x1 PT35c transistor PT36c transistor PR25D pt31c PT18C transistor pt31C transistor pt42c datasheet transistor pt36C transistor pt36c datasheet abstract |
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| Abstract: Data Sheet January 15, 2002 ORCA® Series 4 FPGAs Introduction Traditional I/O selections: - LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time a ... | Original |
174 pages, |
K72 R8 conversion software jedec lattice pl20c PT 9732 PT35c transistor INTEL Core i7 860 K72 v4 PT42C datasheet transistor pt36C transistor pt42c pt36c transistor pt36c datasheet abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features 1 to 7.8 Mbits memory True Dual Port/Pseudo Dual Port/Single Port Dedicated FIFO logic for all block RAM 500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... | Original |
243 pages, |
DS1004 PR80C 426 b34 umi u26 SCM15 SC80 SC40 SC25 SC15 SC115 transistor pt42c transistor pt36c PB110C pt36C DS1004 abstract |
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| Abstract: Data Sheet May, 2006 ORCA® Series 4 FPGAs Traditional I/O selections: - LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time. - ... | Original |
152 pages, |
ap13.6 diode MPC8260 MPC860 mux8x1 OR4E02 OR4E06 PT 9732 transistor pt42c PT35c transistor transistor pt36c datasheet abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typ ... | Original |
238 pages, |
PR83a PR91A SC40 SC80 SC25 SC15 SC115 SCM15 transistor pt42c PB138 LFSCM3GA80EP1-6FC1152C pb127d PB110C transistor pt36c pr94a diode DS1004 DS1004 DS1004 abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125G ... | Original |
237 pages, |
W32 MARKING DS1004 PB124A PL84C PR55D pr94a diode SC115 SC15 SC25 transistor pt42c BA5 904 AF P SCM15 SC80 SC40 pr82a DS1004 abstract |
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| Abstract: Data Sheet March, 2003 ORCA® Series 4 FPGAs Introduction Traditional I/O selections: - LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zer ... | Original |
152 pages, |
transistor BC 557 bwh series MPC860 ap13.6 diode Core i7 860 BOX transistor tl 187 transistor on 4409 497AA PT35c transistor PR37 PR25D plc programming languages pt8a datasheet abstract |
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| Abstract: ORCATM Series 4 FPGA Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications (PCNs) #09-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line OR4E02 OR4E02 OR4E04 OR4E04 Ordering Part Number OR4E02-3BA352C OR4E02-3BA352C OR4E02-2BA352C OR4E02-2BA352C OR4E02-1BA352C OR4E02-1BA352C OR4E02-2BA352I OR4E02-2BA352I OR4E02-1BA352I OR4E02-1BA352I OR4E02- OR4E02- ... | Original |
154 pages, |
transistor pt42c mux8x1 OR4E02-1BA352C OR4E02-1BA352I OR4E02-1BM416C OR4E02-2BA352I OR4E02-2BM416C OR4E02-2BM416I OR4E02-3BM416C OR4E02-3BM680C PT35c transistor pt36c OR4E06 datasheet abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features 1 to 7.8 Mbits memory True Dual Port/Pseudo Dual Port/Single Port Dedicated FIFO logic for all block RAM 500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... | Original |
243 pages, |
W32 MARKING DS1004 PL80B PR55D pr94a diode RS 302 440 40 SC115 SC15 SC25 transistor pt42c transistor pt36c BA5 904 AF P SC80 SC40 DS1004 abstract |
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| Abstract: Data Sheet November, 2003 ORCA® Series 4 FPGAs Introduction Traditional I/O selections: - LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and ... | Original |
158 pages, |
csr pics bwh series ARM Holdings plc AM3 Processor Functional Data Sheet parallel interface port 0f mpc 860 PR25D transistor BC 557 PLC Communication cables pin diagram ap13.6 diode transistor on 4409 transistor BC 157 PT42C datasheet abstract |
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| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.4, December 2011 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125Gbps) · ... | Original |
244 pages, |
DS1004 DS1004 abstract |
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