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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features  1 to 7.8 Mbits memory  True Dual Port/Pseudo Dual Port/Single Port  Dedicated FIFO logic for all block RAM  500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... | Original |
243 pages, |
DS1004 PR80C 426 b34 umi u26 SCM15 SC80 SC40 SC25 SC15 SC115 transistor pt42c transistor pt36c PB110C pt36C DS1004 abstract |
| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 132 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 8 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typ ... | Original |
238 pages, |
PR83a PR91A SC40 SC80 SC25 SC15 SC115 SCM15 transistor pt42c PB138 LFSCM3GA80EP1-6FC1152C pb127d PB110C transistor pt36c pr94a diode DS1004 DS1004 DS1004 abstract |
| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125G ... | Original |
237 pages, |
W32 MARKING DS1004 PB124A PL84C PR55D pr94a diode SC115 SC15 SC25 transistor pt42c BA5 904 AF P SCM15 SC80 SC40 pr82a DS1004 abstract |
| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features  1 to 7.8 Mbits memory  True Dual Port/Pseudo Dual Port/Single Port  Dedicated FIFO logic for all block RAM  500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... | Original |
243 pages, |
W32 MARKING DS1004 PL80B PR55D pr94a diode RS 302 440 40 SC115 SC15 SC25 transistor pt42c transistor pt36c BA5 904 AF P SC80 SC40 DS1004 abstract |
| Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.4, December 2011 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125Gbps) · ... | Original |
244 pages, |
DS1004 DS1004 abstract |
| Abstract: NAPC/PHILIPS SEMICON]) blE J> â- bb5312M 0071=102 4TT «SIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification 3-volt single-chip microcontroller peripheral PSD311L PSD311L Key Features â-¡ Single Chip Programmable Peripheral for Microcontroller-based Applications â-¡ 3.0 to 5.5 Volt Operation â-¡ 19 Individually Configurable I/O pins that can be used as: - Microcontroller I/O port expansion - Programmable Address Decoder (PAD) I/O - Latched address output - Open drain or ... | OCR Scan |
18 pages, |
T23A T12A psd3xxl psd3xx PSD311L em-18 007116-1 PSD311L abstract |