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P102 Datasheet

Part Manufacturer Description PDF Type
P102 International Rectifier PASSIVATED ASSEMBLED CIRCUIT ELEMENTS 25A Original
P102 International Rectifier Passivated Assembled Circuit Element Original
P102 International Rectifier Power Diodes / Power Thyristors, Passivated Assembled Circuit Elements 25A Scan
P102 N/A Semiconductor Master Cross Reference Guide Scan
P102 N/A Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Scan
P102 N/A Short Form Datasheet and Cross Reference Data Scan
P102 N/A Shortform Datasheet & Cross References Data Scan
P1020 Global Components & Controls High reliability photocoupler. Original
P102-000 Tripp Lite D-Sub, D-Shaped Connectors - Adapters, Connectors, Interconnects, ADAPTER DB9F TO DB25F Original
P102-000-R Tripp Lite D-Sub, D-Shaped Connectors - Adapters, Connectors, Interconnects, ADAPTER DB9F TO DB25F Original
P102-03SC PhaseLink Low Skew Output Buffer Original
P102-04SC PhaseLink Low Skew Output Buffer Original
P102-05SC PhaseLink Low Skew Output Buffer Original
P1020MBG-PC Freescale Semiconductor Evaluation and Demonstration Boards and Kits, Programmers, Development Systems, QORIQ MULTI-SERV BUS SOLUTION Original
P1020NSE2DFB Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 533MHZ 689-TEPBGA2 Original
P1020NSE2FFB Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 667MHZ 689-TEPBGA2 Original
P1020NSE2HFB Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 800MHZ 689-TEPBGA2 Original
P1020NSN2DFB Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 533MHZ 689-TEPBGA2 Original
P1020NSN2FFB Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 667MHZ 689-TEPBGA2 Original
P1020NSN2HFB Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 800MHZ 689-TEPBGA2 Original
Showing first 20 results.

P102

Catalog Datasheet MFG & Type PDF Document Tags

esa scc 3401 d-sub

Abstract: 02BNMB P102 NM D8949 P102 NM D8949 P102 NM D8949 P102 NM D8949 P103 NM D8949 P102 NM D8949 P103 NM D8949 P102
Souriau
Original
02BNMB 44BNMB 45BNMB esa scc 3401 d-sub 70513 05BN 03BNMB 05BNMB 04BNMB
Abstract: áç NOVEMBER 2002 PRELIMINARY XRT85L61 REV. P1.0.2 BITS (BUILDING INTEGRATED TIMINING , . P1.0.2 ORDERING INFORMATION PART NUMBER XRT85L61IV PACKAGE 28 Lead TSSOP OPERATING TEMPERATURE , 15 2 XRT85L61 BITS (BUILDING INTEGRATED TIMINING SUPPLY) CLOCK EXTRACTOR REV. P1.0.2 áç , INTEGRATED TIMINING SUPPLY) CLOCK EXTRACTOR REV. P1.0.2 TYPE I DESCRIPTION Reference T1 Clock input , INTEGRATED TIMINING SUPPLY) CLOCK EXTRACTOR REV. P1.0.2 áç PRELIMINARY PIN DESCRIPTIONS PIN # 11 Exar
Original
GR-1244-CORE

B8ZS* encoding

Abstract: OCTOBER 2000 PRELIMINARY XRT82L34 REV. P1.0.2 QUAD E1/T1/J1 LINE TRANSCEIVER WITH CLOCK , QUAD E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.2 PRELIMINARY , PRELIMINARY V XRT82L34 QUAD E1/T! LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.2 , format. 8 PTS2/DATAF 6 PIN # 9 10 XRT82L34 REV. P1.0.2 QUAD E1/T! LINE TRANSCEIVER , WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.2 PRELIMINARY NAME INT TYPE O DESCRIPTION
Exar
Original
B8ZS* encoding XRT82L24

diode sg 87

Abstract: P302T 0 7 iX V '' SGSP101/P102 * S ^ > SGSP201/P202 N-CHANNEL POWER MOS TRANSISTORS ' HIGH SPEED , -5 0 -1 2 9/85 S G S-THOMSO.N 07E D | 7 ^ 2 3 ? 0D177ûb 2 | I 73C 17283 D JZ 07 SGSP101/P102 " , ]2c i237 0017737 4 73C T7284 D T-'Ôe )'07 . . . : SGSP101/P102 SGSP201/P202 SGSP301/P302 E LE C T , ' -* 07E D g ? =12=1 237 D 0017700 t, | SGSP101/P102 SGSP201/P202 SGSP301/P302 , C 17 2 8 6 « e r _D T'^37-2):?' . , ,-Jner w r r s T - SGSP101/P102 ^ h ^ - SGSP201/P202 4 * £ '
-
OCR Scan
SP301 SP302 diode sg 87 P302T SGSP101 SGSP201 001-7737 SGSP101/P102 301/P30Z GD177C E--03
Abstract: áç MARCH 2002 PRELIMINARY XRT83SL34 REV. P1.0.2 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK , JITTER ATTENUATOR REV. P1.0.2 áç PRELIMINARY FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 , . P1.0.2 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY · , . P1.0.2 áç PRELIMINARY TABLE OF CONTENTS GENERAL DESCRIPTION , . 28 I áç XRT83SL34 REV. P1.0.2 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND Exar
Original

MDIO clause 45 specification

Abstract: dj rw PRELIMINARY XRS10L140 SERIAL ATA II: 1:4 PORT MULTIPLIER JUNE 2006 REV. P1.0.2 1.0 , XRS10L140 PRELIMINARY SERIAL ATA II: 1:4 PORT MULTIPLIER REV. P1.0.2 HIGH SPEED I/O FEATURES , R SATA PRELIMINARY XRS10L140 SERIAL ATA II: 1:4 PORT MULTIPLIER REV. P1.0.2 2.0 , MULTIPLIER REV. P1.0.2 TABLE 1: XRS10L140 PIN DESCRIPTIONS Pin Name HBACT Pin Number 76 I/O , Analog Ground. 4 PRELIMINARY XRS10L140 SERIAL ATA II: 1:4 PORT MULTIPLIER REV. P1.0.2
Exar
Original
MDIO clause 45 specification dj rw MDIO MDIO clause 22 TLO 64 Op Amp 000D XRS10L20
Abstract: PRELIMINARY SEPTEMBER 2006 XR16V554/554D REV. P1.0.2 2.25V TO 3.6V QUAD UART WITH 16 , XR16V554/554D PRELIMINARY REV. P1.0.2 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO FIGURE 2. PIN OUT , A0 A0 PRELIMINARY REV. P1.0.2 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO , PART NUMBER XR16V554IJ XR16V554IV XR16V554DIV XR16V554IL XR16V554IV80 PRELIMINARY REV. P1.0.2 , 4 PRELIMINARY REV. P1.0.2 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO Pin Exar
Original
XR16V554 ST16C554 ST16C454 TL16C554A SC16C554B 16C550
Abstract: 2003 REV. P1.0.2 GENERAL DESCRIPTION Additional features include RLOS, a 16-bit LCV counter , LINE INTERFACE UNIT PRELIMINARY REV. P1.0.2 â'¢ Selectable receiver sensitivity from 0 to 36dB , /J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2 PIN OUT OF THE XRT83L314 XRT83L314 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.2 TABLE OF CONTENTS , REV. P1.0.2 FIGURE 17. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN Exar
Original

XRK69774

Abstract: XRK69774 PRELIMINARY 1:14 LVCMOS PLL CLOCK GENERATOR AUGUST 2006 REV. P1.0.2 GENERAL , LVCMOS PLL CLOCK GENERATOR REV. P1.0.2 PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE , PLL CLOCK GENERATOR REV. P1.0.2 PIN DESCRIPTIONS PIN # NAME TYPE 1,15, 19, 24, 30, 35 , resistor. 3 PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.2 1.0 , mA 8 mA PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.2 TABLE
Exar
Original
125MH

CHN 703

Abstract: AS11D OCTOBER 2003 REV. P1.0.2 GENERAL DESCRIPTION attenuator performance meets the ETSI TBR-24 and , XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. P1.0.2 · , WITH JITTER ATTENUATOR PRELIMINARY REV. P1.0.2 TABLE OF CONTENTS GENERAL DESCRIPTION , PRELIMINARY REV. P1.0.2 FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED , PRELIMINARY TABLE 22: TABLE 23: TABLE 24: TABLE 25: REV. P1.0.2 THE ABOVE IS: CHANNEL LEVEL
Exar
Original
CHN 703 AS11D 75R12 diode ja8 DMO11 DMO10 GR-499
Abstract: REV. P1.0.2 GENERAL DESCRIPTION APPLICATIONS The XRT83SL216 is a fully integrated 16 , rx XRT83SL216 PRELIMINARY 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2 , XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2 FIGURE 2. PIN OUT FOR THE , SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2 GENERAL DESCRIPTION , ) . 24 I rx REV. P1.0.2 PRELIMINARY XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE Exar
Original

XRS10L240

Abstract: MDIO JUNE 2006 1.0 REV. P1.0.2 INTRODUCTION The XRS10L240 provides the combined advantages of , PRELIMINARY & CONFIDENTIAL SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. P1.0.2 HIGH SPEED I/O , / PORT SELECTOR REV. P1.0.2 2.0 EXTOR - 1 XRS10L240 FUNCTIONAL DESCRIPTION A top-level , SELECTOR 2.1 REV. P1.0.2 Out Of Band Feature Each Serial ATA link provides full support for the , 17 PRELIMINARY & CONFIDENTIAL REV. P1.0.2 2.2 EXTOR - 1 XRS10L240 SERIAL ATA II: PORT
Exar
Original

0x0203

Abstract: 21-CHANNEL PRELIMINARY NOVEMBER 2006 XRT86SH221 REV. P1.0.2 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED , www.exar.com XRT86SH221 FEATURES VT Mapper PRELIMINARY REV. P1.0.2 SDH-TO-PDH FRAMER/MAPPER WITH , buffer for bit retiming. 2 PRELIMINARY REV. P1.0.2 XRT86SH221 SDH-TO-PDH FRAMER/MAPPER WITH , , B2) and counts the errors. 3 XRT86SH221 PRELIMINARY REV. P1.0.2 SDH-TO-PDH FRAMER , . 41 I PRELIMINARY REV. P1.0.2 XRT86SH221 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21
Exar
Original
21-CHANNEL 0x0203 VC-12 VC-12/TU-12/TUG2/ VC-12/TU-12/TUG-2/TUG-3/ VC-12/TU-12/ VC-12/TU-12/TUG-2/

XRK32308

Abstract: XRK32308-1 XRK32308 PRELIMINARY 3.3V ZERO DELAY BUFFER MAY 2006 REV. P1.0.2 GENERAL DESCRIPTION , www.exar.com PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 TABLE 1: PIN D ESCRIPTION , bypass mode, S2 = 1 and S1 = 0. 2 PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 , PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 TABLE 4: ABSOLUTE MAXIMUM RATINGS Supply , XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308
Exar
Original
XRK32308-1 XRK32308-1H XRK32308-2 XRK32308CD-1 XRK32308CDTR-1 120MH
Abstract: xr MARCH 2005 PRELIMINARY XRK4991 REV. P1.0.2 3.3V HIGH-SPEED (80 MHZ) PROGRAMMABLE SKEW , SKEW CLOCK BUFFER xr REV. P1.0.2 PRODUCT ORDERING INFORMATION PART NUMBER XRK4991IJ-5 XRK4991CJ , 19 QB1 2 TEST FSEL GND VCCQ xr REV. P1.0.2 XRK4991 PRELIMINARY 3.3V HIGH-SPEED , CALCULATION [1] fNOM (MHZ) FSEL[2,3] LOW MID HIGH MIN 15 25 40 MAX 30 50 80 xr REV. P1.0.2 tU = 1 , reached 2.8V. 4 xr REV. P1.0.2 XRK4991 PRELIMINARY 3.3V HIGH-SPEED (80 MHZ) PROGRAMMABLE SKEW Exar
Original

ANT-20

Abstract: rneg2 áç AUGUST 2004 PRELIMINARY XRT83SL28 REV. P1.0.2 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE , UNIT REV. P1.0.2 áç PRELIMINARY FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 1 of , SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2 · Fully integrated 8-Channel short haul transceivers for E1 , -40°C to +85°C 3 XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2 áç , 34 35 36 4 áç PRELIMINARY XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.2
Exar
Original
ANT-20 rneg2

XRK4991

Abstract: XRK4991A FEBRUARY 2005 REV. P1.0.2 FUNCTIONAL DESCRIPTION The XRK4991A 3.3V High-Speed Low-Voltage , ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.2 PRODUCT ORDERING INFORMATION PRODUCT NUMBER ACCURACY , HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.2 PIN DESCRIPTIONS PIN NAME PIN # , PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.2 EXTERNAL FEEDBACK By , REV. P1.0.2 TABLE 2: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) tU = 1 / fNOM X N
Exar
Original
XRK4991ACJ-5 XRK4991ACJ-7 XRK4991AIJ-5 XRK4991AIJ-7 EXAR Function generator
Abstract: PRELIMINARY SEPTEMBER 2006 XR16V654/654D REV. P1.0.2 2.25V TO 3.6V QUAD UART WITH 64 , FAX (510) 668-7017 · www.exar.com XR16V654/654D PRELIMINARY REV. P1.0.2 2.25V TO 3.6V QUAD , 8 9 PRELIMINARY REV. P1.0.2 XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO , REV. P1.0.2 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO FIGURE 4. PIN OUT ASSIGNMENT FOR 48-PIN QFN , PRELIMINARY REV. P1.0.2 XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO ORDERING INFORMATION Exar
Original
XR16V6541 XR16V654IV XR16V654DIV XR16V654 ST16C654/654D TL16C754B

DMO 565 R

Abstract: chn 924 xr JUNE 2005 PRELIMINARY XRT86L30 REV. P1.0.2 SINGLE T1/E1/J1 FRAMER/LIU COMBO , (510) 668-7000 · FAX (510) 668-7017 · www.exar.com xr REV. P1.0.2 PRELIMINARY XRT86L30 , FRAMER/LIU COMBO PRELIMINARY xr REV. P1.0.2 · Direct access to D and E channels for fast , PART NUMBER XRT86L30IV PACKAGE 128 TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C 3 xr REV. P1.0.2 , ) . 196 I XRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO PRELIMINARY xr REV. P1.0.2 6.7.9
Exar
Original
DMO 565 R chn 924 CHN G4 120

MSR-3 0.020 OHM 1

Abstract: PRELIMINARY JUNE 2003 XR16L2450 2.25V TO 5.5V DUART REV. P1.0.2 GENERAL DESCRIPTION The , DUART REV. P1.0.2 DSRA# VCC RIA# CTSA# 38 CDA# 48 NC 47 46 45 44 43 , 2 XR16L2450 2.25V TO 5.5V DUART REV. P1.0.2 PRELIMINARY xr PIN DESCRIPTIONS Pin , -TQFP PIN # 34 39 TYPE O I DESCRIPTION xr XR16L2450 2.25V TO 5.5V DUART REV. P1.0.2 UART channel A , 21 I OP2B# 15 9 O 4 XR16L2450 2.25V TO 5.5V DUART REV. P1.0.2 PRELIMINARY
Exar
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MSR-3 0.020 OHM 1 L2450 ST16C2450 ST16C2550 XR16L2550 XR16L2750 XR16C2850
Abstract: PRELIMINARY NOVEMBER 2007 XRT86SH328 REV. P1.0.2 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER , ) 668-7017 · www.exar.com XRT86SH328 PRELIMINARY REV. P1.0.2 SONET TO 28-T1/21-E1 PDH MAPPER - , 568 PBGA-TEP OPERATING TEMPERATURE RANGE -40° C to +85° C 2 PRELIMINARY REV. P1.0.2 , channels for fast transmission of data link information 3 XRT86SH328 PRELIMINARY REV. P1.0.2 , 4 PRELIMINARY REV. P1.0.2 XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND Exar
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VC-11/VC-12 VC-11/TU-11/TUG-2/VC-3/AU-3/STM-0 VC-12/TU12/TUG-2/VC-3/AU-3/STM-0 VC11/TU11/ VC-11/TU-11/TUG-2/

1000kA

Abstract: block diagram of automatic flush system áç DECEMBER 2003 PRELIMINARY XRT91L81 REV. P1.0.2 2.488/2.666GBPS OC-48/STM-16 SONET/SDH , TRANSCEIVER REV. P1.0.2 áç PRELIMINARY FEATURES · Selectable full duplex operation between standard , 12 13 14 REV. P1.0.2 XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER REV. P1.0.2 áç PRELIMINARY TABLE OF CONTENTS GENERAL DESCRIPTION , . P1.0.2 FIGURE 15. PARALLEL REMOTE LOOPBACK
Exar
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1000kA block diagram of automatic flush system 0X00H OC-48
Abstract: áç DECEMBER 2000 PRELIMINARY XRT71D03 REV. P1.0.2 3 CHANNEL E3/DS3/STS-1 JITTER , REV. P1.0.2 áç PRELIMINARY FIGURE 2. PIN OUT OF THE XRT71D03 48 47 46 45 44 43 42 41 40 39 , . P1.0.2 áç PRELIMINARY PIN DESCRIPTIONS PIN DESCRIPTION PIN # 1 2 3 NAME AVDD VSS RRCLK0 , DESYNCHRONIZER REV. P1.0.2 PRELIMINARY PIN DESCRIPTION PIN # 11 NAME MODE_CTRL TYPE I DESCRIPTION Mode , DESYNCHRONIZER REV. P1.0.2 áç PRELIMINARY NAME DS3/E3_ch0 TYPE I DESCRIPTION PIN DESCRIPTION PIN # 20 Exar
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GR-253 GR-235-CORE GR499-CORE TBR24

PC403

Abstract: XRT79L72 Interface operating at 25, 33 or 50 MHz. REV. P1.0.2 · On chip Clock and Data Recovery circuit for , - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC REV. P1.0.2 TRANSMIT PACKET PROCESSING · Inserts PPP , PRELIMINARY 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC XRT79L72 REV. P1.0.2 PRODUCT ORDERING , -40°C to +85°C 3 XRT79L72 REV. P1.0.2 PRELIMINARY xr 2 - CHANNEL DS3/E3 ATM UNI/PPP , . 54 I xr PRELIMINARY 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC XRT79L72 REV. P1.0.2
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PC403 XRT79L72IB hdlc IBM POS GR-499-CORE
Abstract: áç AUGUST 2000 PRELIMINARY XRT82L38 REV. P1.0.2 OCTAL E1/T1/J1 LINE TRANSCEIVER WITH , www.exar.com XRT82L38 OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.2 , 61 62 63 64 65 66 67 68 69 70 71 72 2 áç XRT82L38 REV. P1.0.2 OCTAL E1/T1/J1 LINE , REV. P1.0.2 áç PRELIMINARY PIN DESCRIPTIONS PIN DESCRIPTION PIN # 1 2 NAME RCLK2 TYPE O O , PLL Analog Positive Supply (3.3V± 5%) 3 áç XRT82L38 REV. P1.0.2 OCTAL E1/T1/J1 LINE Exar
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CTR12/13

l 7135

Abstract: MOTOROLA MP PRELIMINARY NOVEMBER 2003 XRT86L34 QUAD T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.2 GENERAL , XRT86L34 QUAD T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.2 PRELIMINARY · 3 Integrated HDLC controllers per , PACKAGE 225 Tape Ball Grid Array REV. P1.0.2 OPERATING TEMPERATURE RANGE -40°C to +85°C 3 XRT86L34 QUAD T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.2 PRELIMINARY TABLE OF CONTENTS 1.0 MICROPROCESSOR , ) .410 I XRT86L34 QUAD T1/E1/J1 FRAMER/LIU COMBO PRELIMINARY REV. P1.0.2 11.9 FRAME
Exar
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l 7135 MOTOROLA MP add 2201
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