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TMP112AIDRLT Texas Instruments 1.4V-Capable ±0.5°C Accuracy Digital Temperature Sensor in the Compact SOT-563 Package 6-SOT-5X3 -40 to 125 visit Texas Instruments Buy
MSP430P112IJL Texas Instruments 16-BIT, OTPROM, RISC MICROCONTROLLER, CDIP20 visit Texas Instruments
TMP112AIDRLR Texas Instruments 1.4V-Capable ±0.5°C Accuracy Digital Temperature Sensor in the Compact SOT-563 Package 6-SOT-5X3 -40 to 125 visit Texas Instruments Buy
TMP112AQDRLRQ1 Texas Instruments Automotive 1.4V-Capable ±0.5°C Temperature Sensor With Alert Function and I2C/SMBus 6-SOT-5X3 -40 to 125 visit Texas Instruments Buy
TMP112BIDRLT Texas Instruments 1.4V-Capable ±0.5°C Accuracy Digital Temperature Sensor in the Compact SOT-563 Package 6-SOT-5X3 -40 to 125 visit Texas Instruments Buy

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P1-12 Datasheet

Part Manufacturer Description PDF Type
P112 Electroswitch Accessories, Switches, DIAL PLATE 1-12 DIGIT 1.87" DIA Original
P-112 Merrimac Industries POWER DIVIDER/COMBINER Original
P112 International Rectifier Power Diodes / Power Thyristors, Passivated Assembled Circuit Elements 25A Scan
P112 International Rectifier V(rrm): 600V, 25A passivated assembled circuit element. For power supplies, control circuits and battery chargers Scan
P1-12 Molectron Detector Pyroelectric Detector Scan
P112 N/A Short Form Datasheet and Cross Reference Data Scan
P112-000 Tripp Lite Between Series Adapters, Connectors, Interconnects, ADAPTER DB9F TO PS/2F Original
P11201 Senisys THRUBEAMS OEM Pair Scan
P1/120-M12 Semikron For studs and bridge rectifiers Original
P1-12H Molectron Detector Pyroelectric Detector Scan

P1-12

Catalog Datasheet MFG & Type PDF Document Tags

p112

Abstract: P-112 mA pS RMS pS RMS NOTE 1 TABLE 1.0 NOTE CW P112 133.33M 0427 P112 DESCRIPTION OPERATING , The Connor-Winfield P112 is a fixed frequency, surface mount Crystal Controlled Oscillator (XO , voltage, the P112 provides LVPECL Differential Outputs with Enable/Disable function. PECL OUTPUT , equivalent. 4) Duty Cycle measured at 50% of output swing. MAX ORDERING INFORMATION MAX CW P112 133.33M 0427 P112 - 133.33MHz LVPECL CLOCK SERIES CENTER FREQUENCY .059 MAX (1.5mm
Connor-Winfield
Original

P112

Abstract: P112 133.33M P112 DESCRIPTION OPERATING SPECIFICATIONS PARAMETER Center Frequency Total , NOMINAL MAXIMUM 0.3Vcc 10 UNITS Vdc Vdc uA TABLE 3.0 NOTE 2 2 - The Connor-Winfield P112 is a , low jitter and a ±25ppm overall stability. Operating at 2.5V supply voltage, the P112 provides LVPECL , . SURFACE MOUNT PACKAGE TAPE AND REEL PACKAGING MAX ORDERING INFORMATION MAX P112 - 133.33MHz
Connor-Winfield
Original
Abstract: : emmanuelle.briot@tmx.thomson-csf.com P112-R1.doc TMX P112 E. BRIOT : emmanuelle.briot@tmx.thomson-csf.com SAW Bandpass Filter WCDMA-IF TENTATIVE SPECIFICATION TMX P112 Package P112-R1.doc Aug. 8th 2000 page 3/3 rev. 1 , TBD C2 = TBD E. BRIOT : emmanuelle.briot@tmx.thomson-csf.com P112-R1.doc All information , TMX P112 SAW Bandpass Filter WCDMA-IF TENTATIVE SPECIFICATION All performances include , disclosed by the recipient to third party without the prior consent of THOMSON MICROSONICS. TMX P112 Thales Antennas
Original

p112

Abstract: P-112 0 POWER DIVIDERS / COMBINERS P-112 & P-152 1 to 400 MHz / 3-Way / Uniform Phase & Amplitude Bal. / Low Insertion Loss / Broadband / TO-5 PRINCIPAL SPECIFICATIONS Model Number Freq , . Typ. Dissip. P-112 1 - 200 1 - 100 100 - 200 25 25 30 30 1.2 1.2 0.7 0.7 , 0.2 1.3:1 0.3 1.5:1 1.2:1 35 mW 1.3:1 Package Outline of P-112/P-152 GENERAL SPECIFICATIONS , . Dimensions in inches over millimeters. General Notes: 1. The P-112/P-152 series 3-way Power Divider
Merrimac Industries
Original
P1521 112-P P-112/P-152

P817H

Abstract: GF9105ACQQ , 149, 158 GND Ground. 147, 148, 151-157, 159, 160, 1, 2 P112.0 Data Port No. 1: Depending on device configuration, P112.0 may operate as an input data port or an output data port. Note , .0 No Connect. 22 24 25 17 16 18 P112.0 Connect to VDD. Fig. 1 GF9105A Data Pin , P410.0 13 11 C2 P312.0 13 13 PROCESSING CORE INPUT P212.0 13 P112.0 PROCESSING CORE INPUT 13 13 P112.0 C7 } C8 GF9105A SIGNAL PROCESSING CORE Fig. 4d
GENNUM
Original
P817H GF9105ACQQ p612 P6120 ITU-R601 P212 GF9105 ITU-R-601 RP174 RP175 C-101

rvdt sensor

Abstract: rotary power head mechanical details see drawing P112-11 1.5 - 4.5 N approx. +5V dc nom. ± 0.5V, 10mA typ 20mA max 0.5-4.5V , List P112-11 Sensor Outline Drawings, in AutoCAD® dwg or dxf format, available on request. Do you , LIPS® P112 · · · · · · GAUGE HEAD POSITION SENSOR Position feedback for industrial and , sensor to suit a wide variety of applications. Our P112 LIPS® (Linear Induction Position Sensor) is an , . The P112, like all Positek sensors, provides a linear output proportional to displacement. Each sensor
Positek
Original
rvdt sensor rotary power head

HVF 12000

Abstract: SYMBOL VDD GND +5 V ±5% power supply. DESCRIPTION Ground. P112.0 Data Port No. 1: Depending on device configuration, P112.0 may operate as an input data port or an output data port. Note: When HVF , : Serial output for JTAG test data. Connect to VDD. No Connect. P112.0 147 148 151 152 153 154 155 , H F TDI CS P1 P1 P5 OUTPUT/INPUT = 0 OUTPUT/INPUT = 1 P112.0 P212.0 13 13 C1 13 13 13 P112.0 PROCESSING CORE INPUT 13 13 C1 C2 C3 PROCESSING CORE
GENNUM
Original
HVF 12000

P5120

Abstract: p88 3Y3 87, 89-95, 97-99 102-104, 106-112, 114 115-119, 122-128, 130 COEFF_PORT7.0 GND SYMBOL P112.0 DESCRIPTION Data Port No. 1: Depending on device configuration, P112.0 may operate as an input data port or , . 131-137, 139, 142-146 P212.0 2 GENNUM CORPORATION 521 - 88 - 04 P112.0 147 148 151 152 , OUTPUT/INPUT = 0 P112.0 P212.0 P312.0 P410.0 13 13 13 11 13 13 C2 13 C3 11 C4 C1 PROCESSING , 1 OUTPUT/INPUT = 1 P112.0 P212.0 P312.0 P410.0 13 13 13 11 13 13 13 C1 P112/HOUT
GENNUM
Original
P5120 p88 3Y3 P8100 P711 GENNUM DSP 160PIN

Application Notes

Abstract: atmel 830 (A1) P.78 P.112 P.124 P.162 I/O98, GCK7 (A1) P.78 P.112 P.124 P.162 PC84 , I/O33 GCK3 P.35 P.27 P.39 P.76 I/O66 GCK5 P.57 P.54 P.76 P.79 P.112 I/O98 GCK7 A1 P.78 P.79 P.112 PC84 VQ100 TQ144 PQ160 PC84 VQ100 , , I/O) P.78 P.79 P.112 P.124 I/O98 GCK7 A1 P.78 P.79 P.112 P.124 XC5206 , .110 GCK4 (A1, I/O) P.78 P.79 P.112 P.124 P.162 I/O146 GCK7 (A1) P.78 P.79 P.112
Atmel
Original
Application Notes atmel 830 atmel 432 atmel 936 XCS200 XCS200 FPGA AT40K XC4000 AT40K05 5K-10K AT40K10 10K-20K
Abstract: SYMBOL VDD GND +5 V ±5% power supply. DESCRIPTION Ground. P112.0 Data Port No. 1: Depending on device configuration, P112.0 may operate as an input data port or an output data port. Note: When HVF , : Serial output for JTAG test data. Connect to VDD. No Connect. P112.0 147 148 151 152 153 154 155 , 521 - 88 - 02 4 P5 P5 1 OUTPUT/INPUT = 0 OUTPUT/INPUT = 1 P112.0 P212.0 13 13 C1 13 13 13 P112.0 PROCESSING CORE INPUT 13 13 C1 C2 C3 PROCESSING CORE INPUT GENNUM
Original

lcd p113

Abstract: lcd 16 2 p113 -8EU92 GF-3BA20) P112 (GC-8EU93 GF-3BA21) P113 (GC-8EU94 GF-3BA22) P114 (GC-8EU95 GF-3BA23) VSS , /SI3 P111 P111/SO3 P112 P112/SCK3 P113 P113/TxD() P114 P114/RxD() VSS VDD , -A P110/SI3 P111/SO3 P112/SCK3 P113/TxD P114/RxD P115-P117 8-A S0-S23 17 COM0-COM3 18 UPD780B
-
Original
16KB32KB UPD78P064B UPD780308 UPD78P0308 GF-3BA40 P100-P103 lcd p113 lcd 16 2 p113 P110-P114 F400H P1-10 UPD78064/64BUPD780308 100QFP UPD78064/64B 512B1024B

P113 IR

Abstract: x0241 . P-112 PD A 54-12 S E R I E S . P-112 PDC54-11 S E R I E S . P-112 PD C 54-12 S E R I E S . P-112 PSA05-11 S E R I E S . P-112 P SA 0 5-1 2 S E R I E S . P-112 PSA08-11 S E R IE S . P-112 PSA 0 8-1 2 S E R I E S . P-112 PSA12-11 S E R I E S . P-112 PSA23-11 S E R I E S . P-112 PSA39-21 S E R I E S
-
OCR Scan
P113 IR x0241 AP1608P1 p113t 934l 96A8Y AA1114/2/CC AA9219/2 AM2520 AM2520EF/4 AM2520EG/4 2520EG/4

P112

Abstract: TEMEX TMX P112 SAW BANDPASS FILTER - WCDMA RX-IF Specification All performances include temperature variations Minimum Typical 600 Operating temperature range °C Maximum 200 (Balanced)(1) Source impedance Load impedance (Balanced)(1) ­20 +70 MHz , any time when necessary to provide optimum performance and cost. TEMEX TMX P112 SAW BANDPASS FILTER - WCDMA RX-IF Typical response 2 TEMEX TMX P112 SAW BANDPASS FILTER - WCDMA RX-IF
Temex
Original

dmo 465

Abstract: iC 458 REV. P1.1.2 GENERAL DESCRIPTION The Microprocessor Interface is used to configure the Framer in , www.exar.com áç XRT72L56 SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.2 , CONTROLLER PRELIMINARY REV. P1.1.2 TABLE OF CONTENTS GENERAL DESCRIPTION , . P1.1.2 TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR , REV. P1.1.2 RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18
Exar
Original
DS3-M13 dmo 465 iC 458 datasheet relay NAIS 5v 5 pin M25-A dmo 365 dmo 365 r DS3M13

dmo 465

Abstract: dmo 365 r REV. P1.1.2 GENERAL DESCRIPTION The XRT72L54, 4 Channel DS3/E3 Framer IC is designed to accept , www.exar.com áç XRT72L54 FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.2 , CONFIDENTIAL REV. P1.1.2 TABLE OF CONTENTS GENERAL DESCRIPTION , - I XRT72L54 FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.2 , CONFIDENTIAL REV. P1.1.2 RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19
Exar
Original
74hct00 A272 NAIS 210 RELAY relay NAIS 5v 5 pin 0X13 BIP 109

GR-253-CORE

Abstract: GR-499-CORE áç XRT73L02 PRELIMINARY 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT JUNE 2001 REV. P1.1.2 , www.exar.com áç XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 , PRELIMINARY REV. P1.1.2 TABLE OF CONTENTS General description , . 27 I áç XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 , . 39 II áç XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2
Exar
Original
GR-253-CORE GR-499-CORE PE-65966 PE-65967 PE-68629 T3001

Rx1302

Abstract: r4363 áç JANUARY 2001 PRELIMINARY XRT72L50 REV. P1.1.2 SINGLE CHANNEL DS3/E3 FRAMER IC WITH , XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.2 áç PRELIMINARY FIGURE 2 , PRELIMINARY XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.2 TABLE OF , BLOCK I XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.2 áç , REV. P1.1.2 RXE3 GC BYTE REGISTER (ADDRESS = 0X1B
Exar
Original
Rx1302 r4363 dmo 265

B628

Abstract: datasheet relay NAIS 5v 5 pin REV. P1.1.2 GENERAL DESCRIPTION The XRT72L58 Octal DS3/E3 Framer is designed to accept "User Data , XRT72L58 EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.2 FIGURE 2 , PRELIMINARY REV. P1.1.2 TABLE OF CONTENTS GENERAL DESCRIPTION , REV. P1.1.2 TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE , REV. P1.1.2 RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18
Exar
Original
B628 NAIS 414 TTB-11 octal tri state buffer ic CP Clare RELAY

P112

Abstract: darlington npn tip 102 TIP110 TIP111 TI P112 PHILIPS INTERNATIONAL SbE D â  711002b 0043550 224 â  PHIN T-33-Z SILICON DARLINGTON POWER TRANSISTORS N-P-N epitaxial-base transistors in monolithic Darlington circuit , turn-off time 5bE D 'cbo 'ceo EBO TIP110 TIP111 TIP112 TIP110 TIP111 TI P112 vCEOsust vCEOsust , \ s 100 150 Wc) Fig. 6 Power derating curve. I Tâ'"33â'"29 TIP110 TIP111 _TI P112 SbE D â , 841 This Material Copyrighted By Its Respective Manufacturer TIP110 TIP111 TI P112 PHILIPS
-
OCR Scan
TIP115 TIP116 darlington npn tip 102 T0-220AB MSA060-1 T-33-29 0D43S55

NAIS 210 RELAY

Abstract: ic 393 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept , XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.2 120 119 118 , CONTROLLER PRELIMINARY REV. P1.1.2 TABLE OF CONTENTS GENERAL DESCRIPTION , . P1.1.2 TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR , REV. P1.1.2 RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18
Exar
Original
ic 393 k 4213
Abstract: 87, 89-95, 97-99 102-104, 106-112, 114 115-119, 122-128, 130 COEFF_PORT7.0 GND SYMBOL P112.0 DESCRIPTION Data Port No. 1: Depending on device configuration, P112.0 may operate as an input data port or an output data port. Note: When HVF output is enabled H is always presented on P112 regardless of the , . 131-137, 139, 142-146 P212.0 2 GENNUM CORPORATION 521 - 88 - 04 P112.0 147 148 151 152 , 9 12 13 15 P112/HOUT P111 P110 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P212/VOUT P211 P210 P29 Micron Technology
Original
MT48LC2M32B2 PC100- 2M32B2
Abstract: REV. P1.1.2 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept , XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.2 120 119 118 , CONTROLLER PRELIMINARY REV. P1.1.2 TABLE OF CONTENTS GENERAL DESCRIPTION , . P1.1.2 TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR , REV. P1.1.2 RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 Eurofarad
Original
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