NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| OSC40 | Trak Microwave | 26.55 GHz VOLTAGE TUNED DRO |
1 pages, |
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| OSC40-1 | Ovenaire-Audio-Carpenter | DIVIDER XTAL OSCILLATOR |
2 pages, |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Analog Standard Cell OSC40 - CMOS Crystal Oscillator 40MHz DATA SHEET Process Description C35 (0.35m) OSC40 is a quartz crystal oscillator for a frequency range from 20 MHz to 40 MHz. ESD , crystal, connect it to the pins XIN and XOUT. Pad limited layout Symbol OSC40 may also be driven , Not Digital Page 1 of 3 Data Sheet OSC40 Â C35 TECHNICAL DATA FOR 3.3V SUPPLY (T , , 17-Mar-08 Page 2 of 3 Data Sheet OSC40 Â C35 Gm results for typ. XTAL Data HC49 XTAL DATA @ max ... | Original |
3 pages, |
OSC40 HC49 OSC40 abstract |
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| Abstract: , U13 1 OSC40 MHz U14 4 UCC5618 UCC5618 U15, U16, U17, U18 2 SMT_BEAD, 2743019447 L1 ... | Original |
28 pages, |
SYM53C875 scsi 68 connector pin assignment 272924 PE68515 IQ80960RP I960 DP83223 DP83840 ethernet transformer Application Note 120-pin scsi connector right angle 68 pin pcb SCSI connector HC1-TSE HC1TSE DP83840 abstract |
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| Abstract: 2 PE-68515 PE-68515 U8, U9 2 53C875 53C875 U12, U13 1 OSC40 MHz U14 4 UCC5618 UCC5618 U15 ... | Original |
28 pages, |
HC1-TSE 50 PIN SCSI connector manual ethernet switching Symbios Logic DP83223 DP83840 I960 IQ80960RP 120 pin scsi connector right angle 80 pin pcb SCSI connector 68 pin pcb SCSI connector scsi 68 connector pin assignment SYM53C875 datasheet abstract |
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| Abstract: analog input the OSC-40 provides step/direction or A/B quadrature inputs. The quadrature inputs can ... | Original |
25 pages, |
SMC 92 RS-232 to i2c converter TSSOP28 Analog rotary encoder SMO-40 Encoder CONTROLLERS SCHEMATIC SMC-40 rotary optical encoder schematic motor encoder lm339 pin diagram SMC D7 lm339 square wave MAX RS232 SMC-40 abstract |
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| Abstract: < > 9.1 9.2 9.3 9.4 9.5 General ... | Original |
57 pages, |
ph97 14 PIN IC HL-07 cn36 CN37 CN52 CN53 CN54 CN55 DVD player circuit diagram EPVP6200 14 PIN HL-07 IC dvd writer circuit diagram IC 7217 Unit COUNTER ph94 buffer 24V information about 14 PIN IC HL-07 datasheet abstract |
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| Abstract: STB Reference 5V REG STBY_IO OSC 1.0MHz PRE DRIVER SCP 450m OSCÃ-4000 ount ... | Original |
15 pages, |
FRA5097 GRM31CB GRM188B11A105KA61 BD8313 BD8312HFN 11027EDT04 BD8312HFN abstract |
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| Abstract: Octal, 10-Bit, 40 MSPS/65 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC AD9212 AD9212 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) ENOB = 9.8 bits SFDR = 80 dBc (to Nyquist) Excellent linearity DNL = �3 LSB (typical); INL = �4 LSB (typical) Serial LVDS (ANSI-644 ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range ... | Original |
56 pages, |
smd diode c640 smd c643 s m r707 r707 PIN CONFIGURATION R616 L607 l505 f701 diode c750 diode C722 diode C726 specification diode c649 MSPS/65 AD9212 MSPS/65 abstract |
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| Abstract: Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter AD9222 AD9222 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = �3 LSB (typical), INL = �4 LSB (typical) Serial LVDS (ANSI-644 ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port cont ... | Original |
60 pages, |
AN-835 AN-827 AN-742 AD9252 AD9222-65 AD9222-40 AD9222 c624 DIODE SMD R618 smd diode c644 s m r707 AD9212 ic an 7591 Diode smd code cm6 no c709 AD9222 abstract |
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| Abstract: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC AD9252 AD9252 8 analog-to-digital converters (ADCs) integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = �4 LSB (typical); INL = �5 LSB (typical) Serial LVDS (ANSI-644 ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 325 MHz, full-power analog bandwidth 2 V p-p input voltage range 1.8 V su ... | Original |
52 pages, |
AD9252 AD9222 AD9212 C749 C750 SMC transistor C618 SMD R618 s m r707 r707 no c709 L607 diode c746 diode C726 diode C725 AD8334 AD9252 abstract |
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| Abstract: 1-2) N = 10, 40 kHzf osc400kHz M ax Frequency Error at 25 °C: (JP2 1-2) M ax Frequency ... | Original |
11 pages, |
LTC6908-X LTC6906 LTC6905-XXX LTC6905 LTC6900 LTC1799 DIP8 socket osc20M DC814D DC814 LTC6907 DC814 abstract |
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| Abstract: PLL1045A PLL1045A 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A1 PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 1020 - 1070 MHz · Step Size: 30 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications VALUE UNITS 1020 - 1070 MHz RMS Phase Error (100 Hz - 100 KHz) 2.8 Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) -13 -70 ° dBc Power Output ... | Original |
2 pages, |
PLL1045A AN-202 AN-201 AN-200 PLL1045A abstract |
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| Abstract: PLL1000A PLL1000A 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 988 - 1028 MHz · Step Size: 1000 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications VALUE PERFORMANCE SPECIFICATIONS Frequency Range UNITS 988 - 1028 MHz RMS Phase Error (100 Hz - 100 KHz) 0.75 Harmonic Suppression (2nd, typ.) Sideband Spu ... | Original |
2 pages, |
PLL1000A AN-202 AN-201 AN-200 PLL1000A abstract |
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| Abstract: PSN2450A PSN2450A PHASE LOCKED LOOP 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 Rev A1 PHASE NOISE (1 Hz BW, typical) 0 -40 -80 FEATURES · Frequency Range: 2463 - 2465 MHz · Step Size: 1000 KHz · PLL - Style Package APPLICATIONS · Telecommunications · Satellite · Telemetry -120 -160 -200 100 Hz 1 kHz 10 kHz 100 kHz VALUE 2463 - 2465 UNITS MHz RMS Phase Error (100 Hz - 100 KHz) 1.25 Harmonic Suppression (2nd, typ.) ... | Original |
2 pages, |
PSN2450A LMX2326 AN-202 AN-201 AN-200 PSN2450A abstract |
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| Abstract: PSN0930A PSN0930A PHASE LOCKED LOOP 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 Rev A2 PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 900 - 960 MHz · Step Size: 100 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications VALUE 900 - 960 UNITS MHz RMS Phase Error (100 Hz - 100 KHz) 0.75 Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) -15 -65 ° dBc Power Output 3±2 ... | Original |
2 pages, |
PSN0930A LMX2316 AN-202 AN-201 AN-200 PSN0930A abstract |
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| Abstract: PSN1456A PSN1456A PHASE LOCKED LOOP 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 Rev A2 PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 1420 - 1490 MHz · Step Size: 1000 KHz · PLL - Style Package APPLICATIONS · Telecommunications · Satellite · Telemetry VALUE 1420 - 1490 UNITS MHz RMS Phase Error (100 Hz - 100 KHz) 0.75 Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) -20 -65 ° dBc Power Output 1±2 dBm ... | Original |
2 pages, |
PSN1456A LMX2326 AN-202 AN-201 AN-200 Fundamentals PSN1456A abstract |
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| Abstract: PLL2716A PLL2716A 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 2715 - 2717 MHz · Step Size: 1000 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications VALUE UNITS 2715 - 2717 MHz RMS Phase Error (100 Hz - 100 KHz) 1.25 Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) -20 -80 ° dBc Power Outp ... | Original |
2 pages, |
PLL2716A AN-202 AN-201 AN-200 PLL2716A abstract |
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| Abstract: PLL1070A PLL1070A 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 1055 - 1105 MHz · Step Size: 30 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications VALUE UNITS 1055 - 1105 MHz RMS Phase Error (100 Hz - 100 KHz) 2.5 Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) -12 -70 ° dBc Power Output ... | Original |
2 pages, |
PLL1070A AN-202 AN-201 AN-200 1055 PLL1070A abstract |
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| Abstract: PLL1100A PLL1100A 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A1 PHASE NOISE (1 Hz BW, typical) -60 -80 -100 FEATURES · Frequency Range: 1076 - 1130 MHz · Step Size: 50 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications -120 -140 -160 100 Hz 1 kHz 10 kHz 100 kHz VALUE UNITS 1076 - 1130 MHz RMS Phase Error (100 Hz - 100 KHz) 2.0 Harmonic Suppression ... | Original |
2 pages, |
PLL1100A AN-202 AN-200 AN-201 p 621 PLL1100A abstract |
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| Abstract: PSN1070A PSN1070A PHASE LOCKED LOOP 9939 Via Pasar · San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 Rev A PHASE NOISE (1 Hz BW, typical) FEATURES · Frequency Range: 1055 - 1105 MHz · Step Size: 30 KHz · PLL - Style Package APPLICATIONS · Basestations · Mobile Radios · Satellite Communications VALUE 1055 - 1105 UNITS MHz RMS Phase Error (100 Hz - 100 KHz) 2.5 Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) -12 -70 ° dBc Power Output ... | Original |
2 pages, |
PSN1070A LMX2316 AN-202 AN-201 AN-200 1055 PSN1070A abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| SPEED,25,"Frequency on XTAL1 (8XC196NU 8XC196NU 8XC196NU 8XC196NU 25 MHz) (Note 4)" v1,"SYSTEM SPECIFICATIONS - NORMAL VOLTAGE OTHER TIMINGS" tOSC,40,40,"1/SPEED (8XC196NU 8XC196NU 8XC196NU 8XC196NU 25 MHz)" v7,"" v6,"HOLD#/HLDA# TIMING SPECIFICATIONS" tHVCH,65,"HOLD# Setup Time (Note1)" tCLHAL,-15,15,"CLKOUT Low to HLDA# Low" tCLBRL,-15,15,"CLKOUT Low to BREQ# Low" tHALAZ,33,"HLDA# Low to Address Float" tHALBZ,25,"HLDA# Low to BHE#, INST - Osc. Freq. - 8XC196NU 8XC196NU 8XC196NU 8XC196NU 25 MHZ" tXLXL,"tOSC",40,40,"Oscillator Period" tXHXX,"[min(0.35*t www.datasheetarchive.com/download/37837815-173476ZC/196.zip (1.TLK) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| SPEED,25,"Frequency on XTAL1 (8XC196NU 8XC196NU 8XC196NU 8XC196NU 25 MHz) (Note 4)" v1,"SYSTEM SPECIFICATIONS - NORMAL VOLTAGE OTHER TIMINGS" tOSC,40,40,"1/SPEED (8XC196NU 8XC196NU 8XC196NU 8XC196NU 25 MHz)" v7,"" v6,"HOLD#/HLDA# TIMING SPECIFICATIONS" tHVCH,65,"HOLD# Setup Time (Note1)" tCLHAL,-15,15,"CLKOUT Low to HLDA# Low" tCLBRL,-15,15,"CLKOUT Low to BREQ# Low" tHALAZ,33,"HLDA# Low to Address Float" tHALBZ,25,"HLDA# Low to BHE#, INST - Osc. Freq. - 8XC196NU 8XC196NU 8XC196NU 8XC196NU 25 MHZ" tXLXL,"tOSC",40,40,"Oscillator Period" tXHXX,"[min(0.35*t www.datasheetarchive.com/download/51057172-260244ZC/196.zip (1.TLK) |
Intel | 26/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| AVLL,"[max(tOSC-20),]",42.50,"Address Setup to ALE Falling Edge" Hold ),]",68750,"Reset High to First PALE# Low" # Pulse Width" tAVLL1,0,"Address ),]",3125,"Data Hold Time" # Pulse Width" tPHLL,"[max(fOSC*120 PHPL,"[max(fOSC*120),]",7500,"PROG# High to Next PROG# Low" tPHIL,0,"PROG# High to AINC# Low" # Pulse Width" tILVH,"[max(fOSC*50),]",3125,"PVER# Hold after AINC# Low" t www.datasheetarchive.com/download/37837815-173476ZC/196.zip (16.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| ),]",105,"Address Setup to ALE Falling Edge" Hold after ALE Falling Edge" t SHLL,"[max(fOSC*1100),]",137500,"Reset High to First PALE# Low" # Pulse Width PLDX,"[max(fOSC*50),]",6250,"Data Hold Time" # Pulse Width" t # Low" # Pulse Width" tILVH,"[max(fOSC*50),]",6250,"PVER# Hold www.datasheetarchive.com/download/37837815-173476ZC/196.zip (8.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| ALE Falling Edge" Hold after ALE Falling Edge" t Setup Time" tPLDX,"[max(fOSC*50),]",8333,"Data Hold Time" ,"PROG# High to AINC# Low" # Pulse Width" tILVH,"[max(fOSC*50 = 125ns 12MHz = 83.33ns )" tSHLL,"[max(fOSC*1100),]",183326,"Reset High to First PALE# Low" # Pulse Width" tAVLL1,0,"Address Setup Time" tLLAX1,"[max(fOSC*50 www.datasheetarchive.com/download/37837815-173476ZC/196.zip (6.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| Edge" Hold after ALE Falling Edge" tLLRL,"[max(tOSC-35 ),]",68750,"Reset High to First PALE# Low" # Pulse Width" tAVLL1,0,"Address ),]",3125,"Data Hold Time" # Pulse Width" tPHLL,"[max(fOSC*120 PHPL,"[max(fOSC*120),]",7500,"PROG# High to Next PROG# Low" tPHIL,0,"PROG# High to AINC# Low" # Pulse Width" tILVH,"[max(fOSC*50),]",3125,"PVER# Hold after AINC# Low" t www.datasheetarchive.com/download/37837815-173476ZC/196.zip (16.TLK) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| ),]",80,"Address Setup to ALE Falling Edge" Hold after ALE Falling Edge" t SHLL,"[max(fOSC*1100),]",110000,"Reset High to First PALE# Low" # Pulse Width PLDX,"[max(fOSC*50),]",5000,"Data Hold Time" # Pulse Width" t # Low" # Pulse Width" tILVH,"[max(fOSC*50),]",5000,"PVER# Hold www.datasheetarchive.com/download/37837815-173476ZC/196.zip (10.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| Edge" Hold after ALE Falling Edge" tLLRL,"[max(tOSC-35 SHLL,"[max(fOSC*1100),]",91663,"Reset High to First PALE# Low" # Pulse Width PLDX,"[max(fOSC*50),]",4166.50,"Data Hold Time" # Pulse Width" t to AINC# Low" # Pulse Width" tILVH,"[max(fOSC*50 www.datasheetarchive.com/download/37837815-173476ZC/196.zip (12.TL) |
Intel | 25/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| AVLL,"[max(tOSC-20),]",42.50,"Address Setup to ALE Falling Edge" Hold ),]",68750,"Reset High to First PALE# Low" # Pulse Width" tAVLL1,0,"Address ),]",3125,"Data Hold Time" # Pulse Width" tPHLL,"[max(fOSC*120 PHPL,"[max(fOSC*120),]",7500,"PROG# High to Next PROG# Low" tPHIL,0,"PROG# High to AINC# Low" # Pulse Width" tILVH,"[max(fOSC*50),]",3125,"PVER# Hold after AINC# Low" t www.datasheetarchive.com/download/51057172-260244ZC/196.zip (16.TL) |
Intel | 26/03/1997 | 1374.08 Kb | ZIP | 196.zip |
| ),]",105,"Address Setup to ALE Falling Edge" Hold after ALE Falling Edge" t SHLL,"[max(fOSC*1100),]",137500,"Reset High to First PALE# Low" # Pulse Width PLDX,"[max(fOSC*50),]",6250,"Data Hold Time" # Pulse Width" t # Low" # Pulse Width" tILVH,"[max(fOSC*50),]",6250,"PVER# Hold www.datasheetarchive.com/download/51057172-260244ZC/196.zip (8.TL) |
Intel | 26/03/1997 | 1374.08 Kb | ZIP | 196.zip |