| Fulltext Datasheet Results |
1 - 50 of about 575 for ORCA |
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First line: Product Briefs ORCA ORT82G5 Field Programmable System-on-a-Chip (FPSC) ORCA ORT82G5 Evaluation Board ORCA ORT82G5 Design Kit. Article Reprints Abstract: .. Table of Contents. Product Briefs. ORCA ORT82G5 ORT82G5 – Field Programmable System-on-a-Chip FPSC .. 1. ORCA ORT82G5 ORT82G5 Evaluation .. Tags: ORT82G5 |
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First line: OC-48 FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 World's Fastest Programmable SERDES Solution! ORT82G5 Metro Access Applications OC-48c Port Card (ATM only) SONET/SDH Add/Drop Chip Layer Processor Parallel Interface ORCA ORT82G5 3.125Gbps Backplane Abstract: .. ORCA ORT82G5 ORT82G5 . High-Speed Backplane. 10 Gigabit Serial LAN 10 Gigabit Serial LAN. 10 Gb MAC. XAUI Backplane. XENPAK 70-Pin 70-Pin 10Gb 10Gb Transponder. XGMII. Protection. ORCA ORT82G5 ORT82G5 . Network Processor. ORCA ORT82G5 ORT82G5 .. Tags: OC-48 xaui SONET/SDH 8423 ORT82G5 |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 World's Fastest Programmable SERDES Solution! ORT82G5 Metro Access Applications OC-48c Port Card (ATM only) SONET/SDH Add/Drop Chip Layer Processor Parallel Interface ORCA ORT82G5 3.125Gbps Backplane Abstract: .. ORCA ORT82G5 ORT82G5 . High-Speed Backplane. 10 Gigabit Serial LAN 10 Gigabit Serial LAN. 10 Gb MAC. XAUI Backplane. XENPAK 70-Pin 70-Pin 10Gb 10Gb Transponder. XGMII. Protection. ORCA ORT82G5 ORT82G5 . Network Processor. ORCA ORT82G5 ORT82G5 .. Tags: ORT82G5 |
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First line: new ieee programs in vhdl and verilog Last Link ORCA® FPGA ExpressTM Interface Manual Abstract: .. Version 2002 1. Last Link Previous Next. ORCA ® FPGA ExpressTM Interface Manual. ispLEVER ® version 3.0. For Use With Synopsys ® FPGA ExpressTM version 3.5 or lower, ORCA 2002, and ispLEVER 2.0 and higher .. Tags: new ieee programs in vhdl and verilog datasheet abstract.. |
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First line: BTZ12 Last Link ORCA® Synopsys® Interface Manual Abstract: .. Version 2002 1. Last Link Previous Next. ORCA ® Synopsys ® Interface Manual. ispLEVER ® version 3.0. For Use With Synopsys ® FPGA CompilerTM or Design CompilerTM Version 1999.05, 1998.08, or higher .. Tags: BTZ12 datasheet abstract.. |
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First line: Last Link ORCA® Mentor GraphicsTM Interface Manual Abstract: .. Version 9.35 1. Last Link Previous Next. ORCA ® Mentor GraphicsTM Interface Manual. For Use With Leonardo SpectrumTM Version 2002a 2002a or higher , ORCA 4.0, and ispLEVER 2.0 or higher. Technical Support .. Tags: datasheet abstract.. |
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First line: Last Link ORCA® ExemplarTM Interface Manual Abstract: .. Version 9.35 1. Last Link Previous Next. ORCA ® ExemplarTM Interface Manual. ispLEVER ® version 3.0. For Use With Leonardo SpectrumTM Version 2002a 2002a or higher , ORCA 2002, and ispLEVER 2.0 or higher .. Tags: Exemplar Logic datasheet abstract.. |
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First line: Last Link ORCA® VHDL Simulation Manual Abstract: .. ORCA ® VHDL Simulation Manual. For Use With Synopsys ® FPGA ExpressTM version 3.5 or lower, Model Technology ® Modelsim/ PLUS Workstation ® 5.2 or higher Modelsim/VHDL Windows ® Version 4.7 or higher .. Tags: datasheet abstract.. |
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First line: Last Link ORCA® Synplicity® Interface Manual Abstract: .. Version 2002 1. Last Link Previous Next. ORCA ® Synplicity ® Interface Manual. For Use With Synplicity ® Synplify ® Version 6.2.4 or higher and ORCA 2002, and ispLEVER 2.0 and higher. Technical Support .. Tags: datasheet abstract.. |
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First line: ORCA® ORCA Properties Design Entry Desk Reference ispLEVER® version With ORCA 2002, ispLEVER higher Technical Support Line: 1-800-LATTICE 408-826-6002 (international) Last Link Abstract: .. ORCA ® ORCA Properties for Design Entry Desk Reference. ispLEVER ® version 3.0. For Use With ORCA 2002, and ispLEVER 2.0 and higher. Technical Support Line: 1-800-LATTICE 1-800-LATTICE or 408-826-6002 international .. Tags: datasheet abstract.. |
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First line: Last Link ORCA® Verilog® Simulation Manual Abstract: .. Version 4.1 1. Last Link Previous Next. ORCA ® Verilog ® Simulation Manual. For Use With Verilog ® Software XL-Version 2.6.36 or higher and ORCA 4.1, and ispLEVER 2.0 and higher. Technical Support Line .. Tags: datasheet abstract.. |
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First line: edit SR NOR latch abstract 16-bit multiplexer using xilinx Last Link ORCA® APPLICATION USER NOTES Abstract: .. Last Link Previous Next. ORCA ® APPLICATION USER NOTES. ispLEVER ® version 3.0. For Use With ORCA 2002, and ispLEVER 2.0 and higher. Technical Support Line: 1-800-LATTICE 1-800-LATTICE or 408-826-6002 international .. Tags: abstract 16-bit multiplexer using xilinx edit SR NOR latch CORE F5A datasheet abstract.. |
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First line: Exemplar Logic ATM-UTOPIA-Master-Core* odel Standards SiliconTM Product Brief UTOPIA Master Core V2.0 Abstract: .. • ORCA-specific optimization - tailor-made for high performance. • Ample design flexibility using control signals and VHDL generics. • Verified functionality and standards compliance. Figure .. Tags: ATM-UTOPIA-Master-Core* Exemplar Logic vhdl code download parallel interface vhdl 4 bit microprocessor using vhdl datasheet abstract.. |
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First line: ORCA Device Programming Download Cable Technical Note TN1009 Abstract: .. ORCA. Device Programming Download Cable. July 2002 Technical Note TN1009 TN1009 . ®. Introduction. The ORCA device family offers many programming options for device configuration. Users can easily incorporate .. Tags: TN1009 standard 6-pin JTAG header isplever* ATT ORCA fpga and/jtag cable TN1009 |
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First line: Advantages FLEX Versus Lucent ORCA Devices TECHNI 1997 produce best designs, programmable logic users focus device density, price, performance, availability. Compared with other high-density devices, devices offer high density, fast performance, prices, simple routing, high probability fitting. More Abstract: .. The Advantages of FLEX 10K Versus Lucent ORCA Devices. T E C H N I C A L B R I E F 3 1 O C T O B E R 1 9 9 7. M-TB-031-01 M-TB-031-01 . ALTERA MEGAFUNCTION PARTNERS PROGRAM. ®. To produce the best designs, programmable logic users .. Tags: datasheet abstract.. |
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First line: ORCA® Physical Design Rule Check (DRC) Desk Reference ispLEVER® version With ORCA 2001, ispLEVER higher Technical Support Line: 1-800-LATTICE 408-826-6002 (international) Last Link Abstract: .. ORCA ® Physical Design Rule Check DRC Desk Reference. ispLEVER ® version 3.0. For Use With ORCA 2001, and ispLEVER 2.0 and higher. Technical Support Line: 1-800-LATTICE 1-800-LATTICE or 408-826-6002 international .. Tags: datasheet abstract.. |
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First line: Using Lattice CPLD Flash Memory Configure SRAM-Based FPGA SRAM-based FPGA devices volatile require reconfiguration power-up cycles. FPGA external configuration data must held non-volatile device. systems incorporating microprocessor host computer system, configuration data stored system's local hard Abstract: .. Figure 1 shows a block diagram of the CPLD, Flash and ORCA. ®. FPGA device as. described in the reference design. This application note describes how a Lattice CPLD and Flash can work together to support .. Tags: multiple FPGA bitstream RD1017 |
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First line: Lattice ORCA® Products Lattice Semiconductor added line SRAM-based field-programmable gate array (FPGA) Field Programmable System-on-a-Chip (FPSC) devices comprehensive line in-system programmable logic solutions. Optimized Reconfigurable Cell Array (ORCA) FPGAs FPSCs offer designers unparallele Abstract: .. The Optimized Reconfigurable Cell Array ORCA FPGAs and FPSCs offer designers unparalleled perfor-mance and density for today’s demanding design challenges. ORCA Field-Programmable .. Tags: micropro datasheet abstract.. |
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First line: Introduction Lattice Digital Design Tools Lattice offers ispLEVER design tools CPLD, ispGDX® SPLD device design includes integrated FPGA FPSC device design. ispLEVERTM Abstract: .. an effective integrated solution for all Lattice devices, including ORCA. ®. Series 2/3/4, ORCA Series 4-based FPSC, ispLSI. ®. , ispMACHTM, MACH. ®. , ispGDX. ®. , ispGAL. ®. and GAL. ®. devices. This complete .. Tags: ispLEVER datasheet abstract.. |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT8850 8-Channel High-Speed Serial Backplane Driver Lattice developed solution designers need many advantages FPGA-based design implementation, coupled with high-speed serial backplane data transfer. Built ORCA® Series reconfigurable embedded system-on-a Abstract: .. ORCA ORT8850 ORT8850 F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P. Key Features and Benefits. â– High Performance ORCA Series 4 FPGA Gates: • Internal performance of > 250 MHz. • Up to 600K 600K usable system gates with .. Tags: 8423 ORT8850 |
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First line: BTZ12* Enclosed IBIS buffer models Buffers that programmed various sites ORCA type devices. These models make possible generate unique IBIS model chip design that created these devices. unique IBIS model must created each customized ORCA design because each design contains unique combination Buffer Abstract: .. programmed at various pin sites in ORCA type devices. These models make it possible to generate the unique IBIS model for any chip design that can be created in these devices. A unique IBIS model .. Tags: BTZ12* BMZ12FPU BTZ12FPU |
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First line: ORCA® FPGA Powerup Recommendations ORCA FPGAs CMOS static (SRAM) based programmable logic devices. circuitry that user designs FPGA implemented within FPGA setting multiple SRAM configuration memory cells. This unique structure compared with typical CMOS circuits lends itself having certain powe Abstract: .. Application Note September 1998. ORCA ® FPGA. Powerup Recommendations. Introduction. ORCA FPGAs are CMOS static RAM SRAM based programmable logic devices. The circuitry that the user designs .. Tags: SPE 316 Power Supply 3C80 datasheet abstract.. |
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First line: Last Link Field Programmable Systems Chip (FPSC) Simulation/Synthesis Guide Abstract: .. Chapter 2 ORCA FPSC/SYNTHESIS INTERFACE. OVERVIEW ..2-1. SOFTWARE .. Tags: Synplify datasheet abstract.. |
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First line: data entry online job ispLEVER Installation Release Notes Technical Support Line: 1-800-LATTICE (408) 826-6002 Update: view most current version this document, www.latticesemi.com. LEVER-WS-RN v3.0.0 Abstract: .. , ispSVF, ispTURBO, ispVIRTUAL MACHINE, ispVM, LINE2AR, MACH, MMI logo , ORCA, PAC, PAC-Designer, PAL, PALCE, Performance Analyst, Silicon Forest, Speedlocked, Speed Locking, SuperBIG .. Tags: data entry online job PALCE isplsi databook ispLEVER project Navigator ispLEVER datasheet abstract.. |
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First line: MUX/deMUX Core Family Abstract: .. â– ORCA ® specific optimization—tailor-made for high performance. â– Ample design flexibility using control signals and. VHDL generics. â– Verified functionality and standards compliance. 0376 .. Tags: datasheet abstract.. |
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First line: UTOPIA Slave Core V2.0 Abstract: .. — Internal 128 × 9/64 × 17 ORCA ® FIFOs scal-able â– Flexible control inputs with options for the follow-ing: — Internal/external hardwiring — Access via a parallel or serial microprocessor .. Tags: datasheet abstract.. |
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First line: intel 8098 ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four Channel Mbits/s Backplane Transceiver Lattice Semiconductor developed solution designers need many advantages FPGAbased design implementation, coupled with highspeed serial backplane data transfer. Mbits/ backplane transceiver o Abstract: .. Product Brief January 2002. ORCA. ®. ORT4622 ORT4622 Field-Programmable System Chip FPSC Four Channel x 622 Mbits/s Backplane Transceiver. Introduction. Lattice Semiconductor has developed a solution .. Tags: intel 8098 ADM processor ORT4622 |
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First line: Constraining ORCA Designs Abstract: .. In ORCA devices and the ORCA Foundry design flow, device constraints are referred to as preferences. Preferences can be handled at multiple points in the ORCA Foundry design flow. This application .. Tags: 10.000000* TN1012 |
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First line: ORCA® Series Programmable Clock Manager (PCM) FPGA designs continue increase size, speed, complexity, need system-level functions becomes extremely important maintain time-to-market advantage that inherent with FPGAs. With introduction such items embedded microprocessor interfaces, programmable Abstract: .. ORCA. Series 3 programmable clock manager PCM is a special function block that is used to mod-ify or condition clock signals for optimum system per-formance. To accommodate various applications .. Tags: datasheet abstract.. |
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First line: ORCA® Series FPGAs Master (with Target) Applications Lucent Technologies Microelectronics Group developed Verilog1 implementation peripheral component interface (PCI) master/target controller. Because implemented Verilog, code synthesized into ORCA OR2CxxA/OR2TxxA Series FPGAs Series FPGAs. This Abstract: .. ORCA ® Series FPGAs in PCI Bus Master with Target Applications. Product Brief August 2000. Introduction. Lucent Technologies Microelectronics Group has developed a Verilog 1 implementation .. Tags: verilog code for pci verilog code pci master verilog code intel 865 OR2CxxA OR2TxxA OR2T15A OR3T80 |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT8850 850Mbits/s SERDES Plus 899K FPGA Gates Chip! Making Right Choice Abstract: .. ORCA ORT8850 ORT8850 F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P. 8 x 850Mbits 850Mbits /s SERDES Plus up to 899K 899K FPGA Gates on One Chip! Evaluation Board. Making the Right Choice Choosing the right backplane transceiver .. Tags: ORCA ORT8850 8423 ORT8850 |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 Evaluate 3.7Gbps SERDES FPGA Quickly Easily Making Right Choice. Abstract: .. ORCA ORT82G5 ORT82G5 F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P. Evaluate 3.7Gbps SERDES + FPGA Quickly and Easily. Evaluation Board. ORCA ORT82G5 ORT82G5 . SERDES A. SERDES B. CHAR I/O. MPI INT. GP I/O. HSI. Mode Cont. Serial .. Tags: ORT82G5 |
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First line: J119* J101 J119 j78 transistor J119 transistor OR4E6 Evaluation Board Tutorial This tutorial will assist first-time users ORCA OR4E FPGA evaluation board understand device features well capabilities evaluation board. tutorial, user must have installed copy ORCA Foundry 2001 software understanding OR Abstract: .. Overview This tutorial will assist first-time users of the ORCA OR4E FPGA how to use the evaluation board to understand the device features as well as the capabilities of the evaluation board. .. Tags: J119 transistor j78 transistor J78 datasheet J119* J101 Datasheet j59 TN1009 |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORLI10G Making Right Choice. Abstract: .. ORCA ORLI10G ORLI10G F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P. Measure the Performance of a 10Gbits 10Gbits /s Integrated Data Communication Solution. Evaluation Board. Making the Right Choice.. Choosing the .. Tags: 8423 ORLI10G |
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First line: RFCMOS Case Study: Orca Systems' 1st-pass Functional Silicon Success with Fujitsu CMOS 90nm Technology "When you're designing type digital architecture, it's vital know that final silicon will match simulation results. results with Fujitsu's 90nm close simulated. silicon works expected. technol Abstract: .. C A S E S T U D Y. RFCMOS Case Study: Orca Systems’ 1st-pass Functional Silicon Success with Fujitsu CMOS 90nm 90nm Technology. “When you’re designing a new type of digital architecture, it’s vital to know .. Tags: datasheet abstract.. |
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First line: ispLEVER Tutorials Synthesis Design with Synplify: ORCA Flow Synthesis Design with Synplify: ORCA Flow Task Create Project.3 Task Target Device Task Create Synplify Project Task Verilog Source Files.9 Task Implementation Options.11 Task Import EDIF File into Your Project Task Design Task Place Route Abstract: .. ispLEVER Tutorials. HDL Synthesis Design with Synplify: ORCA Flow. Table of Contents HDL Synthesis Design with Synplify: ORCA Flow .. .. Tags: datasheet abstract.. |
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First line: ORCA Series Boundary Scan August 2004 Application Note AN8073 increasing complexity integrated circuits packages increased difficulty testing printed-circuit boards. integrated circuits become more complex, testing loaded board most difficult tasks design cycle. Advanced package technology need deve Abstract: .. ORCA Series Boundary Scan. August 2004 Application Note AN8073 AN8073 . Introduction. The increasing complexity of integrated circuits and packages has increased the difficulty of testing printed-circuit .. Tags: psri* ORCA* AN8073 |
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First line: ic 747 Using ispPAC30 Monitor Temperature ORCA-4 FPSC IC's achieve reliable operation modern, complex digital logic chips such Lattice Semiconductor's ORCA®-4 Field-Programmable Gate Arrays (FPGAs) Field-Programmable System Chips (FPSCs) often requires that monitor actual temperature device, tak Abstract: .. Using the ispPAC30 ispPAC30 to Monitor Die Temperature in the ORCA-4 and FPSC IC’s. April 2002 Application Note AN6033 AN6033 . Introduction. To achieve reliable operation of modern, complex digital logic chips .. Tags: ic 747 AN6033 |
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First line: Lucent SLC 2000 intel 8098 ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four Channel Mbits/s Backplane Transceiver Lucent Technologies Microelectronics Group developed solution designers need many advantages FPGA-based design implementation, coupled with high-speed serial backplane data t Abstract: .. Product Brief May 2000. ORCA ® ORT4622 ORT4622 Field-Programmable System Chip FPSC Four Channel x 622 Mbits/s Backplane Transceiver. Introduction. Lucent Technologies Microelectronics Group has .. Tags: intel 8098 Lucent SLC 2000 intel 865 ORT4622 |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORLI10G Ultimate Programmable 10Gbits/sec Data Solution Data Over Fiber Made Easy Lattice's ORLI10G ORCA® Series based Field Programmable System Chip (FPSC) which combines high-speed line interface with flexible FPGA logic core. Built Series reconfigurabl Abstract: .. ORCA ORLI10G ORLI10G F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P. Data Over Fiber Made Easy .. Lattice’s ORLI10G ORLI10G is an ORCA ® Series 4 based Field Programmable System Chip FPSC which combines a high-speed .. Tags: STM-16 Architecture Ethernet-MAC ORLI10G |
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First line: S240 ci 7495 ci 555 ORCA® Series Field-Programmable Gate Arrays Abstract: .. Product Brief April 1999. ORCA ® Series 2. Field-Programmable Gate Arrays. Features. â– High-performance, cost-effective, low-power. 0.35 μm CMOS technology OR2CxxA , 0.3 μm CMOS technology OR2TxxA .. Tags: S240 S304 OR2C40A Dual Four-Input OR Gate CI -dp904c ci 7495 ci 555 BC432 datasheet abstract.. |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 Evaluate 3.7Gbps SERDES FPGA Quickly Easily Making Right Choice. Abstract: .. 3. ORCA ORT82G5 ORT82G5 F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P. Evaluate 3.7Gbps SERDES + FPGA Quickly and Easily. Evaluation Board. ORCA ORT82G5 ORT82G5 . SERDES A. SERDES B. CHAR I/O. MPI INT. GP I/O. HSI. Mode Cont. Serial .. Tags: rt82* 8423 ORT82G5 |
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First line: BR03 bc600 br06* BR08 ORCA® Series Field-Programmable Gate Arrays Abstract: .. Product Brief April 1999. ORCA ® Series 3C and 3T Field-Programmable Gate Arrays. Features. â– High-performance, cost-effective, 0.35 μm and 0.3 μm. 4-level metal technology 4- or 5-input look-up .. Tags: BR08 br06* bc600 BR03 pic 123 intel 865 BL05 datasheet abstract.. |
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First line: cell broadband odel Standards SiliconTM Product Brief Multi-Channel Core Abstract: .. • Lucent Technologies ORCA Foundry for FPGA layout. Additional Resources. • ORCA ATM Physical Layer CSC Application Note AP97-050FPGA AP97-050FPGA available from Lucent Technologies • ORCA OR2CxxA and .. Tags: cell broadband datasheet abstract.. |
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First line: UTOPIA Slave Bridge Abstract: .. â– ORCA ® specific optimization—tailor made for high performance. â– Verified functionality and standards compliance. 0375 F Figure 1. ATM UTOPIA Slave Bridge Application. Description. The ATM .. Tags: UTOPIA Level 3 atm forum bench 2800 datasheet abstract.. |
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First line: TN1010 ORCA Design Floorplanning Technical Note TN1010 Abstract: .. floorplanning is, when it should be used, and how it is done with respect to ORCA FPGA/FPSC designs. This document is divided into four major sections: • Floorplanning definition, logical and .. Tags: TN1010 TN1010 |
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First line: ispLEVER Tutorials Synthesis Design with LeonardoSpectrum: ORCA Flow Synthesis Design with LeonardoSpectrum: ORCA Flow Task Create Project.3 Task Target Device Task Start LeonardoSpectrum from ispLEVER Task Quick Setup Synthesize Design.9 Task Import EDIF File into Your Project Task Design Task Plac Abstract: .. ispLEVER Tutorials. HDL Synthesis Design with LeonardoSpectrum: ORCA Flow. Table of Contents HDL Synthesis Design with LeonardoSpectrum: ORCA Flow .. .. Tags: datasheet abstract.. |
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First line: AW12 transistor d115 ORCA Series Quad-Port Embedded Block ORCA Series FPGA platform provides embedded block (EBR) macrocells compliment it's distributed RAM. using ORCA Series EBR, designers realize benefits system-on-a- chip (SoC) intellectual property (IP) reuse quickly deliver their product marke Abstract: .. ORCA Series 4 Quad-Port Embedded Block RAM. April 2002 Technical Note TN1016 TN1016 . Introduction. The ORCA Series 4 FPGA platform provides embedded block RAM EBR macrocells to compliment it’s distributed .. Tags: transistor d115 AW12 Synplify* Q110 Q016 q011 TN1016 |
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First line: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORT82G5/42G5 Abstract: .. ■High Performance ORCA Series 4 FPGA Gates: • Internal performance of > 250 MHz. • Over 10,000 Lookup Tables. • 1.5V operation 30% less power than 1.8V operation • Comprehensive I/O selections .. Tags: xaui smps 500W bl9148 10 gbps transceiver board 10 gbps transceiver ORT82G5 42G5 |
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First line: free vhdl code download for pll palce programming Guide ddr ram repair pdf ispLEVER Release Notes Technical Support Line: 1-800-LATTICE (408) 826-6002 Update: view most current version this document, www.latticesemi.com. LEVER-RN 3.0.0 Abstract: .. , ispSVF, ispTURBO, ispVIRTUAL MACHINE, ispVM, LINE2AR, MACH, MMI logo , ORCA, PAC, PAC-Designer, PAL, PALCE, Performance Analyst, Silicon Forest, Speedlocked, Speed Locking, SuperBIG .. Tags: ddr ram repair pdf palce programming Guide free vhdl code download for pll OT31 Intel 8237A datasheet abstract.. |
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