500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
2N4392 Central Semiconductor Corp Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET, TO-18, visit Digikey Buy
U441 Vishay Siliconix Small Signal Field-Effect Transistor, N-Channel, Junction FET, visit Digikey Buy
2N4858A Atmel Corporation Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET, TO-206AA visit Digikey Buy
U440 Vishay Siliconix Small Signal Field-Effect Transistor, N-Channel, Junction FET, visit Digikey Buy
2N4393 Central Semiconductor Corp Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET, TO-18, visit Digikey Buy
U430 Vishay Siliconix Small Signal Field-Effect Transistor, N-Channel, Junction FET visit Digikey Buy
2N4393 Atmel Corporation Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET, TO-206AA visit Digikey Buy
U290 Atmel Corporation Small Signal Field-Effect Transistor, 30V, 1-Element, N-Channel, Silicon, Junction FET, TO206AA(TO18),TO206AC(TO52) visit Digikey Buy
2N4858A Central Semiconductor Corp Small Signal Field-Effect Transistor, 40V, 1-Element, N-Channel, Silicon, Junction FET, TO-18, visit Digikey Buy
2N4392 Atmel Corporation Small Signal Field-Effect Transistor, 40V, 1-Element, N-Channel, Silicon, Junction FET, TO206AA(TO18), TO206AC(TO52) visit Digikey Buy
2N5433 Atmel Corporation Small Signal Field-Effect Transistor, 25V, 1-Element, N-Channel, Silicon, Junction FET, TO206AA(TO18), TO206AC(TO52) visit Digikey Buy
2N4340 Atmel Corporation Small Signal Field-Effect Transistor, 50V, 1-Element, N-Channel, Silicon, Junction FET, TO206AA(TO18), TO206AC(TO52), TO206AF(TO-72) visit Digikey Buy

N Channel Junction FET

Catalog Datasheet MFG & Type PDF Document Tags

2SK1479

Abstract: 2SK1479 Silicon N Channel Junction FET Low Frequency Impedance Converter Features MPAK · Small input capacitance. (Ciss = 3.2 pF typ.) · High |yfs|, small power loss. (|yfs| 3.5 mS typ.) · Suitable for electric condencer Mic impedance converter. Table 1 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit -­ Gate to drain voltage VGDO , -­ Channel power dissipation Pch 100 mW -­ Channel
Hitachi Semiconductor
Original

FET 2N5459

Abstract: fet 2n5457 Datasheet 2N545/ 2N5458 2N5459 wencrai N CHANNEL FET aemicunaunur %iirpa 145 Adams Avenue , World Class Discrete Semiconductors The CENTRAL SEMICONDUCTOR 2N5457 series types are Silicon N Channel Junction FET's designed for switching and amplifier applications. MAXIMUM RATINGS (Ta=25°C unless otherwise noted) SYMBOL Drain - Source Voltage D ra i n - Gate Vol tage Gate - Source Voltage Gate Current Power Dissipation Operating and Storage Junction Temperature ELECTRICAL
-
OCR Scan
FET 2N5459 fet 2n5457 2N545 FET 2N5458 to92 fet p channel N Channel FET to92 2N5A57 2N5A58

2n5555 Vgs(off)

Abstract: CS 150 10v centralâ"¢ semiconductor corp. 145 Adams Avenue Hauppauge, New York 11 788 ♦I 2N5555 N-CHANNEL FET JEDEC TO-92 CASE DESCRIPTION The CENTRAL SEMICONDUCTOR 2N5555 type is an Silicon N Channel Junction FET designed for switching, RF amplifier and mixer applications where low capacitance is desired. MAXIMUM RATINGS(TA=25°C unless otherwise noted) SYMBOL Gate-Source Voltage Drain-Source Voltage Drain-Gate Voltage Gate Current Power Dissipation Operating and Storage Junction Temperature GS VDS VDG 'G
-
OCR Scan
2n5555 Vgs(off) CS 150 10v

FET electret microphone

Abstract: 5v electret TF202 N- channel Junction FET Electret Condenser Microphone TENTATIVE Features ·Especially suited for use in electret condenser microphone. ·TF202 is possible to make applied sets smaller and Slimmer. ·Excellent voltage characteristics. ·Excellent transient characteristics. ·Adoption of FBET process. Absolute Maximum Ratings/Ta=25°C Gate to Drain Voltage Gate Current Drain Current Allowable Power Dissipation Junction Temperature Storage Temperature VGDO IG ID PD Tj Tstg ­20 10 1 100 150 ­55to+150 min ­20
SANYO Electric
Original
FET electret microphone 5v electret 980907TM2

2SK1532

Abstract: Low frequency amplifier 2SK1532 Silicon N Channel Junction FET Low Frequency Amplifier, Analog Switching Features CMPAK · Suitable for low frequency amplifier, variable resistance and analog switching circuit of audio equipment. · Compact packages. Table 1 Absolute Maximum Ratings (Ta = 25°C) Item Symbol , current ID 10 mA -­ Channel power dissipation Pch 100 mW -­ Channel temperature Tch 150 °C -­ Storage
Hitachi Semiconductor
Original
Low frequency amplifier

2SK1479

Abstract: HITACHI 2SK1479- - Silicon N Channel Junction FET Low Frequency Impedance Converter Features · Small input capacitance. (Ciss = 3.2 pF typ.) · High lyfsl, small power loss. (Iyfsl 3.5 mS typ.) · Suitable for electric condencer Mic impedance converter. M PA K Table 1 Absolute Maximum Ratings (Ta = 25°C) Item Gate to drain voltage Gate to source voltage Drain current Gate current Channel power dissipation Channel temperature Storage temperature Symbol Rating -25 -25 5 5 100 150 -5 5 t o
-
OCR Scan
2SK1479-------

2SK1532

Abstract: H ITACHI 2SK1532-Silicon N Channel Junction FET Low Frequency Amplifier, Analog Switching Features · Suitable for low frequency amplifier, variable resistance and analog switching , to drain voltage Gate to source voltage Drain current Channel power dissipation Channel temperature , C XDC 1.2 to 3.0 D XDD 2.6 to 6.5 H ITACH I 2SK1532 í ' - M axim um ch a n n e l d issipa tion curve Typical o u tp u t c h a ra cte ristics . ? c . < i: N \ a c S
-
OCR Scan
2SK1532-------------S

marking E5

Abstract: FET electret microphone TS788 N- channel Junction FET Electret Condenser Microphone TENTATIVE Features · Especially suited for use in electret condenser microphone. · TS788 is possible to make applied sets smaller and Slimmer. · Excellent voltage characteristics. · Excellent transient characteristics. · Adoption of FBET process. Absolute Maximum Ratings / Ta=25°C unit VGDO IG ID PD Tj Tstg Gate to Drain Voltage Gate Current Drain Current Allowable Power Dissipation Junction Temperature Storage
SANYO Electric
Original
marking E5 markingE4 971128TM2

XR2271

Abstract: XR-2271 output pull down resistance is an N channel junction FET. For Vo * V - it is resistive, and for |Vo (V - , EXAR CORP XR-494 91D 04470 D NON-INV , H * O S DEAD TIME 4 f T T CONTROL 1 11 I cT s r r n l i - i . . OUTPUT 11 I CONTROL Z013 + , Current, Peak ± 100 mA Power Dissipation Ceramic (N) Package 1.0 Watt Derate Above + 25°C 6.7 mW/°C
-
OCR Scan
XR-2271 XR2271 XR2271CP XR 2271 1468cn 12V fluo XR-1568 XR-1568M XR-1568N XR-1468CN XR-1568/XR-1468C

P-Channel Depletion Mosfets

Abstract: shockley diode form a semiconductor junction on the channel of a FET to achieve gate control of the channel current , field-effect transistors). Junction FETs are inherently depletion-mode devices, and are available in both n , also exist as both n- and p-channel devices. The two main FET groups depend on different phenomena for , junction formed along the channel. Implicit in this description is the fundamental difference between JFET , Channel N-Drain S D P N Depletion Layer P N-Channel P-Gate G Final form taken by
Siliconix
Original
P-Channel Depletion Mosfets shockley diode P-Channel Depletion Mode FET shockley diode application shockley diode datasheet n channel depletion MOSFET AN101

P-Channel Depletion Mode FET

Abstract: p channel depletion mosfet Channel NDrain S D P N Depletion Layer P NChannel PGate Final form taken by FET with ntype channel embedded in ptype substrate. Figure 2. Idealized Structure of An NChannel Junction , to form a semiconductor junction on the channel of a FET in order to achieve gate control of the , enhancement and depletion modes, and also exist as both n and pchannel devices. The two main FET groups , . FET Family Tree (07/11/94) 1 AN101 Siliconix In addition to the channel material, a JFET
Temic Semiconductors
Original
p channel depletion mosfet an101 siliconix N-Channel JFET FETs JFETs Junction FETs Junction FETs JFETs list of n channel fet

p channel depletion mosfet

Abstract: list of n channel fet to form a semiconductor junction on the channel of a FET in order to achieve gate control of the , junction formed along the channel. Implicit in this description is the fundamental difference between JFET , Figure 1. FET Family Tree Siliconix 11-Jul1­94 1 AN101 In addition to the channel material, a , which the maximum IDSS flows. VDS < VP Channel S N-Source D P N N-Drain Depletion Layer P G N-Channel P-Gate Final form taken by FET with n-type channel embedded in p-type
Temic Semiconductors
Original
Depletion MOSFET 6D list of n channel MOSFET P-Channel Depletion Mode Field Effect Transistor depletion p mosfet list of fet Depletion MOSFET

P-Channel Depletion Mode FET

Abstract: P-Channel Depletion Mosfets Cross-Section N­ Source Gate The lateral DMOS FET differs radically in its channel construction when , field-effect transistors). Junction FETs are inherently depletion-mode devices, and are available in both n , also exist as both n- and p-channel devices. The two main FET groups depend on different phenomena for , junction formed along the channel. Implicit in this description is the fundamental difference between JFET , which the maximum IDSS flows. VDS < VP N-Source N-Drain Channel S D P N Depletion
Temic Semiconductors
Original
P-Channel Depletion mosFET Siliconix JFET application note shockley depletion n channel mosfet diode shockley N-Channel depletion mos

2N3797

Abstract: MPF102 equivalent transistor TRANSISTORS (MOSFET) P (SUBSTRATE) P L CHANNEL CHANNEL LENGTH Figure 3. Junction FET with , oxide layer serves as a protective coating for the FET surface and to insulate the channel from the , + ­­­­­­­­­ N+ N+ INDUCED CHANNEL P (SUBSTRATE) Figure 5. Channel Enhancement , . Notice that for the junction FET, drain current may be enhanced by forward gate voltage only until the gate-source p-n junction becomes forward biased. The third type of FET operates only in the enhancement
Motorola
Original
2N3797 MPF102 equivalent transistor mpf102 fet MPF102 JFET 2N3797 equivalent 2N4221 motorola AN211A/D AN211A

AN211A

Abstract: MPF102 JFET P-CHANNEL MOSFET ID N MOS FIELD-EFFECT TRANSISTORS (MOSFET) P (SUBSTRATE) P L CHANNEL CHANNEL LENGTH Figure 3. Junction FET with Single-Ended Geometry SOURCE N P (SUBSTRATE) (a) OXIDE , JFET SOURCE JUNCTION FIELD-EFFECT TRANSISTOR (JFET) P P SOURCE N DRAIN N , + ­­­­­­­­­ N+ N+ INDUCED CHANNEL P (SUBSTRATE) Figure 5. Channel Enhancement , . Notice that for the junction FET, drain current may be enhanced by forward gate voltage only until the
Motorola
Original
MPF102 Transistor MPF102 JFET data sheet mpf102 equivalent P channel depletion mode fet JFET TRANSISTOR REPLACEMENT GUIDE mpf102 equivalent

MPF102 JFET

Abstract: motorola AN211A current in the 2 GATE P (SUBSTRATE) P L CHANNEL CHANNEL LENGTH Figure 3. Junction FET with Single-Ended Geometry SOURCE DRAIN N N P (SUBSTRATE) P (SUBSTRATE) (a , - N+ INDUCED CHANNEL N+ Freescale Semiconductor, Inc. P (SUBSTRATE) Figure 5 , large gate voltages. Notice that for the junction FET, drain current may be enhanced by forward gate voltage only until the gate-source p-n junction becomes forward biased. The third type of FET operates
Motorola
Original
motorola AN211A 2N4221 MOTOROLA POWER TRANSISTOR MPF102 circuit application JFET with Yos 2N4351 MOTOROLA igfet

MPF102 equivalent transistor

Abstract: MPF102 JFET into the channel until they meet, È È È È È È N (a) (-) P P N DRAIN SOURCE ÈÇÇÈ ÇÇÇ ÇÇÇ È , ËËËËËËËË ËËËË ËËËËËËËË ËËËË ËËËËËËËË ËËËË ËËËËËËËË ËËËË P P (SUBSTRATE) ID N P L CHANNEL LENGTH MOS , for the FET surface and to insulate the channel from the gate. However, the oxide is subject to , connected back to back. Figure 3. Junction FET with Single-Ended Geometry http://onsemi.com 2 , EnhancementMode MOSFET ÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍ N+ N+ Figure 5. Channel Enhancement. Application of
ON Semiconductor
Original
2N4351 mpf102 application note 2N5458 equivalent equivalent to MPF102 Transistors MPF102 n-channel MFE2012

P-Channel Depletion Mode FET

Abstract: P-Channel Depletion-Mode necessary to form a semiconductor junction on the channel of a FET in order to achieve gate control of the , incorporated 6-10 Junction FET Capacitances Associated with the junction between the gate and the channel of a , enhancement or depletion modes, and exist as both N- and P-Channel devices. The two main FET groups depend on , a reverse-biased PN junction formed along the channel. Implicit in this description is the fundamental difference between FET and bipolar devices: when the FET junction is reverse-biased the gate
-
OCR Scan
P-Channel Depletion-Mode FET E202 2N3631 2N3823 2N2606 2N3329

fZ80

Abstract: C5750X7R1H106M dual-phase, single output regulator. The output of each channel can be independently adjusted from 1.3V to , response to fast load transients. Current is sensed across either the Vds of the top FET or across an external currentsense resistor connected in series with the drain of the top FET. The LM5642 features , soft-start behavior more predictable and controllable than traditional soft-start circuits. n n n n n , off time for the IC during an output under-voltage event. n n n n n n n n n n n n n n
National Semiconductor
Original
LM5642X fZ80 C5750X7R1H106M AN-1229 LM5642MTC LM5642XMT LM5642/LM5642X CSP-9-111C2 CSP-9-111S2
Abstract: INTEGRATED CIRCUIT TPD7000F 4-CHANNEL LOW -SIDE POW ER M O S FET DRIVER TPD7000F is a power MOS FET driver for low-side switching. This 4-channel driver with a built-in circuit is used to monitor the voltage between the MOS FET drain and source for each channel and to output the state of the power MOS FET. FEATURES â'¢ Low-side N-channel power MOS FET driver (input capacitance: 15nF Max). â'¢ Incorporates a power MOS FET overcurrent protection function. â'¢ Incorporates induction load energy -
OCR Scan
961001EBA2 SSOP24-P-300-1

pnp transistor 800v

Abstract: current o f the MOS FET. R n - cmod ) is conductivity m odulated N~ layer resistance. R ch is the channel , ing the electric field. The breakdow n will then occur in the internal junction rather than on the , electric field thus be comes stronger near the junction surface, caus ing a breakdow n in the NPN , MOS FET chip base 91 the IGBT is finally enabled. To disable the IGBT, the channel is closed , Figure 8, after the MOS FET channel is opened, a hole (m inority carrier) is driven in from the P+ chip
-
OCR Scan
pnp transistor 800v

lm2642

Abstract: either the Vds of the top FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is independently adjustable for each channel. The LM2642 features , either channel generate unwanted Ldi/dt noise spikes at the source node of the FET (SWx node) and also , FET as apply to the bottom FET. Loop Compensation where Tj_max is the maximum allowed junction , also be paralleled to operate as a dual-phase single output regulator. The output of each channel can
National Semiconductor
Original
SNVS203H

LM5642

Abstract: BAS40-06 allowed junction temperature in the FET, Ta_max is the maximum ambient temperature, Rja is the , operating 180° out of phase with each other at a normal switching frequency of 200kHz. n Two synchronous buck regulators n 180° out of phase operation n Synchronizable switching frequency from 150kHz to 250kHz n 4.5V to 36V input range n 50µA Shutdown current n Adjustable output from 1.3V to 90% of Vin n 0.04% (typical) line and load regulation error n Current mode control with or without a sense
National Semiconductor
Original
BAS40-06 RLF12545T-100M5R1 RLF12560T-4R2N100 Si4840DY Si4850EY TSSOP-28

LM2642

Abstract: LM2642MTC frequency of 300kHz. n n n n n n n n The two switching regulator controllers operate 180° out , dual-phase single output regulator. The output of each channel can be independently adjusted from 1.3 to , top FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is independently adjustable for each channel. The LM2642 features analog soft-start , monitor the dc output of channel 1. Over-voltage protection is available for both outputs. A UV-Delay pin
National Semiconductor
Original
LM2642MTC

pHfet

Abstract: Channel 1 or 2 ROSC Oscillator Resistor GATE(H)1, GATE(H)2 High-Side FET Driver for Channel 1 or 2 GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 PGnd1 Power Ground for Channel 1 PGnd2 Power Ground for Channel 2 SGnd Ground for Internal Reference LGnd Logic Ground Operating Junction , GATE(H)1 GATE(L)1 PGnd1 LGnd SGnd VFFB1 VFB1 COMP1 High Side Switch FET driver pin for the channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. High Current ground for the GATE(H)1
Cherry Semiconductor
Original
pHfet CS5421 MS-012 CS5421GD16 CS5421GDR16

SI4470DY

Abstract: LM5642MTC . (25) where Tj_max is the maximum allowed junction temperature in the FET, Ta_max is the maximum , operating 180° out of phase with each other at a normal switching frequency of 200kHz. n Two synchronous buck regulators n 180° out of phase operation n Synchronizable switching frequency from 150kHz to 250kHz n 4.5V to 36V input range n 50µA Shutdown current n Adjustable output from 1.3V to 90% of Vin n 0.04% (typical) line and load regulation error n Current mode control with or without a sense
National Semiconductor
Original
SI4470DY

LM5642MTC

Abstract: BAS40-06 . (25) where Tj_max is the maximum allowed junction temperature in the FET, Ta_max is the maximum , operating 180° out of phase with each other at a normal switching frequency of 200kHz. n Two synchronous buck regulators n 180° out of phase operation n Synchronizable switching frequency from 150kHz to 250kHz n 4.5V to 36V input range n 50µA Shutdown current n Adjustable output from 1.3V to 90% of Vin n 0.04% (typical) line and load regulation error n Current mode control with or without a sense
National Semiconductor
Original

LM2642

Abstract: LM2642MTC maximum allowed junction temperature in the FET, Ta_max is the maximum ambient temperature, Rja is the , frequency of 300kHz. n n n n n n n n n The two switching regulator controllers operate 180 , dual-phase single output regulator. The output of each channel can be independently adjusted from 1.3 to , response to fast load transients. Current is sensed across either the Vds of the top FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is
National Semiconductor
Original

LM2642

Abstract: LM2642MTC guidelines apply to the top FET as apply to the bottom FET. where Tj_max is the maximum allowed junction , frequency of 300kHz. n n n n n n n n The two switching regulator controllers operate 180° out , dual-phase single output regulator. The output of each channel can be independently adjusted from 1.3 to , top FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is independently adjustable for each channel. The LM2642 features analog soft-start
National Semiconductor
Original

LM2642

Abstract: LM2642MTC is the maximum allowed junction temperature in the FET, Ta_max is the maximum ambient temperature , frequency of 300kHz. n n n n n n n n The two switching regulator controllers operate 180° out , dual-phase single output regulator. The output of each channel can be independently adjusted from 1.3 to , top FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is independently adjustable for each channel. The LM2642 features analog soft-start
National Semiconductor
Original
Abstract: either channel Usually a 3.3 to 4.7 resistor is sufficient to suppress the noise. Top FET switching , to the bottom FET. where Tj_max is the maximum allowed junction temperature in the FET, Ta_max is the , paralleled to operate as a dual-phase single output regulator. The output of each channel can be , FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is independently adjustable for each channel. The LM2642 features analog soft-start National Semiconductor
Original

LM2645MTD

Abstract: MTD48 FET. Current limit is independently adjustable for each channel. The analog soft-start for the , Two channels operating 180° out of phase n Separate on/off for each channel n Separate Power Good , n Skip-mode operation available n Negative current limit n Separate soft start for each channel n , is user selectable between 200 kHz or 300 kHz. The first switching controller (Channel 1) features a fixed 5V output, and the second switching controller controller (Channel 2) features a fixed 3.3V
National Semiconductor
Original
LM2645 LM2645MTD MTD48

LM27222

Abstract: 0828V of the bottom power FET. Pin 36, OUT2: Channel 2 pulse output to control the switching of the , 45, NC: No connect. Pin 46, SRCK1: Kelvin connect to Channel 1 bottom FET source node (ground) to , force Channel 1 to run in diode emulation mode (bottom FET is turned off when inductor current goes , driver to enable or disable the turning on of the bottom power FET. Pin 30, OUT2: Channel 2 pulse , bottom FET source node (ground) to detect negative inductor current. Pin 41, SW1: Connect to Channel 1
National Semiconductor
Original
LM27212 LM27222 0828V LM27212MTD LM27212MTDX LM27212SQ LM272

tp41c

Abstract: 1 amp FET switch 24SW 24 Channel MOSFET Driver LDX_IN LDX_OUT SS_CMD_X 1 of 24 Switches Memory , module (MCM) 24 channel MOSFET driver uses Maxwell Technologies' patented radiation-hardened RAD-PAK , current per channel No derating required to 90° C Total dose hardness: depending upon space mission in , MOSFETs, along with interface components, that can switch up to 2A per channel. The RDS-ON of the MOSFET , rights reserved. 24SW 24 Channel MOSFET Driver TABLE 1. 24SW PINOUT DESCRIPTION PIN NAME
Maxwell Technologies
Original
tp41c 1 amp FET switch TP41A tp5d TP40D TP10D

LM2645

Abstract: LM2645MTD FET. Current limit is independently adjustable for each channel. The analog soft-start for the , Two channels operating 180° out of phase n Separate on/off for each channel n Separate Power Good , n Skip-mode operation available n Negative current limit n Separate soft start for each channel n , is user selectable between 200 kHz or 300 kHz. The first switching controller (Channel 1) features a fixed 5V output, and the second switching controller controller (Channel 2) features a fixed 3.3V
National Semiconductor
Original

1000 watt buck converter scheme

Abstract: CS5421 Resistor 4.0 V -0.3 V 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High-Side FET Driver for Channel , Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC PGND1 Power Ground for Channel 1 0V 0V 1.5 A peak 200 mA DC N/A PGND2 Power Ground for Channel 2 0V 0V 1.5 A peak 200 mA DC N/A SGND Ground for Internal Reference , FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side Synchronous FET driver pin for the
ON Semiconductor
Original
1000 watt buck converter scheme SO-16 CS5421/D

TPD7000F

Abstract: SILICON MONOLITHIC BIPOLAR LINEAR INTEGRATED CIRCUIT TPD7000F 4-CHANNEL LOW-SIDE POWER MOS FET DRIVER TPD7000F is a power MOS FET driver for low-side switching. This 4-charmel driver with a built-in circuit is used to monitor the voltage between the MOS FET drain and source for each channel and to output the state of the power MOS FET. FEATURES · Low-side N-channel power MOS FET driver (input capacitance: 15nF Max). · Incorporates a power MOS FET overcurrent protection function. · Incorporates induction load
-
OCR Scan
Abstract: current reaching the summing junction of the op amp. Secondly, the rp s (O N ) of the FET begins to " , ., the drains of the FET switch are held at or near ground by oper ating into the summing junction of an , placed in the feedback path in order to compensate for the "O N " resist ance of the switch FET as shown , grounded exhibit im proved noise immunity for positive analog signals in the C O M PE N S A T IO N FET , FET switch tends to forward bias the source to gate junction and the signal shunting diode resulting -
OCR Scan
AH5009/AH5010/AH5011/AH5012 LF13331 LF13332 LF13333 AH5010C TL/H/5659-7

TP41C

Abstract: TP40D 24SW 24 Channel MOSFET Driver LDX_IN LDX_OUT SS_CMD_X 1 of 24 Switches Memory , module (MCM) 24 channel MOSFET driver uses Maxwell Technologies' patented radiation-hardened RAD-PAK , current per channel No derating required to 90° C Total dose hardness: depending upon space mission in , MOSFETs, along with interface components, that can switch up to 2A per channel. The RDS-ON of the MOSFET , . 24SW 24 Channel MOSFET Driver TABLE 1. 24SW PINOUT DESCRIPTION PIN NAME 1 Pkg-Gnd 2
Maxwell Technologies
Original
tp41c transistor low voltage mosfet switch 3 amp 200 Amp mosfet TP10A Analog FET Switch fet data book free download

transistor 2Fn

Abstract: motorola transistor cross reference Low-Side FET OnResistance Gate Drive (for Channel 2 Switching Regulator Controller) Iboot2 CBOOT Leakage , N LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs General , smaller input filter. The first switching controller (Channel 1) features an Intel mobile CPU compatible , also compatible with the dynamic VID requirements. The second switching controller (Channel 2) is , through sensing the Vds of the top FET and thus an external sense resistor is not necessary. A power
National Semiconductor
Original
transistor 2Fn motorola transistor cross reference 16uH Thermal Shut Down Functioned MOSFET

CS5421

Abstract: CS5421GD16 Resistor 4.0 V ­0.3 V 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High­Side FET Driver for Channel , Low­Side FET Driver for Channel 1 or 2 16 V ­0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC PGND1 Power Ground for Channel 1 0V 0V 1.5 A peak 200 mA DC N/A PGND2 Power Ground for Channel 2 0V 0V 1.5 A peak 200 mA DC N/A SGND Ground for Internal Reference , GATE(H)1 High Side Switch FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side
ON Semiconductor
Original
Abstract: FET Driver for Channel 1 or 2 Low­Side FET Driver for Channel 1 or 2 Power Ground for Channel 1 Power , GATE(L)1 PGND1 LGND SGND VFFB1 VFB1 COMP1 FUNCTION High Side Switch FET driver pin for the channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. High Current ground for the GATE(H)1 , pins. Low Side Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin for the channel 2 FET. BIAS CURRENT SOURCE GEN RAMP1 RAMP2 CLK1 VFFB1 VFFB2 OSC CLK2 PWM ON Semiconductor
Original
Abstract: GATE(L)1, GATE(L)2 PGND1 PGND2 SGND LGND Pin Name High­Side FET Driver for Channel 1 or 2 Low­Side FET , Switch FET driver pin for the channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET , GATE(H)2 and GATE(L)2 pins. Low Side Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin for the channel 2 FET. BLOCK DIAGRAM VCC ROSC BIAS CURRENT SOURCE GEN , dissipation in the FET switch does not cause the power component's junction temperature to exceed 150°C. The ON Semiconductor
Original

S11V

Abstract: AH5009 AH5012C AH5011C i j -k t J S t Ï / Ï n_ 1 0 !. J AH5009C and AH5010C MUX Switches (4-Channel , . However, current through the FET switch tends to forward bias the source to gate junction and the signal , finite error in the current reaching the summing junction of the op amp. Secondly, the ros(ON) of the FET , /demultiplexers Multiple channel AGO Quad compressors/expanders Choppers/demodulators Programmable gain amplifiers , ) Dual-ln-Line Package DuaMn-Line Package J T~ 14 13 T 7 4 CHANNEL MUX 4 SPST SWITCHES ^j ÏZ II
-
OCR Scan
S11V AH5009 AH5011CN AH5009/AH5010/AH5011 AH5012 TL/H/5669-7 AH5009/AH5010/AH501 AHH11 AH5011

high power FET transistor s-parameters

Abstract: ATP-1054 diode junction. III. How Does the FET Work? Gain in an FET is proportional to the channel conductivity (the "channel" being that area within the epi material under the gate). In a depletion mode FET , with a diode gate structure (similar to a junction FET, but a surface device) made from gallium , inversely proportional to its gate length. Gate width The size of the GaAs FET channel that carries , ­ The measured or estimated temperature of the GaAs FET channel under operating conditions. Tstg
Agilent Technologies
Original
ATP-1054 high power FET transistor s-parameters bipolar transistor ghz s-parameter high frequency transistor ga as fet RF Transistor s-parameter NF50 5963-2025E 5966-0779E

Diode DII

Abstract: 2SK299 FET channel current overrides the PN junction leakage current. Junction Temperature Tj (°C , transistor's Tj, the allowable channel temperature is the upper limit junction temperature value, which , I in relation to ID. P channel MOS FETs also have similar characteristics. P channel and N channel , . 116 Figure 5-36 Structure of D Series) (Vertical type) (N channel Figure 5-37 Structure o f S Series (Lateral type) (N channel) Reverse Drain Current vs. Reverse Drain Current vs. 3 C £ Q oe
-
OCR Scan
Diode DII 2SK299 2SK2265 2SJ68 2sk135 application note 2SK1058

high frequency transistor ga as fet

Abstract: ATP-1054 MESFET for Metal Semiconductor) is simply an FET with a diode gate structure (similar to a junction FET , looks like a forward-biased diode junction. III. How Does the FET Work? Gain in an FET is , capacitor or reversebiased diode junction) of the semiconductor. As a unipolar device, the current in an FET , channel and there is little or no current carried by the minority carriers (in an N-channel FET, holes). , width The size of the GaAs FET channel that carries current. That is, width is the longer of the two
Hewlett-Packard
Original
bipolar transistor s-parameter Transistor s-parameter

mosfet 2sk

Abstract: FB3x temperature for a given FET package, is: where Tj_max is the maximum allowed junction temperature in the , LM2648 Two-Phase, Synchronous Step-Down 3-Channel Switching Regulator Controller General , regulator controllers providing 3 outputs at a switching frequency of 300kHz. n n n n n Each pair , . Current-mode feedback control on Channel 3 assures superior line and load regulation and wide loop bandwidth , LM2648 also features an adjustable UVLO feature. n n n n n n n n n n Four synchronous
National Semiconductor
Original
mosfet 2sk FB3x LM2648MTD MTD56

683j CAPACITOR

Abstract: 16v .047 uf ° out of phase n Separate on/off control for each channel n Current mode control without sense , Channel 1 output from 0.925V to 2.00V n ± 1.5% DAC accuracy from 0°C to 125°C n ± 1.7% initial tolerance for Channel 2 n Dynamic VID change ready n Power good flags VID changes n Channel 2 output from , , resulting in a smaller input filter. The first switching controller (Channel 1) features an Intel mobile , controller (Channel 2) is adjustable between 1.25V to 6.0V. Use of synchronous rectification and pulse-skip
National Semiconductor
Original
683j CAPACITOR 16v .047 uf 4752F CEPH149 CRCW0805 MOTOROLA small signal transistor

683j CAPACITOR

Abstract: VJ1206S105MXJAC ° out of phase n Separate on/off control for each channel n Current mode control without sense , Channel 1 output from 0.925V to 2.00V n ± 1.5% DAC accuracy from 0°C to 125°C n ± 1.7% initial tolerance for Channel 2 n Dynamic VID change ready n Power good flags VID changes n Channel 2 output from , current mode synchronous buck regulator controllers and a linear regulator controller. GENERAL n Three regulated output voltages n 4.5V to 30V input range n Power good function n Input under-voltage lockout
National Semiconductor
Original
VJ1206S105MXJAC vishay transistor databook 104j 2A IRF7805 IRF7807 LM2633MTD

2n4391, Voltage controlled

Abstract: sw 2n4093 voltage is applied at the Drain of the FET. (Vos = O junction FET) (V «(TH ) M OS FET). This param eter is , the G ate in relation to the Source to turn the FET off. (junction FET). This is similar to the Pull , " O n " resistance (Ros) the H igher the junction cap acitan ce. (Slow er switching speed) The Lower , 4416 RECOMMENDED SWITCHING DEVICE TYPES " N" CHANNEL TYPICAL APPPLICATIONS 2NS432 2N5433 Low "R " , -Ælitran Devices. Inc. knot? ¥© ^©[D)(yj(gir ©attæmkqx IN TRO D U CTIO N TO TH E F E T S
-
OCR Scan
2N5906 2n4391, Voltage controlled sw 2n4093 SDF1001 2N4391 2N4393 2N4861 2N3824 4417-2N4416

NCP5425DBR2G

Abstract: NCP5425DB , GATE(H)2 High-Side FET Driver for Channel 1 or 2 20 V -0.3 V 2.0 A Peak 200 mA DC 2.0 A Peak 200 mA DC GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V , High Side Switch FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side Synchronous FET driver pin for the channel 1 FET. 3 GND Ground. All circuits are referenced to this pin. IC , for the channel 2 FET. 20 GATE(H)2 High Side Switch FET driver pin for the channel 2 FET
ON Semiconductor
Original
NCP5425 NCP5425DBR2G NCP5425DB NCP5425DBG NCP5425DBR2 NTD110N02RT4 NTD60N02R TSSOP-20 NCP5425/D
Abstract: High-Side FET Driver for Channel 1 or 2 20 V -0.3 V 2.0 A Peak 200 mA DC 2.0 A Peak 200 mA DC GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 2.0 A Peak 200 mA , . Symbol Description 1 GATE(H)1 High Side Switch FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side Synchronous FET driver pin for the channel 1 FET. 3 GND Ground. All , (L)2 Low Side Synchronous FET driver pin for the channel 2 FET. 20 GATE(H)2 High Side ON Semiconductor
Original

9v voltage regulator code 9y

Abstract: pj 019 SMD diode Application Information continued n cà Adaptive FET Non-Overlap The CS51312 includes circuitry to prevent , Figure 11: Adaptive FET Non-Overlap (lOOns/div). Channel 1 - GATE(H) (5V/div) Channel 2 - GATE(L) (5V/div , total power dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: Tj = Ta + [Phfet(total) x RbjaL where Tj = FET junction temperature; Ta = ambient , the maximum FET switch junction temperature can be calculated: Tj = TA + [Plfet(total) x RbjaL where
-
OCR Scan
9v voltage regulator code 9y pj 019 SMD diode CS51312-D ca 3161 e IC pj SMD diode 2099 SS16GICT SS16GICT-ND1 ZM4746ACT-ND C10-1HF T510X477K006AS4394 CS51312D16 CS51312DR16

N CHANNEL jfet Low Noise Audio Amplifier

Abstract: transistor fn 1016 devices. Figure 2. Characteristics of Junction FET Noise Describing Junction FET Noise Characteristic Junction FET en and in characteristics are frequency- dependent within the audio noise spectrum , thermal noise voltage of the channel resistance. In the so-called 1/fn region, en is expressed as e n + , current in the gate channel junction. It is defined as where Rp is the real part of the gate-to-source , AN106 Low-Noise JFETs - Superior Performance to Bipolars D Introduction Junction field
Temic Semiconductors
Original
SST4393 N CHANNEL jfet Low Noise Audio Amplifier transistor fn 1016 siliconix fet JFET APPLICATIONS Siliconix AN106 jfets U401/U404/ SST404/ SST406
Abstract: High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Positive Current Sense for , COMP1 Description High Side Switch FET driver pin for the channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. Ground. All circuits are referenced to this pin. IC substrate connection , . Power input for GATE(L)1 and GATE(L)2 pins. Low Side Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin for the channel 2 FET. 11 COMP2 12 13 14 15 16 17 18 19 20 ON Semiconductor
Original

NCP5425 D

Abstract: pHfet Resistor 5.0 V -0.3 V 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High-Side FET Driver for Channel , Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 2.0 A Peak 200 mA DC 2.0 A Peak 200 mA DC , FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side Synchronous FET driver pin for the channel 1 FET. 3 GND Ground. All circuits are referenced to this pin. IC substrate connection , frequency. 18 VCC 19 GATE(L)2 Low Side Synchronous FET driver pin for the channel 2 FET
ON Semiconductor
Original
NCP5425 D
Abstract: Channel 1 or 2 Voltage Feedback Input for Channel 1 or 2 Oscillator Resistor High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Positive Current Sense for Channel 1 or 2 Negative , channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. Ground. All circuits are , Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin for the channel 2 FET. 11 , that the total power dissipation in the FET switch does not cause the power component's junction ON Semiconductor
Original

NCP5425

Abstract: NCP5425DB Resistor 5.0 V -0.3 V 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High-Side FET Driver for Channel , Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 2.0 A Peak 200 mA DC 2.0 A Peak 200 mA DC , . Symbol Description 1 GATE(H)1 High Side Switch FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side Synchronous FET driver pin for the channel 1 FET. 3 GND Ground. All , (L)2 Low Side Synchronous FET driver pin for the channel 2 FET. 20 GATE(H)2 High Side
ON Semiconductor
Original

NCP5425

Abstract: NCP5425DB 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High-Side FET Driver for Channel 1 or 2 20 V -0.3 V , . Symbol Description 1 GATE(H)1 High Side Switch FET driver pin for the channel 1 FET. 2 GATE(L)1 Low Side Synchronous FET driver pin for the channel 1 FET. 3 GND Ground. All , (L)2 Low Side Synchronous FET driver pin for the channel 2 FET. 20 GATE(H)2 High Side Switch FET driver pin for the channel 2 FET. Input Power supply pin. Power input for GATE(L)1 and GATE
ON Semiconductor
Original

25SP33M

Abstract: LM2633 channels operating 180° out of phase n Separate on/off control for each channel n Current mode control , < 17V) n Channel 1 output from 0.925V to 2.00V n ± 1.5% DAC accuracy from 0°C to 125°C n ± 1.5% initial tolerance for Channel 2 n Dynamic VID change ready n Power good flags VID changes n Channel 2 , Low-Side FET On-Resistance 0.5 100 nA A Gate Drive (For Channel 2 Switching Regulator , Low-Side FET On-Resistance 0.5 Gate Drive (For Channel 2 Switching Regulator Controller) 11
National Semiconductor
Original
25SP33M

PH7030L

Abstract: PH7030L Philips Semiconductors N- channel TrenchMOSTM logic level FET 3. Ordering information , PH7030L Philips Semiconductors N- channel TrenchMOSTM logic level FET 6. Characteristics Table 5 , March 2004 5 of 12 PH7030L Philips Semiconductors N- channel TrenchMOSTM logic level FET , 6 of 12 PH7030L Philips Semiconductors N- channel TrenchMOSTM logic level FET 03aa33 , PH7030L Philips Semiconductors N- channel TrenchMOSTM logic level FET 003aaa391 20 IS (A
Philips Semiconductors
Original
M3D748 MBB076 MBL286

transistor 2n5088 equivalent

Abstract: transistor fn 1016 corner frequency is normally above 10 kHz in JFET devices. Figure 2. Characteristics of Junction FET Noise Describing Junction FET Noise Characteristic Junction FET en and in characteristics are , , except in the 1/f n region, closely approximates the equivalent thermal noise voltage of the channel , region shown in Figure 2, due 2 to thermallygenerated reverse current in the gate channel junction , (7) The noise power of the FET referred to the input is en2 + ) i n 2 @ R G RG (8) When
Temic Semiconductors
Original
transistor 2n5088 equivalent 2N5088 equivalent 2N5088 SIMILAR 2n930 equivalent transistor j201 Siliconix "low noise jfet"

sd2t

Abstract: THERMAL FET HAF2002 Silicon N Channel MOS FET Series Power Switching / Over Temperature Shut-down Capability HITACHI Features ADE-208-503 1st. Edition This FET has the over temperature shut-dow n capability sensing to the junction temperature. This FET has the built-in over temperature shut-dow n circuit in the gate area. And this circuit operation to shut-dow n the gate voltage in case o f high junction , shut-down circuit · Latch type shut-dow n operation (Need 0 voltage recovery) Outline TO -220FM 1
-
OCR Scan
sd2t F2002 HAF2001

2N5088 equivalent

Abstract: siliconix FET AUDIO AMPLIFIER 2. Characteristics of Junction FET Noise Describing Junction FET Noise Characteristic Junction , voltage of the channel resistance. (2) where n varies from 1 to 2 depending upon the device in , channel junction. It is defined as 4kTB Rp (4) where Rp is the real part of the , en 2 ) i n 2 R G 2 4kTR GB (10) NF + 10 log 10 [F] The noise figure of the FET is 1 ) e , AN106 Low-Noise JFETs - Superior Performance to Bipolars D Introduction Junction field
Temic Semiconductors
Original
siliconix FET AUDIO AMPLIFIER siliconix FET DESIGN monolithic amplifier MAR 3 app note Siliconix JFETs Dual transistor pn4393 transistor equivalent table chart ST201/ SST204 PN4393

N CHANNEL jfet Low Noise Audio Amplifier

Abstract: jfet n channel ultra low noise 2. Characteristics of Junction FET Noise Describing Junction FET Noise Characteristic Junction , voltage of the channel resistance. (2) where n varies from 1 to 2 depending upon the device in , channel junction. It is defined as 4kTB Rp (4) where Rp is the real part of the , expressions for the noise power of both the FET and RG are substituted, the noise factor becomes en 2 ) i n 2 R G 2 4kTR GB (10) The noise figure of the FET is n 2 The curves shown in Figure 3
Siliconix
Original
jfet n channel ultra low noise Siliconix JFET Dual 2N4338 ic for hearing aid SST404 2n5088 transistor

beckman resistor

Abstract: 698-1-R given FET switch As an example if N e 10 AD e 0 1% and ID(OFF) s10 nA at 85 C for the AH5010 R1(MAX , demultiplexers Multiple channel AGC Quad compressors expanders Choppers demodulators Programmable gain , ) Dual-In-Line Package Dual-In-Line Package LOGIC DRIVE 5V LOGIC 15V LOGIC AH5010C MUX Switches (4-Channel , internally connected to the substrate C1995 National Semiconductor Corporation TL H 5659 4 CHANNEL , Analog Signal Voltage b 15V Diode Current 30 mA Soldering Information N Package 10 sec SO
National Semiconductor
Original
beckman resistor 698-1-R AH5012CN DIODE 10B3 cmos open collector AH5012CM AH5010CN

AH5012CN

Abstract: ah5011cn junction of the op amp Secondly the rDS(ON) of the FET begins to ``round'' as IS approaches IDSS A , Number of channels e ``OFF'' leakage of a given FET switch As an example if N e 10 AD e 0 1% and ID , kHz ol et e Y Active filters Signal multiplexers demultiplexers Multiple channel AGC , AH5010C AH5012C AH5011C O bs 5V LOGIC 15V LOGIC 4 CHANNEL MUX AH5010C MUX Switches (4-Channel , Voltage Negative Analog Signal Voltage b 15V Diode Current 30 mA Soldering Information N
National Semiconductor
Original
Beckman 698-1 n channel fet array M14A N14A BECKMAN 698 beckman 100k

2sk135 application note

Abstract: 2sk1058 equivalent FET channel current overrides the PN junction leakage current. 100 50 Drain Current IDSS (µA , transistor's Tj, the allowable channel temperature is the upper limit junction temperature value, which , characteristics. P channel and N channel types have complementary characteristics. 10 15 10 8 9 T c , . Power MOS FET Absolute Maximum Ratings and Electrical Characteristics 1. Absolute Maximum Ratings , current ID Channel dissipation Pch Also, these items express rating values which cannot be exceeded no
Renesas Technology
Original
2sk1058 equivalent k176 2sk135 audio application 2sk135 application 2SC1343 2SK186 REJ27G0017-0200/R

fet third quadrant operation

Abstract: fet vcr compatible voltage divider attenuator.*^) (al N-channel FET Circuit Arrangement for Both an N and P Channel FET , across the junction (VGg, VGp) controls the channel conductance. Under the condition that the FET is , (on)> occurs at VGS = 0 and is dictated by the geometry of the FET. A device with a channel of small , between two of the terminals is controlled by a voltage potential applied to the third. A junction , conductance in the channel between the source and the drain is modulated by a transverse electric field. The
-
OCR Scan
fet third quadrant operation fet vcr compatible jfet transistor for VCR 647 "photomultiplier" n-channel jfet amplitude control sherwin AU-13

tp41c

Abstract: TP41A PRELIMINARY SPACE ELECTRONICS INC. 24 CHANNEL MOSFET DRIVER SPACE PRODUCTS 24SWRE PWR VOUT 24 Sets 2.5" Sq. SIG PWR 24 Channel MOSFETT Driver Memory OPERATING , to 90 oC Maximum junction temperature:125 oC 0228.00Rev0 (858) 452-4167 - Fax: (858) 452-5499 , (200 m typ) 2A switching current per channel No derating required to 90 oC Meets total ionization , Space Electronics Inc. All rights reserved. PRELIMINARY 24SWRE 24 CHANNEL MOSFET DRIVER
Space Electronics
Original
TP11A TP10B tp5c TP10C electroplating power switch 24SWRP I-15V 050BSC Q176-01
Abstract: 2 Voltage Feedback Input for Channel 1 or 2 Oscillator Resistor High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Positive Current Sense for Channel 1 or 2 Negative , channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. Ground. All circuits are , Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin for the channel 2 FET. 11 , that the total power dissipation in the FET switch does not cause the power component's junction ON Semiconductor
Original

beckman resistor

Abstract: Beckman Industrial current reaching the summing junction of the op amp. Secondly, the rQS(ON) of the FET begins to "round" , arriving at the summing junction of the op amp. As an example, if N = 10, Ad = 0.1%, and Id(OFF) S10 nA , channel AGC â  Quad compressors/expanders â  Choppers/demodulators â  Programmable gain amplifiers , ) Dual-ln-Line Package 14 x; 13 rr H s u 10 L â  -Iâ'"J L_ AH5010C MUX Switches (4-Channel Version Shown) Order Number AH5010CN See NS Package Number M14A or N14A COMPENSATING FET TYn^r Tir- FT TT
-
OCR Scan
Beckman Industrial audio compressor expander IC si6976 AH5010/AH5011/AH5012 TL/H/5659-8 TL/H/5659-12 698-1-H TL/H/5659 L5011H4

mb39c313

Abstract: lcd t-con circuit N ew Products MB39C313 for Large LCD Panels MB39C313 4-Channel DC/DC Converter IC A , in a single chip. With built-in switching FET for large current operation, this product is optimal , management IC with a builtin 4-channel power management control block. It consists of a 2-channel DC/DC converter with switching FET and a 2channel charge pump type DC/DC converter. The DC/DC converter block , the built-in switching FET and phase compensator. protection, undervoltage lockout, over
Fujitsu
Original
lcd t-con circuit

FET U310

Abstract: FET 2N4416 when a specified voltage is applied at the Drain of the FET. (V g s= O junction FET) (Vss(TH) MOS FET). , must be applied to the G ate in relation to the Source to turn the FET off. (junction FET). This is , : The Lower the "O n " resistance ( R es) the Higher the junction capacitance. (Slower switching speed , 2N5594 2N4117 thru 2N4119 2N5903 thru 2N5906 2N4416 RECOMMENDED SWITCHING DEVICE TYPES " N" CHANNEL , -Jbtttron Devices. Inc mw TO FOR SWITCHING §MUË
-
OCR Scan
2N5396-2N5397 2N5397-2N5396 FET U310 FET 2N4416 2n4117 jan 2N3687A 2N4856 2N4417-2N4416 2N2609 2N5114 2N5116

BD9240

Abstract: bd9240f 12 13 14 VREF DUTY1 DUTY2 STB FUNCTION PIN No. Power Ground for FET drivers NMOS FET driver (Channel 2 side) NMOS FET driver (Channel 2 side) Input of Under Voltage Lock Out CT , Protection NMOS FET driver (Channel 1 side) NMOS FET driver (Channel 1 side) 4/4 NOTE FOR USE This , Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation *1 , Burst-dimming by PWM signal or DC (Channel 1) Control Burst-dimming by PWM signal or DC (Channel 2) Stand-by
ROHM
Original
BD9240 bd9240f dc-ac inverter Controller PWM SSOP-B28 BD9240FV BD9240F 25VCC R0039A

AN73-1 fet

Abstract: 9L05 (Volts, Max.1 50 5.0 60 Resistance Channel , (TO· I Operating Mode Threshold Voltage (Volts, Max,) 50 Resistance Channel , . f = 1 kHz f = 1 MHz 4 5 200 600 4,000 8,000 3 3 NT 1.5 1.5 .n pF -0 y. 6 , - 3 4 5 6 7 200 25 15 10 = -1 J.l.A, VOS = -'10 V VGS=O,IO=O VGO = 10 V, IS = 0 .n pF 0 y VGS=10V,10=0 Silicanix 2-99 ~ U ~ APPLICATIONS > ~ ~ A. N-CHANNEL FET
Vishay Siliconix
Original
AN73-1 fet 9L05 siliconix AN73-7 AN73-1 J174-7 2n Siliconix FET

E1351-66201

Abstract: list of n channel fet PDFINFO H5 5 8 6 - 0 1 16-Channel FET Multiplexer HP E1351A Technical Specifications q , Information Description 16-Channel FET Multiplexer Service Manual 3 Yr. Retn. to HP to 1 Yr. OnSite Warr , Description The HP E1351A FET multiplexer is a B-size, 1-slot, register-based VXI module that switches 16 channels each of high, low, and guard. The FET multiplexer module consists of a B-size component card , TRIGger:SOURce DBUS. To connect an external DMM to the FET multiplexer for high-speed scanning
Hewlett-Packard
Original
E1351-66201 E1411-80001 W01 fet P channel Junction FET E1326A 16 DIGITAL MULTIPLEXER E1352A E1353A E1357A E1358A E1326B
Abstract: -0.3 V ISOURCE N/A ISINK 1.5 A peak 200 mA DC 1.0 mA Compensation Capacitor for Channel 1 or 2 , Oscillator Resistor High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Ground , Side Switch FET driver pin for channel 1. Low Side Synchronous FET driver pin for channel 1. Ground pin , Side Synchronous FET driver pin for channel 2. High Side Switch FET driver pin for channel 2. 9 , that the total power dissipation in the FET switch does not cause the power component's junction ON Semiconductor
Original
NCP5422A NCP5422ADR2 NCP5422A/D

AH5010CN

Abstract: 1 amp FET switch . However, current through the FET switch tends to forward bias the source to gate junction and the signal , compensation fet analog output - o _n_ FIGURE 1. Use of Compensation FET r1 Va*+iovo-^AAt-0 Tl/H/5659-4 , analog input signal Ap = Desired accuracy N = Number of channels 'd(OFF) = "OFF" leakage of a given FET , channel AGO â  Quad compressors/expanders â  Choppers/demodulators â  Programmable gain amplifiers , 1 i s I LOGIC DRIVE 4 CHANNEL MUX 4 SPST SWITCHES 5V LOGIC 15V LOGIC AH5010C AH5009C AH5012C
-
OCR Scan
LS TTL family characteristics MS10 PACKAGE 9B Ro-2A Diode 56597 AH5009CM AH5010CM TL/H/5659-6 TL/H/5659-10

CXO 043

Abstract: BA9739KV short-circuit protection. Channel 1: N channel Power MOS FET Driver with Push-Pull. Channel 2: P channel Power MOS FET Driver with Push-Pull. Channel 3 and 4: PNP Power Transistor Driver with totem-pole , Hysteresis Width Hyst â'" 0.1 â'" V 4 [N channel MOS FET Driver (CH1 )] Output Voltage H VOH - â'" 5.8 V FB=2.0V 3 Output Voltage L VOL 0.2 â'" â'" V FB=0V 3 [P channel MOS FET Driver (CH2 , same voltage. Keep Vcc-2(38PIN) and source of external MOS FET (ch3) to the same voltage. 8 . Channel 1
-
OCR Scan
BA9739KV TSZ22111-04 TSZ22111-03 CXO 043 47KQ BA9739KV-1-2 VQFP-48 JSZ02201-BA9739KV-1 TSZ02201 BA9739KV-1

E1351-66201

Abstract: HP DC POWER CONNECTOR PDFINFO H5 5 2 0 - 0 1 32-Channel Single-Ended FET Multiplexer HP E1352A Technical , components Description The HP E1352A FET multiplexer is a B-size, 1-slot, register-based VXI module that switches 32 channels of high only and one low common input. The FET multiplexer module consists of a , to the FET multiplexer for high-speed scanning synchronization up to 100,000 switches/second, order the digital FET MUX-to-DMM cable below. One analog bus cable is shipped with each module, making it
Hewlett-Packard
Original
E1411B E1352-80001 HP DC POWER CONNECTOR E1301A hp circuit diagram E1411 E1403C 95/NT E1351A/52A 5965-5520E

Microwave Switch Technology: Part 2

Abstract: transistor (FET) or switching FET functions as a three port device, where the channel between source and , well as FET physical size (periphery). Hence a balance of channel resistance (RS) and off capacitance , significantly by making the channel wider. This can be done by adding periphery to the FET, however if the , Technology: Part 2 by Rick Cory and Dave Fryklund, Skyworks Solutions, Inc. Introduction n part 1 we , is blocked or may pass. A DC control voltage applied between the gate and channel is required to
Skyworks Solutions
Original
Microwave Switch Technology: Part 2 APN1002

2n3904 smd pdf data application note

Abstract: 751E Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC , channel 1. 2 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 - GND , VCC 15 23 GATE(L)2 Low Side Synchronous FET driver pin for channel 2. 16 24 GATE(H)2 High Side Switch FET driver pin for channel 2. FUNCTION Ground pin for all circuitry , FET is known, the maximum FET switch junction temperature can be calculated: Both logic level and
ON Semiconductor
Original
CS5422 2n3904 smd pdf data application note 751E CS5422GD16 CS5422GDR16 CS5422GDWF24 SO-24L CS5422/D
Abstract: INTEGRATED CIRCUIT TPD7000F 4-CHANNEL LOW-SIDE PO W ER MOS FET DRIVER TPD7000F is a power MOS FET driver for low-side switching. This 4-channel driver with a built-in circuit is used to monitor the voitage between the MOS FET drain and source for each channel and to output the state of the power MOS FET , Junction Temperature Storage Temperature DC Pulse SYM BO L Vnu m V DH (2) Vdl VOPOUT V|N IOPOUT Pd "l"opr , Tj IlH - Tj JUNCTION T EM PER A TU RE Tj (°C) JUNCTIO N T EM PER A TU RE Tj (°C -
OCR Scan

NCP5424

Abstract: NCP5424D V -0.3 V N/A 1.5 A peak 200 mA DC COMP1, COMP2 Compensation Capacitor for Channel 1 , 1.0 mA GATE(H)1, GATE(H)2 High-Side FET Driver for Channel 1 or 2 20 V -0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or , 1.5 A peak 200 mA DC N/A IS+1, IS+2 Positive Current Sense for Channel 1 or 2 6.0 V , FUNCTION 1 GATE(H)1 High Side Switch FET driver pin for channel 1. 2 GATE(L)1 Low Side
ON Semiconductor
Original
NCP5424 NCP5424D NCP5424DR2 NCP5424/D

683j CAPACITOR

Abstract: ° out of phase n Separate on/off control for each channel n Current mode control without sense resistor , OVP n Programmable output UVP delay n 250kHz switching frequency (for Vin < 17V) n Channel 1 output from 0.925V to 2.00V n ± 1.5% DAC accuracy from 0°C to 125°C n ± 1.7% initial tolerance for Channel 2 n Dynamic VID change ready n Power good flags VID changes n Channel 2 output from 1.3V to 6.0V LINEAR , RMS current, resulting in a smaller input filter. The first switching controller (Channel 1) features
National Semiconductor
Original
SNVS139C

P-Channel Depletion Mode FET

Abstract: 5155 transistor is used in a system. It is comple mentary to the HV N- channel transistor for use in push-pull , PARAMETER Breakdown Voltage SYMBOL BVds ushsiss; ushsi5 6 +25°C) CONDITIONS ID = 10uA (N Channel) Vgs , , Vds = 16V (N Channel) Vgs = OV, Vds - -16V (P Channel) - 100 nA - -100 nA Threshold Voltage Vth Vds = Vgs ID = 1uA (N Channel) Vds = Vgs, ID = - luA (P Channel) 0.5 1.5 , DMOS FET P-channel enhancement mode DMOS FET insulated gate thyristor (IGT) thyristor diode CMOS
-
OCR Scan
5155 transistor Depletion MOSFET 20V HV Diode dc voltage regulator using thyristor P-Channel mosfet 400v 0.5A breadboard 400 USH5155 USH5156

NCP5424A

Abstract: MTD60N03 High-Side FET Driver for Channel 1 or 2 20 V -0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 1.5 A peak 200 mA , GATE(H)1 High Side Switch FET driver pin for channel 1. 2 GATE(L)1 Low Side Synchronous FET , pin for channel 2. 16 GATE(H)2 High Side Switch FET driver pin for channel 2. Error , ) FET losses; RJA = lower FET junction-to-ambient thermal resistance. where: TJ = FET junction
ON Semiconductor
Original
NCP5424A MTD60N03 NCP5424A/D

3225 zener diode

Abstract: ZM4746ACT dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: TJ = TA + [PHFET(TOTAL) × RJA], where TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL , losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction , , adaptive FET non-overlap time, and remote sense. The CS51312 will operate over a 9V to 20V (VCC2) range , FET Non-overlap Time s Adaptive Voltage Positioning s Power-Good Output Monitors Regulator Output s 5V
ON Semiconductor
Original
3225 zener diode ZM4746ACT F/10V FS70VSJ-03 CS51312GD16 CS51312GDR16

IC44L01

Abstract: DIODE BAT TPIC44L01, TPIC44L02, TPIC44L03 4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER SLIS062A-NOVEM BER 1996-R E V IS E D SEPTEMBER 1997 4-Channel Serial-in Parallel-in Low-Side Pre-FET Driver , input interfaces to control four external FET power switches such as offered in the TlTM TPIC family of , applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load
-
OCR Scan
IC44L01 DIODE BAT

schematic symbol for n channel fet

Abstract: rtl logic Signals up to 16 Volts Peak-to-Peak GENERAL DESCRIPTION These switching circuits contain one channel in one package, the channel consisting of a driver circuit controlling ¡1 SPST junction FET switch. The , IH5001/IH5002 1-Channel Driver with SPST FET Switch AND Gate Available FEATURES â'¢ Gate Lead Available for Nulling Charge Injection Voltage â'¢ Channel Completeâ'"Interfaces With Most Integrated Logic , FET switch ON, and logic "0" turns it OFF. The gate lead of the FET has been brought out to enable the
-
OCR Scan
IH5001 IH5002 schematic symbol for n channel fet rtl logic IHSO01
Abstract: floating, the SKIP mode is enabled. In FPWM mode, the lower FET of a given channel is always ON whenever , . Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows , the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top , FET. It is bootstrapped by means of a ceramic capacitor connected to the channel Switching node. This , : Power Ground pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND National Semiconductor
Original
LM2647

h500

Abstract: IH5001 channel in one package, the channel consisting of a driver circuit controlling a SPST junction FET switch , ölfflEi^DIL IH5001/IH5002 1-Channel Driver with SPST FET Switch (Gate Available) FEATURES â'¢ Gate Lead Available for Nulling Charge Injection Voltage â'¢ Channel Completeâ'"Interfaces With Most , FET switch ON, and logic "0" turns it OFF. The gate lead of the FET has been brought out to enable the , 12V, V- : -18V. Input test condition which guarantees FET switch ON or OFF as SYMBOL CHARACTERISTIC
-
OCR Scan
h500

LM2647

Abstract: LM2647LQ channel is always ON whenever the upper FET is OFF (except for a narrow shoot-through protection deadband , Channel 2. Also serves as the lower rail of the floating driver of the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top gate driver is interlocked with the , drive pin for the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with , through inductor, passing from Drain to Source of lower FET, see Channel 4 in Figure 2). Now the current
National Semiconductor
Original
LM2647LQ LM2647LQX LM2647MTC LM2647MTCX LQA28A

3 DG 1000

Abstract: D0126 DMEÃ^DIL DG 126, DG129, DG 133, DG 134, DG 140, DG141, DG 151, DG 152, DG 153, DG154 2-Channel Drivers with SPST and DPST FET Switches FEATURES â'¢ Each channel completeâ'"interfaces with most , Versions. GENERAL DESCRIPTION These switching circuits contain two channels in one package, each channel consisting of a driver circuit controlling a SPST or DPST junction FET switch. The driver interfaces DTL, TTL , /154 TYPICAL CHARACTERISTICS (per channel) DG126, 129, 133, 134, 140, 141 V|N THRESHOLD vi
-
OCR Scan
DG161 DG152 0G141 IDG140 3 DG 1000 D0126 DG140/A DG141/A DQ133 OG134

OG426

Abstract: ADG433A DG426/A, DG429/A, DG433/A, DG434/A, DG440/A, DG441/A, DG451/A, DG452/A, DG453/A, DG454/A 2-Channel Drivers with SPST and DPST FET Switches FEATURES â'¢ Each channel completeâ'"interfaces with most , %â'""A" versions GENERAL DESCRIPTION These switching circuits contain two channels in one package, each channel consisting of a driver circuit controlling a SPST or DPST junction FET switch. The driver interfaces DTL, TTL , logic design directly with the switch function. Logic "1" at the input turns the FET switch ON, and
-
OCR Scan
DG451A OG426 ADG433A ADG429 n channel j fet OG434/A DG451/AI OG426/A OG429/A DG426 DQ426/A

DG441

Abstract: DG43 , each channel consisting of a driver circuit controlling a SPST or DPST junction FET switch. The driver , 2-Channel Drivers with SPST and DPST FET Switches FEATURES â'¢ Each channel completeâ'"interfaces , , which permits logic design directly with the switch function. Logic "1" at the input turns the FET , conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS PER CHANNEL , ) and DG4 DG452, DG453, DG454 (V+ = +15V, V" = -15V, VR = 0). Input test condition which guarantees FET
-
OCR Scan
DG441 DG43 DG451 OG453/A DG426A DG429A DG433A DG434A

LM2647

Abstract: LM2647LQ FPWM mode, the lower FET of a given channel is always ON whenever the upper FET is OFF (except for a , floating driver of the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 , Channel 2. This is the upper supply rail for the floating driver of the upper FET. It is bootstrapped by , pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND's are to be , recommended Layout Guidelines . Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET (Low-side drive).
National Semiconductor
Original

shockley diode

Abstract: shockley diode application different types of applications: the JFET (junction FET) used in small-signal processing and the MOSFET , and Symbol Series 901 (continued from Page 13) bulk portion of the channel resistance. An n , will generate the channel and an n+ into it defining the source. Next the thin, high quality gate , that the material immediately under the gate turns from p- to n-type). Now an n "channel" is formed , currentcontrolled device. The Field Effect Transistor (FET), although structurally different, provides the same
Microsemi
Original
n-channel enhancement mode vmos power fet shockley diode applications advantage and disadvantage of mosfet shockley diode high voltage and high current jfet p channel switch megamos

ADG453

Abstract: D0440 package, each channel consisting of a driver circuit controlling a SPST or DPST junction FET switch. The , /A 2-Channel Drivers with SPST and DPST FET Switches FEATURES â'¢ Each channel , FET switch ON, and logic "0" turns it SCHEMATIC & LOGIC DIAGRAMS (Outline Dwgs JD, FD-2) DUAL SPST , ) DG452/A[rDS(ON) = 100ÃÃ) M ^S, v DUAL DPST DG426/A(rDS(C|N) - 80ÌÌI DG429/A(rDS|ON) = 35à , device reliability. ELECTRICAL CHARACTERISTICS PER CHANNEL Applied voltages for all tests: DG426, DG429
-
OCR Scan
ADG453 D0440 Dual N FET DG426IA DG441A DG453A DG440 DG44I DG440A

LM2647MTCX

Abstract: LQA28A FPWM mode, the lower FET of a given channel is always ON whenever the upper FET is OFF (except for a , floating driver of the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 , Channel 2. This is the upper supply rail for the floating driver of the upper FET. It is bootstrapped by , pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND's are to be , recommended Layout Guidelines . Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET (Low-side drive).
National Semiconductor
Original
Abstract: floating, the SKIP mode is enabled. In FPWM mode, the lower FET of a given channel is always ON whenever , . Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows , the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top , FET. It is bootstrapped by means of a ceramic capacitor connected to the channel Switching node. This , : Power Ground pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND National Semiconductor
Original

IR5001

Abstract: IRDC5001-LS48V typical), the Vout of the IR5001 will be pulled high, turning the channel of the active ORing FET on. As , N-channel ORing FET is from source to drain, the output of the IR5001 will be pulled high to Vcc, thus turning the Active ORing FET on. If the current reverses direction and flows from drain to source (due , FET off. Typical turn-off delay for the IR5001 is only 130nS, which helps to minimize voltage sags , APPLICATION +48V input A B IR5001 Vline FET Check Pulse FET A Status Vout Vcc Gnd
International Rectifier
Original
IRDC5001-LS48V IR5001S R-THETA PD60229

ORing fet 12v 100a

Abstract: IR5001S ), the Vout of the IR5001 will be pulled high, turning the channel of the active ORing FET on. As the , N-channel ORing FET is from source to drain, the output of the IR5001 will be pulled high to Vcc, thus turning the Active ORing FET on. If the current reverses direction and flows from drain to source (due , FET off. Typical turn-off delay for the IR5001 is only 130nS, which helps to minimize voltage sags , APPLICATION +48V input A B IR5001 Vline FET Check Pulse FET A Status Vout Vcc Gnd
International Rectifier
Original
ORing fet 12v 100a FETs
Abstract: Agilent E1351A 16-Channel FET Multiplexer Data Sheet â'¢ 1-Slot, B-size, register based â , , 0.9, 0.75, 0.5 mm) 13,000 channels/s typ. 16-Channel FET Multiplexer Service Manual Terminal , terminal card and the analog bus connector. Description The Agilent E1351A FET Multiplexer is a B-size, 1-slot, register-based VXI module that switches 16 channels each of high, low, and guard. The FET , external DMM to the FET multiplexer for highspeed scanning synchronization up to 100,000 switches/ second Agilent Technologies
Original
5965-5586E

Hitachi DSA002732

Abstract: THERMAL FET HAF2002 Silicon N Channel MOS FET Series Power Switching / Over Temperature Shut­down Capability ADE-208-503 1st. Edition Features This FET has the over temperature shut­down capability sensing to the junction temperature. This FET has the built­in over temperature shut­down circuit in the gate area. And this circuit operation to shut­down the gate voltage in case of high junction , voltage Drain current Drain peak current Body to drain diode reverse drain current Channel dissipation
Hitachi Semiconductor
Original
Hitachi DSA002732
Abstract: Highâ'Side FET Driver for Channel 1 or 2 20 V â'0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC GATE(L)1, GATE(L)2 Lowâ'Side FET Driver for Channel 1 or 2 16 V â'0.3 V 1.5 A , '16 SOâ'24L PIN SYMBOL 1 1 GATE(H)1 High Side Switch FET driver pin for channel 1. 2 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 â' GND â' 3 , VCC 15 23 GATE(L)2 Low Side Synchronous FET driver pin for channel 2. 16 24 GATE ON Semiconductor
Original
Abstract: or 2 Power Input for GATE(H)1, 2 Oscillator Resistor High­Side FET Driver for Channel 1 or 2 Low­Side FET Driver for Channel 1 or 2 Ground Positive Current Sense for Channel 1 or 2 Negative Current Sense , GND PGND BST LGND IS+1 IS­1 VFB1 FUNCTION High Side Switch FET driver pin for the channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. Ground pin for all circuitry contained in the IC , supply pin. Low Side Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin ON Semiconductor
Original

C23-C25

Abstract: floating, the SKIP mode is enabled. In FPWM mode, the lower FET of a given channel is always ON whenever , . Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows , the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top , FET. It is bootstrapped by means of a ceramic capacitor connected to the channel Switching node. This , : Power Ground pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND
National Semiconductor
Original
C23-C25 SNVS210E

transistor FN 1016

Abstract: siliconix fet RG: NF = 10 logig [F] The noise figure of the FET is NF = lOlogiQ 1 + eN2 + 'N 4kTRrB dB (5) (6) When junction FET noise is expressed in terms of the noise figure (NF), an inherent disadvantage arises , itself. Describing Junction FET Noise Characteristics Junction FET e^ and ij^ characteristics are , ) Characteristics of Junction FET Noise Figure 2 ejvj, the equivalent short circuit input noise voltage (with the , root of the transconductance of the FET (ejsf
-
OCR Scan
Siliconix FET Design Catalog Siliconix JFET Siliconix "fet" siliconix catalog ag2 transistor U311
Abstract: Agilent E1352A 32-Channel Single-Ended FET Multiplexer Data Sheet â'¢ 1-Slot, B-size , Description Product No. 32-Channel Single-ended FET Multiplexer Service Manual Terminal Card,16 , guard input. The FET multiplexer module consists of a B-size component card (labeled E1351-66201 on , :SOURce DBUS. To connect an external DMM to the FET multiplexer for highspeed scanning synchronization up to 100,000 switches/ second, order the digital FET MUX-to-DMM cable below. An analog bus Agilent Technologies
Original

ANALOG SWITCH 6 CHANNEL SPST

Abstract: IH5143 Resistance 50 50 75 t5 75 100 n Is = -10 mA Vanalog = -10 V to +10 V A rDS(on) Channel to Channel rDS(on) Match 25 25 25 30 30 30 n Is (Each Channel) = -10 mA Vanaloo Min. Analog Signal Handling Capability  , DRIVERS FIGURE 13. 'BODY PULLER" FET ANALOG OUT ANALOG IN - -10V _T °1 N â E " N GND WHEN POWER , switches utilizes Intersil's latch-free junction isolated processing to build the fastest switches now , switches therefore combines the speed of the hybrid FET DG 180 Family with the reliability and low power
-
OCR Scan
IH5140 IH5040 DG180 IH5143 IH5141 IH5142 ANALOG SWITCH 6 CHANNEL SPST IH5144MTW T0100 equivalent 140-IH5145
Abstract: dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: TJ = TA + [PHFET(TOTAL) × RJA], where TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL , losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction , , adaptive FET non-overlap time, and remote sense. The CS51312 will operate over a 9V to 20V (VCC2) range , FET Non-overlap Time s Adaptive Voltage Positioning s Power-Good Output Monitors Regulator Output s 5V Cherry Semiconductor
Original
Abstract: channel GATE output to the external FET. The serial input interface is recommended when the number of , n t s POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL , TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER S LIS055A-N O VEM BER 1996 - REVISED SEPTEMBER 1997 · · · 6-Channel Serial-in/Parallel-in Low-side Pre-FET , serial input interface and parallel input interface to control six external field-effect transistor(FET -
OCR Scan

Schematic of 3phase capacitor bank

Abstract: PX3510 1.5KV Thermal Resistance JA(oC/W) JB(oC/W) JC(oC/W) N/A 3 Junction to bottom of case . . . N/A Junction to top of case . . . . . . N/A N/A 12.0 Junction to board (Note 2) . . . , . . . . . 21.2 N/A N/A Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . , Biasing gate of External, Synchronous Rectifier, N Channel MOSFETs 1.3 NGATE Pulldown Resistance Pulldown Resistance of ISL6580 for Biasing gate of External, Synchronous Rectifier, N Channel
Intersil
Original
ISL6590 ISL6580CR ISL6580CR-T Schematic of 3phase capacitor bank PX3510 ISL6580 September 2003 FN9060.2 Integrated Power Stage ic vrm MOSFET Driver coil understanding power mosfet intersil FN9060 TB389

schematic diagram ac voltage regulator

Abstract: equivalent smd mosfet Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC , channel 1. 2 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 - GND , VCC 15 23 GATE(L)2 Low Side Synchronous FET driver pin for channel 2. 16 24 GATE(H)2 High Side Switch FET driver pin for channel 2. FUNCTION Ground pin for all circuitry , the switching FET is known, the maximum FET switch junction temperature can be calculated: TJ + TA
ON Semiconductor
Original
schematic diagram ac voltage regulator equivalent smd mosfet mosfet switch circuit diagram mpp schematic Theory of Modern Electronic Semiconductor fuses 2N3904

Hitachi DSA002759

Abstract: THERMAL FET HAF2002 Silicon N Channel MOS FET Series Power Switching / Over Temperature Shut­down Capability ADE-208-503 1st. Edition Features This FET has the over temperature shut­down capability sensing to the junction temperature. This FET has the built­in over temperature shut­down circuit in the gate area. And this circuit operation to shut­down the gate voltage in case of high junction , voltage Drain current Drain peak current Body to drain diode reverse drain current Channel dissipation
Hitachi
Original
Hitachi DSA002759

MA3180

Abstract: 2N3904 GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -2.0 V for 100 ns -0.3 V DC , N/A IS+1, IS+2 Positive Current Sense for Channel 1 or 2 6.0 V -0.3 V 1.0 mA 1.0 , 1 GATE(H)1 High Side Switch FET driver pin for channel 1. 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 GND Ground pin for all circuitry contained in the IC , frequency. 14 VCC 15 GATE(L)2 Low Side Synchronous FET driver pin for channel 2. 16
ON Semiconductor
Original
MA3180 MBR0530T1 MTD3302

16SV220

Abstract: CS51312 . Once the total power dissipation in the switching FET is known, the maximum FET switch junction , junction temperature; TA = ambient temperature; PHFET(TOTAL) = total switching (upper) FET losses; RJA = , ensure that the total power dissipation in the FET switch does not cause the power component's junction , voltage positioning, adaptive FET non-overlap time, and remote sense. The CS51312 will operate over a 9V , Times (3.3nF load) s 65ns Adaptive FET Non-overlap Time s Adaptive Voltage Positioning s Power-Good
Cherry Semiconductor
Original
16SV220 FY10AAJ-03A 3525 PWM

in3600

Abstract: t125 switch channels in one package, each channel consisting of a driver circuit controlling a SPST junction FET switch , applications, which permits logic design IH5005 â'"IH5007 -Channel Drivers with SPST FET Switches (Gate Available) directly with the switch function. Logic "1" at the input turns the FET switch ON, and Logic "0" , TYPICAL CHARACTERISTICS (per channel) V|N THRESHOLD vs TEMPERATURE vb v+ â  0 = +12v 0 n v , Available â'¢ Each Channel Complete-Interfaces With Most Integrated Logic â'¢ Low OFF power dissipation, 1
-
OCR Scan
IH5006 in3600 t125 switch

3J83-E

Abstract: id i i f AH5010C MUX S w itches (4-Channel V ersion Show n) O rd er N um ber AHS01OCN See NS Package , the FET switch. N o te 4; Thermal Resistance: N14A.N16A M 14A.M 16A 0JA 92°C/W 115"C /W 2 , ) ensuring that ac signals imposed on the 10V input will not gate the FET "O N .'' Selection of Gain Setting , junction of the op amp. Secondly, the r&s(ON) o f the FET begins to " round" as Is approaches loss- A , "O F F " leakage of a given FET switch Accordingly: =5 kil As an example, if N = 10, A d = 0.1
-
OCR Scan
3J83-E 81-Q43-29 SQ1124

IR5001STRPBF

Abstract: IR5001S typical), the Vout of the IR5001S will be pulled high, turning the channel of the active ORing FET on , flow through an N-channel ORing FET is from source to drain, the output of the IR5001S will be pulled high to Vcc, thus turning the Active ORing FET on. If the current reverses direction and flows from , switch the Active ORing FET off. Typical turn-off delay for the IR5001S is only 130nS, which helps to , redundant processor power +48V input A B IR5001 Vline FET Check Pulse FET A Status Vout
International Rectifier
Original
IR5001STRPBF IR5001STR

AN-1197

Abstract: AN-1207 the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The , the upper FET. It is bootstrapped by means of a ceramic capacitor connected to the channel Switching , 21). Pin 19, PGND2: Power Ground pin of Channel 2. This is the return path for the bottom FET gate , the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with the top gate , FET of a given channel is always ON whenever the upper FET is OFF (except for a narrow shoot-through
National Semiconductor
Original
LM2657 AN-1197 AN-1207 LM2657MTC LM2657MTCX

ISL6580 September 2003 FN9060.2 Integrated Power Stage

Abstract: L568 1.5KV Thermal Resistance JA(oC/W) JB(oC/W) JC(oC/W) N/A 3 Junction to bottom of case . . . N/A Junction to top of case . . . . . . N/A N/A 12.0 Junction to board (Note 2) . . . , . . . . . 21.2 N/A N/A Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . , Biasing gate of External, Synchronous Rectifier, N Channel MOSFETs 1.3 NGATE Pulldown Resistance Pulldown Resistance of ISL6580 for Biasing gate of External, Synchronous Rectifier, N Channel
Intersil
Original
L568 VR10 RIA 39 transistor Primarion PRIMARION px3

NCP5422ADR2G

Abstract: pHfet 4.0 V -0.3 V 1.0 mA 1.0 mA GATE(H)1, GATE(H)2 High-Side FET Driver for Channel 1 or 2 , , GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -2.0 V for 100 ns -0.3 V DC 1.5 A , for channel 1. 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 GND , FET driver pin for channel 2. 16 GATE(H)2 High Side Switch FET driver pin for channel 2 , switching FET is known, the maximum FET switch junction temperature can be calculated: TJ + TA ) [PHFET
ON Semiconductor
Original
NCP5423 NCP5422ADR2G NCP5422A/3 NCP542

2N3904

Abstract: 751E Low­Side FET Driver for Channel 1 or 2 16 V ­0.3 V 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC , channel 1. 2 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 ­ GND , VCC 15 23 GATE(L)2 Low Side Synchronous FET driver pin for channel 2. 16 24 GATE(H)2 High Side Switch FET driver pin for channel 2. FUNCTION Ground pin for all circuitry , switching FET is known, the maximum FET switch junction temperature can be calculated: TJ + TA ) [PHFET
ON Semiconductor
Original
CS5422GDWFR24

fet K 793

Abstract: CI 5022 ) Channel Control Voltage-ON 5V Logic Ckts See Figure 7, Note 3 0.5 0.5 0.5 V V|N(ON) Channel Control , Ckts See Figure 6, Note 3 4.5 4.5 V V|N(0FF) Channel Control Voltage-OFF 15V Logic Ckts See Figure 8 , signals seen at the drain of a junction FET type analog switch can be arbitrarily divided into two , drains. Those devices which feature common drains have another FET in addition to the channel switches , low level TTL logic (5 volts). Each channel simulates a SPDT switch. SPST switch action is obtained by
-
OCR Scan
IH5009-5012 IH5009 IH5010 IH5011 IH5012 IH5014 fet K 793 CI 5022 SPDT FETs M160C 8 pin dip 5022

NCP5424

Abstract: NCP5424D N/A 1.5 A peak, 200 mA DC COMP1, COMP2 Compensation Capacitor for Channel 1 or 2 4.0 V , High-Side FET Driver for Channel 1 or 2 20 V -0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -0.3 V 1.5 A peak, 200 mA DC , SYMBOL FUNCTION 1 GATE(H)1 High Side Switch FET driver pin for channel 1. 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 GND Ground pin for all circuitry
ON Semiconductor
Original
NCP5424DG NCP5424DR2G SOIC-16
Abstract: FET on. As the channel of the N-FET becomes fully enhanced, the (INP â'" INN) will reduce and , flow through an N-channel ORing FET is from source to drain, the output of the IR5001S will be pulled high to Vcc, thus turning the Active ORing FET on. If the current reverses direction and flows from , switch the Active ORing FET off. Typical turn-off delay for the IR5001S is only 130nS, which helps to , IR5001 Vline FET Check Pulse FET A Status Vout Vcc Gnd FETch INN FETst INP International Rectifier
Original

1h5012

Abstract: IH5022 application circuit Current-OFF 15V Logic Ckts V|N= +11V, VA= ±10V 0.04 ±0.5 20 nA v|n(on) Channel Control Voltage-ON 5V Logic Ckts See Figure 7, Note 3 0.5 0.5 0.5 V V|N(ON) Channel Control Voltage-ON 15V Logic Ckts See Figure 8, Note 3 1.5 1.5 1.5 V V|N(OFF) Channel Control Voitage-OFF 5V Logic Ckts See Figure 6, Note 3 , ) 0158-22 DETAILED DESCRIPTION The signals seen at the drain of a junction FET type analog switch can be , addition to the channel switches. This FET, which has gate and source connected such that Vqs=0, is
-
OCR Scan
IH5013 IH5015 IH5016 1h5012 IH5022 application circuit IH5019 1H5011 5009m IH5009-IH5024

LM2657

Abstract: 10TPE68M the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The , the upper FET. It is bootstrapped by means of a ceramic capacitor connected to the channel Switching , 21). Pin 19, PGND2: Power Ground pin of Channel 2. This is the return path for the bottom FET gate , the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with the top gate , FET of a given channel is always ON whenever the upper FET is OFF (except for a narrow shoot-through
National Semiconductor
Original
10TPE68M CMPD6263C 6MV470WG

BUK3F00-50WDFE

Abstract: BUK3F00-50WDFM clear Y[4] 00h 00h 00h 09h PWM_SYNC channel PWM synchronization N 00h 00h 00h 0Ah PWM_SAM_BEGINEND channel PWM sample point begin or end N FFh FFh FFh , trip level for channel 0 N[4] FFh FFh FFh 1Dh CURR_TRIPLEV_CH1 current trip level for channel 1 N[4] FFh FFh FFh current trip level for channel 2 N[4] FFh FFh FFh current trip level for channel 3 N[4] FFh FFh FFh 1Eh 1Fh CURR_TRIPLEV_CH2
NXP Semiconductors
Original
BUK3F00-50WDXX BUK3F00-50WDFE BUK3F00-50WDFM BUK3F00-50WDFY CH30 QFP64 BUK3F00-50WD
Abstract: high, turning the channel of the active ORing FET on. As the channel of the N-FET becomes fully , flow through an N-channel ORing FET is from source to drain, the output of the IR5001S will be pulled high to Vcc, thus turning the Active ORing FET on. If the current reverses direction and flows from , switch the Active ORing FET off. Typical turn-off delay for the IR5001S is only 130nS, which helps to , redundant processor power +48V input A B IR5001 Vline FET Check Pulse FET A Status Vout International Rectifier
Original

IH5009-5012

Abstract: IH5010 junction FET type analog switch can be arbitrarily divided into two categories; those which are less than  , feature common drains have another FET in addition to the channel switches. This FET, which has gate and , low level TTL logic (5 volts). Each channel simulates a SPDT switch. SPST switch action is obtained by , intended for high performance multiplexing and commutating usage. A logic "0" turns the channel ON and a logic "1" turns the channel OFF. ORDERING INFORMATION Basic Part Number Channels Logic Level Packages
-
OCR Scan
IH5017 IH5018 IH5020 Bz 5010 1H5017 IH5022 IH5024 43Q2271

NCP5422A

Abstract: -0.3 V ISOURCE N/A ISINK 1.5 A peak 200 mA DC 1.0 mA Compensation Capacitor for Channel 1 or 2 , Oscillator Resistor High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Ground , BST IS+1 IS-1 VFB1 COMP1 FUNCTION High Side Switch FET driver pin for channel 1. Low Side Synchronous FET driver pin for channel 1. Ground pin for all circuitry contained in the IC. This pin is internally , frequency. Input Power supply pin. Low Side Synchronous FET driver pin for channel 2. High Side Switch FET
ON Semiconductor
Original
Abstract: -0.3 V ISOURCE N/A ISINK 1.5 A peak 200 mA DC 1.0 mA Compensation Capacitor for Channel 1 or 2 , Oscillator Resistor High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Ground , BST IS+1 IS-1 VFB1 COMP1 FUNCTION High Side Switch FET driver pin for channel 1. Low Side Synchronous FET driver pin for channel 1. Ground pin for all circuitry contained in the IC. This pin is internally , frequency. Input Power supply pin. Low Side Synchronous FET driver pin for channel 2. High Side Switch FET ON Semiconductor
Original

ncp5422ag

Abstract: NCP5422ADR2G GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -2.0 V for 100 ns -0.3 V DC , N/A IS+1, IS+2 Positive Current Sense for Channel 1 or 2 6.0 V -0.3 V 1.0 mA 1.0 , for channel 1. 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 GND , FET driver pin for channel 2. 16 GATE(H)2 High Side Switch FET driver pin for channel 2 , , the maximum FET switch junction temperature can be calculated: TJ + TA ) [PHFET(TOTAL) http
ON Semiconductor
Original
ncp5422ag NCP5422AD NCP5422AG

BUK3F00-50WDFE

Abstract: BUK3F00-50WDXX 00h 00h 06h CURR_MEAS channel select analog current measurement; see Section 9.4.2 N , ; see Section 9.3.4 N 00h 00h 00h 0Ah PWM_SAM_BEGINEND channel PWM sample point begin or end; see Section 9.3.4 N FFh FFh FFh 0Ch CHAN_WD_MAP select channel , Section 9.5.2 N[4] FFh FFh FFh 1Dh CURR_TRIPLEV_CH1 current trip level for channel 1 , channel 2; see Section 9.5.2 N[4] FFh FFh FFh 1Fh CURR_TRIPLEV_CH3 current trip
NXP Semiconductors
Original
MS13h 1123-4-H

NCP5422AG

Abstract: GATE(L)1, GATE(L)2 Low-Side FET Driver for Channel 1 or 2 16 V -2.0 V for 100 ns -0.3 V DC , N/A IS+1, IS+2 Positive Current Sense for Channel 1 or 2 6.0 V -0.3 V 1.0 mA 1.0 , for channel 1. 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1. 3 GND , FET driver pin for channel 2. 16 GATE(H)2 High Side Switch FET driver pin for channel 2 , , the maximum FET switch junction temperature can be calculated: TJ + TA ) [PHFET(TOTAL) http
ON Semiconductor
Original
Abstract: mode, the lower FET of a given channel is always ON whenever the upper FET is OFF (except for a narrow , , ILIM2: Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows out of , the floating driver of the upper FET. Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 , of the upper FET. It is bootstrapped by means of a ceramic capacitor connected to the channel , (Pin 21). Pin 19, PGND2: Power Ground pin of Channel 2. This is the return path for the bottom FET gate National Semiconductor
Original
SNVS342A

RSS065P03

Abstract: RSS040P03 chart, { the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND , TECHNICAL NOTE Large Current External FET Controller Type Switching Regulator Dual-output , Regulator Controller 2channels 2) FET(Pch/Nch) Direct Drive 3) Adjustable Oscillator Frequency with External , Circuit Protection SCP 7) Independent ON/OFF Function in Each Channel with Soft Start Pin 8) SSOP ­ B16 , Operating Temperature Range Junction Temperature Storage Temperature Range 70×70×1.6tmm grass-epoxy PCB
ROHM
Original
RSS065P03 RSS040P03 RB081 BD9853AFV

jfet matching fixture

Abstract: MICROWAVE POWER TRANSISTOR IMPEDANCE MEASUREMENT MA1CHWG t- -i CIRCUITpv i I_J *r input i n ] z riâ'"h I OUTPUT ¡ H IMPEDANCE MATCHING r I CtRCUlTPV i I_J p3 W OUTPUT Figure 1 50 Ohm Microstrip Impedance Launcher The 50 n microstrip , channel, high frequency DMOS device. The models do not include the variation of gate capacitance with gate , FET switching characteristics and Finman has reported successful use of the model with RF MOSFETs. The , uses the level 3 MOSFET model because it includes short channel effects and permits control of the
-
OCR Scan
AN001 jfet matching fixture MICROWAVE POWER TRANSISTOR IMPEDANCE MEASUREMENT NMOS MODEL PARAMETERS SPICE RF Power Transistor spice AN002 ZERO Bias diode

SMD IC 2025

Abstract: CS51312-D synchronous FET is know n the maxim um FET switch junction tem perature can be calculated: Tj = TA + [P lfet , Sw itching Regulator Controller for CrU D ual N -Channel MOSFET Synchronous Buck D esign V2,M Control , . Once the total pow er dissipation in the switching FET is known, the maxim um FET switch junction tem perature can be calculated: Tj = Ta + [P hfet (total ) x RojaL where Tj = FET junction temperature; Ta = , losses; V jn = input voltage; Iout = load current; tRisE = MOSFET rise tim e (fro m FET m a n u fa c
-
OCR Scan
SMD IC 2025
Abstract: pin to ground is used to set the ILimit for channel 1. 6 Source 2 Source terminal of the FET , the FET 3. A resistor from this pin to ground is used to set the ILimit for channel 3. 7 Source , ) VENlow - - 1.6 V Characteristics POWER FET (Each Channel) ON Resistance (VCC = 24V, ID , LED current sources. Each channel is comprised of a FET controlled by a current limit circuit that , NUD4330MN Advance Information Three Channel Linear LED Driver The NUD4330 device is an ON Semiconductor
Original
NUD4300 18-LEAD NUD4330MNT NUD4330/D

D-Sub 78-pin female Connector

Abstract: thermocouple d-sub connector Information 3720-MTC-1.5 O F C O N F I D E N C E 3724 Dual 1×30 FET Multiplexer Card 60 , M E A S U R E O F C O N F I D E N C E 3724 Dual 1×30 FET Multiplexer Card 60 , 3724 Dual 1×30 FET Multiplexer Card 60 differential channels, automatic CJC with 3724 , configurations. Dual 1×30 FET multiplexer card Side Text · Optically isolated, solid-state FET relays provide unlimited contact life The solid-state FET relay technology supports fast switching times with
Keithley Instruments
Original
3724-ST D-Sub 78-pin female Connector thermocouple d-sub connector 3791c 3720-MTC-3 thermocouple multiplexer relay a 3700 73/23/EEC EN61010-1 2004/108/EC EN61326-1

5009m

Abstract: IH5010 nA 'lN(OFF) Input Current-OFF 15V Logic Ckts V|N= +11V, VA= ±10V 0.04 ±0.5 20 nA vIN(ON) Channel , the drain of a junction FET type analog switch can be arbitrarily divided into two categories; those , . Those devices which feature common drains have another FET in addition to the channel switches. This FET , low level TTL logic (5 volts). Each channel simulates a SPDT switch. SPST switch action is obtained by , intended for high performance multiplexing and commutating usage. A logic "0" turns the channel ON and a
-
OCR Scan
1H5018 a003
Abstract: . Once the total pow er dissipation in the synchronous FET is know n the maxim um FET switch junction tem , : P s w h (o n ) P s w h (o f f ) P h FET(TOTAL) = P r MSH + PsWH(ON) + PsWH(OFF> where = total , the switching FET is known, the m axim um FET switch junction tem perature can be calculated: P h f e , a k ) x where Tj = FET junction tem perature; Ta = am bient tem perature; P h f e t (t o t a l , , adaptive FET non-overlap time, and remote sense. The CS51311 will operate over an 8.4V to 14V range and is -
OCR Scan
CS51311D14 CS51311DR14

MS13H

Abstract: BUK3F00-50WDFE 00h 00h 06h CURR_MEAS channel select analog current measurement N 00h 00h 00h , channel PWM synchronization N 00h 00h 00h 0Ah PWM_SAM_BEGINEND channel PWM sample point begin or end N FFh FFh FFh 0Ch CHAN_WD_MAP select channel watchdog behavior , N[4] FFh FFh FFh 1Dh CURR_TRIPLEV_CH1 current trip level for channel 1 N[4] FFh FFh FFh current trip level for channel 2 N[4] FFh FFh FFh current trip
NXP Semiconductors
Original
Abstract: ; = high side FET voltage drop due to R d s (o n ); Vl = output inductor voltage drop due to inductor , input voltage; V l f e t = l°w side FET voltage drop due to R d s (o n )V h fet Step3a: Calculation , s (o n )/ which effects regulator efficiency and FET thermal managem ent require­ ments. The , monitor, soft start, adaptive voltage position­ ing, adaptive FET non-overlap time, and remote sense , â'™I S v n chronous Buck D esign V-IMC onlrol Fopnlog) 200rt#>Ti' -
OCR Scan
CS51311GD14 CS51311GDR14
Showing first 150 results.