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MR-80C31/883

Catalog Datasheet MFG & Type PDF Document Tags

1202z

Abstract: MR80C31 59b2'-H60S505ZC SMD TEMIC Part Number HM Î E-65764N/883 HM4-65764N/883 HMI-65764N/883 HM1E-65764M/883 HM4-65764M/883 HM1-65764MW83 HM IK-65764K/883 HM4-65764K/883 HM3 65764K/883 HMH-65764H/883 HM4-65764H/883 HM1 -65764 H/883 HM 1E-65764J-7883 HM4-65764F/883 HM i -65764F/883 M D-80C31/883 MR-80C31/883 MD-80C51xxx/883 MR- -80051 xxx/883 MU-KOC3Ì-16/883 MR-80C3 1-16/883 MD-80C'5lxx\ -16/883 MR 80
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OCR Scan
5962-8506402MQA 5962-89X 1202z MR80C31 J65608 8kx8 sram LCC48 80C31 TEMIC 5962-3829409MXA 5962-3829409MYC 5962-3829409MZA 5962-3829411MXA 5962-382941IMYC 2-3H29411MZA

P-Channel Depletion-Mode

Abstract: MD80C31 RAM 12 MHZ MD-80C31/883 CDIL40 600 MILs 5962-8506401MXC 8 Bit uC 128 Bytes RAM 12 MHZ MR-80C31/883 LCC44 5962-8506402MQA 8Bit uC 4K Bytes ROM 12MHZ MD-80C51xxx/883 CDIL40 , Analog Switches Siliconix Part No. Description DG129AP/883 Dual DPST JFET Analog Switch DG180AA/883 Dual SPST 10­Ohm JFET Switch DG180AP/883 Dual SPST 10­Ohm JFET Switch DG181AA/883 Dual SPST 30­Ohm JFET Switch DG181AP/883 Dual SPST 30­Ohm JFET Switch DG182AA/883 Dual SPST
Temic Semiconductors
Original
P-Channel Depletion-Mode MD80C31 JANTX2N4858 JANTX2N6661 5962-9089101MEA SI9110AK 2N5547JANTX 2N5547JANTXV 2N4856JAN 2N6660JANTX 2N4856JANTX 2N6660JANTXV

TRANSISTOR B737

Abstract: MD80C31 µC 4K bytes RAM 16 MHz MR­80C31/883 MR­80C51xxx/883 MR­80C31­16/883 MR­80C51xxx­16/883 LCC44 , authorities and performing internal audits, TEMIC ­ MHS declared self­compliance to MIL­883 on January 1991 , parts tested to either of MIL­883 quality flows, level B or S, in accordance with MIL­I­38510. When DSCC , Bit µC 4K bytes ROM 12 MHz 8 Bit µC 128 bytes RAM 16 MHz 8 Bit µC 4K bytes RAM 16 MHz TEMIC P/N MD­80C31/883 MD­80C51xxx/883 MD­80C31­36/883 MD­80C51xxx­36/883 Package CDIL40 600 mils wide CDIL40 600
Temic Semiconductors
Original
TRANSISTOR B737 smd TRANSISTOR code marking 8K 67202FV PGA300 marking code RAD SMD Transistor npn ERC32SIM TM2010 SCC9000

8506402QA

Abstract: 8200901ja 82HS641B 592 80C31 80C31 80C31 80C31 80C31 80C51 80C51 80C51 80C51 80C3M 6 80C31-16 30C3M 6 80C31-16
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OCR Scan
7802301EA 8200803KA 8506401MQ 8506402QA 26LS232 8200901ja 7700801CA 7801601KA 7802001EA 78020Q12A 7802001MEA 7802001MFA

80C154

Abstract: P80C31 : Dry Pack - M ISCELLANEOUS 883 MIL STD 883D cond. B/S SB Compliant with SCC9000/B SC Compliant with , 80C31/80C51 80C32/80C52 80C154/83C154 83C154D 80C31E : RT version 80C32E/80C52E: RT version -PACKAGE , Examples P-80C31 ID-80C32 X X -80C 31 D -80C 32-1 M D -80C 51IB Standard plastic 8-bit microcontroller , . Dice probed at 25°C - packaged in chip-tray. 80C32 in Cer dip - 16 MHz. 80C51 according to MIL STD 883
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OCR Scan
80C154 P80C31 SCC9000/C 80C31/80C51 P-80C31

8kx8 eprom pin diagram

Abstract: XTAL 12MH | 3S3011M 0000104 3 The future. .today. EDH 607C31 pPak Family 8/12 MHz Microcomputer 80C31 Based, CMOS , high density microcomputer modules based on the industry-standard 80C31 single chip, CMOS microcontroller architecture from Intel. The module incorporates an 80C31, an 8Kx8 or32Kx8 EPROM, an 8Kx8 SRAM and , externally, with a total 80C31 address range of 64K bytes for both program and data storage, giving 128K bytes of accessible memory. All EDI Military Module Components are 100% processed to MIL-STD-883, test
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OCR Scan
MCS-51 8kx8 eprom pin diagram XTAL 12MH static ram 8KX8 F800H INTEL 24 PIN CERAMIC DUAL-IN-LINE PACKAGE MIL-STD-883 687C31 697C31 697C31-12PC 687C31-8CI

UPAK

Abstract: sram 8kx8 memory map . Microcomputer 80C31 Based, CMOS 8Kx8 EEPROM plus 8Kx8 SRAM The EDH 685C31 pPAK from EDI is a new series of high density microcomputer modules based on the industry-standard 80C31 single chip, CMOS microcontroller architecture from Intel. The module incorporates an 80C31, an 8Kx8 EEPROM, an 8Kx8 SRAM and a Logic Control , 80C31 address range of 56K bytes for both program and data storage, giving 112K bytes of accessible memory. (See memory map on p. 3) All EDI Military Module Components are 100% processed to MIL-STD-883
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OCR Scan
UPAK sram 8kx8 memory map 685C31-8PC 685C31-8CI 685C31-12CI 685C31-8CMHR 685C31-12CMHR

sram 8kx8 memory map

Abstract: UPAK . Microcomputer 80C31 Based, CMOS 8K or 32Kx8 EPROM plus 8Kx8 SRAM The EDH 607C31 pPAK family from EDI Is the first in a series of high density microcomputer modules based on the industry-standard 80C31 single chip, CMOS microcontroller architecture from Intel. The module incorporates an 80C31, an 8Kx8 or32Kx8 EPROM , added externally, with a total 80C31 address range of 64K bytes for both program and data storage, giving 128K bytes of accessible memory. All EDI Military Module Components are 100% processed to MIL-STD-883
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OCR Scan
Ram 64k 8kX8 80C31 Development Board 80C31 instruction set 607G31 697C31-8CI 697C31-12CI 687C31-8CMHR

80C31 instruction set

Abstract: 80C31 80C31 Based, CMOS 8Kx8 EEPROM plus 8Kx8 SRAM The EDH 685C31 ^PAK from EDI is a new series of high density microcomputer modules based on the industry-standard 80C31 single chip, CMOS microcontroller architecture from Intel. The module incorporates an 80C31, an 8Kx8 EEPROM, an 8Kx8 SRAM and a Logic Control , 80C31 address range of 56K bytes for both program and data storage, giving 112K bytes of accessible memory. (See memory map on p. 3) All EDI Military Module Components are 100% processed to MIL-STD-883
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OCR Scan
BOC31 80c31 application 685C31-12PC GU185RF

8kx8 eprom pin diagram

Abstract: sram 8kx8 memory map , im h Features 80C31 Based · Industry Standard MCS-51 Architecture · Speeds of 3.5-8 MHz or3 , with 80C31 Single 5V (±10%) Supply Operation The EDH 607C31 ^PAK family from EDI Is the first in a series of high density microcomputer modules based on the industry-standard 80C31 single chip, CMOS microcontroller architecture from Intel. The module incorporates an 80C31, an 8Kx8 or32Kx8 EPROM, an 8Kx8 SRAM and
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OCR Scan
MAX11213 687C31-8PC 687C31-12PC 697C31-8PC 687C31-12CI 687C31-12CMHR 697C31-8CMHR

80C51-12

Abstract: MATRA MHS 80c31 Pack Flow /883 MIL compliant (1) Only for 80C31 at commercial range. 20 MATRA MHS Rev. D , 80C31/80C51 CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller Description TEMIC's 80C31 and , design of the TEMIC 80C31/80C51 allows to reduce system power consumption by bringing the clock , -level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. D 80C31 : Romless version of the 80C51 D 80C31/80C51 -V4 : Very Low Voltage version Vcc : 1.8-5.5 V Freq : 0-4 MHz
Temic Semiconductors
Original
80C51-12 MATRA MHS 80c31 temic 8051 XTAL 12 MHz 80c31 MHS DIL40 80C31/80C51-L16 80C31/80C51-12 80C31/80C51-20 80C51C 80C51T

i87C51

Abstract: i87C52 80C31 80C51 DS5000FP DS5001FP SAB8051 SAB8031 AT89C55 i87C54 i80C54 P80C54 P87C54 , AT 89CXX-X X X X - 5 X XXXXX Processing Blank = Standard /883 = MIL-STD-883, Class B , Plastic Leaded Chip Carrier A = Hermetic Stressed S = SOIC (Small Outline Integrated Circuit) B = 883 , : XXX Secrete ROM: FXXX Device Type 80C31/80C51 80C32/80C52 80C154/83C154 80C154D 80C31µ/80C51µ
Atmel
Original
Z08614 Z0802 68HC711E9 ST7271N5B1 ST72T71N5B1 i87C51 i87C52 i80c51 i87c51fa 89CXX AT89C51 87C51 SC80C31 SC80C51 SC87C51 PIC16C73

80C31 instruction set

Abstract: 80c31 "pin compatible" Product Brief May 1997 Silicon Suite for ISDN Products and Services Overview 80C31/32/51/52 8-Bit Microcontroller Description Features The Lucent 80C31 macro is an 8 , . The 80C51/80C31 architecture has been optimized for sequential real-time control applications, and , 80C31 macro is functionally equivalent and cycle-by-cycle compatible with industry-standard 80C51/80C31 products. s s s s s s s s s s s s s s s s s s
Lucent Technologies
Original
80c31 "pin compatible" lucent 40 microcontroller bus system "test bus" 80C31/32/51/52 80C51/80C31

WSI PSD312

Abstract: 80C31 Peripheral Family with 80C31/80C51 Microcontrollers By Dan Kinsella Introduction The 80C51 , using the 80C51 microcontroller family along with the WSI PSD3XX family. A simple 80C31 system will be , external memory accesses needed (80C31, 80C51 with external accesses, etc.). The PSD3XX family helps solve , (logic, SRAM, EPROM, etc.) onto a single chip. Figure 1 illustrates a typical 80C31 system and how it is , . Figure 1. ADDRESS DECODER PLD '373 CS ADDRESS PSEN 80C31 µC DATA EPROM A/D
WaferScale Integration
Original
WSI PSD312 PSEN cs 3.1 80c31 interface PSD3xx 8751 microcontroller architecture of 8031 microcontroller 74HC14

89c31

Abstract: MHS 80C31 October 1992 DATA SHEET 80C31/80C51 CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31/80C51 :0 TO 12 MHz 80C31/80C51-1 : 0 T016 MHz 80C31-S/80C51-S : 0 TO 20 MHz 80C31A0CS1-L: 0 TO 6 MHz WTTH 2.7 V , RANGE: COMMERCIAL, INDUSTRIAL, AUTOMOTIVE AND MILITARY INTRODUCTION MHS's 80C31 and 80C51 are high , self-aligned silicon gate CMOS process (SAJI VI). The fully static design of the MHS 80C31 /80C51 allows to , saved and all other functions are inoperative. The 80C31 is identical to the 80C51 except that it has
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OCR Scan
80C51F 89c31 MHS 80C31 T016 MHS-C51 80c31a 80C31/80C51-1 80C31-S/80C51-S 80C31/R DDG3731

EP-1140

Abstract: 80552 83C053, 83C054, 87C054, 87C055 pod 12MHz 8031 pod 12MHz 80C31 pod 16MHz 80C31 pod 20MHz 80C31 pod 24MHz 80C31 pod 30MHz 80C31 pod 33MHz 80C31 pod 12MHz 8032 pod 12MHz 80C32 pod 16MHz 80C32 pod , 8031­12PC 8031­16PC 8031­20PC 8031­24PC 8032­12PC 8032­16PC 8032­20PC 0.5 to 12MHz 8031, 80C31 0.5 to 16MHz 8031, 80C31 0.5 to 20MHz 8031, 80C31 0.5 to 24MHz 8031, 80C31 0.5 to 12MHz 8031, 80C31, 8032, 80C32 0.5 to 16MHz 8031, 80C31, 8032, 80C32 0.5 to 20MHz 8031, 80C31, 8032, 80C32 IM
Philips Semiconductors
Original
EP-1140 80552 8052 microcontroller philips 80552 microcontroller philips LCPX5X40 80C552 Development Board 80C51- 8752/C52/C252/C51FA 87C752 87C751 P8051DB S87C00KSD
Abstract: time of 160 hours at 125°C with V cc = 6-9V ± 0.25V, following guidelines in MIL-STD-883, Method , conjunction with the commercial 80C51BH/80C31 BH data sheet, 270064-008. 7-101 Septem ber 1990 O rder , in MIL-STD-883 Method 1015 (Test Condition D). Examples: P80C31BH indicates 80C31BH in a plastic -
OCR Scan
80C31BH/80C51BH 80C51BH/80C31 LD80C51BH 80C51BH

80c51/31 MHS

Abstract: October 1992 IlM l 80C31/80C51 DATASHEET CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31/80C51-L : 0 TO 6 MHz WITH 2.7 V < Vcc < 6 V 80C51F : 80C51 WITH PROTECTED ROM 80C31/80C51:0 TO 12 MHz 80C31/80C51-1: 0 T 0 16 MHz 80C31-S/80C51-S : 0 TO 20 MHz FEATURES â  . . . . . . , . MHSâ'™s 80C31 and 80C51 are high performance CMOS versions of the 8031/8051 NMOS single chip 8 bit |iC , inoperative. The fully static design of the MHS 80C31/80C51 allows to reduce system power consumption by
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OCR Scan
80c51/31 MHS 80C31/80C51-L DDD3731
Abstract: Ãjg 4 19 93 electronic October 1992 80C31/80C51 DATA SHEET CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31/80C51 :0 TO 12 MHz 80C31/80C51-1 : 0 T 0 16 MHz 80C31-S/80C51 -S : 0 TO 20 MHz 80C31/B0CS1-L : 0 TO 6 MHz WTTH 2.7 V < VÅ" < 6 V 80C51F : 80C51 WITH PROTECTED ROM , , INDUSTRIAL, AUTOMOTIVE AND MILITARY INTRODUCTION MHSâ'™s 80C31 and 80C51 are high performance CMOS , inoperative. The 80C31 is identical to the 80C51 except that it has no on-chip ROM. The fully static -
OCR Scan
80C31-S/80C51 80C31/B0CS1-L

MATRA MHS 80c51

Abstract: MHS 80C31 Temic MATRA MHS 80c31/80c51 CMOS 0 to 42 MHz Single-Chip 8 Bit Microcontroller Description MHS's 80C31 and 80C51 are high performance SCMOS versions of the 8031/8051 NMOS single chip 8 bit p.c. The fully staüc design of the MHS 80C31/80C51 allows to reduce system power consumption by bringing the , inoperative. The 80C31 is identical to the 80C51 except that it has no on-chip ROM. MHS's 80C31/80C51 are manufactured using SCMOS process which allows them to run from 0 up to 42 MHz with VCC = 5 V. MHS's 80C31 and
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OCR Scan
MATRA MHS 80c51 80C51-30 ANM031 80C51-36 80C31/80C51-25 80C31/80C51-30 80C31/80C51-36 80C31-40 80C31-42
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