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Part : MB81V17800A-60PFTN Supplier : Fujitsu Manufacturer : Master Electronics Stock : 219 Best Price : $14.98 Price Each : $17.78
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MB81V17805A-60 Datasheet

Part Manufacturer Description PDF Type
MB81V17805A-60LPFTN Fujitsu 2 M x 8 BITS HYPER PAGE MODE DYNAMIC RAM Original
MB81V17805A-60PFTN Fujitsu 2 M x 8 BITS HYPER PAGE MODE DYNAMIC RAM Original
MB81V17805A-60PJ Fujitsu 2 M x 8 BITS HYPER PAGE MODE DYNAMIC RAM Original

MB81V17805A-60

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I ^ UKÊ^ÊÊUÊHnKHÊm ÊÊÊ MB81V17805A-60 , voltage higher than maximum rated voltages to this high impedance circuit. 1 MB81V17805A-60/-60L , (Low Power) 2 MB81V17805A-60/-60L/-70/-70L Fig. 1 - MB81V17805A DYNAMIC RAM -B L O C K , Capacitance, DQi to DQs MB81V17805A-60/-60L/-70/-70L PIN ASSIGNMENTS AND DESCRIPTIONS 28-Pin SOJ (TOP , A c 1 A ,C 12 A ,C 13 Vg c Q 14 A e 4 MB81V17805A-60/-60L/-70/-70L RECOMMENDED OPERATING -
OCR Scan
MB81V17805A-60/60L/-70/70L F9611
Abstract: MEMORY CMOS 2 M x 8 BITS HYPER PAGE MODE DYNAMIC RAM MB81V17805A-60/60L/-70/70L CMOS 2,097 , MB81V17805A-60/-60L/-70/-70L â  ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit , normal bend leads, order as MB81 V17805A-xxPFTN and MB81V17805A-xxLPFTN (Low Power) 2 MB81V17805A-60 , PF dq 3 MB81V17805A-60/-60L/-70/-70L â  PIN ASSIGNMENTS AND DESCRIPTIONS 28-Pin SOJ , power supply No connection MB81V17805A-60/-60L/-70/-70L â  RECOMMENDED OPERATING CONDITIONS -
OCR Scan
MB81V17805A-60/-60L/-70/-70L 28-LEAD LCC-28P-M07 C28058S-2C FPT-28P-M14 F28040S-1C
Abstract: 2 M x 8 BITS HYPER PAGE MODE DYNAMIC RAM MB81V17805A-60/60L/-70/70L CMOS 2,097,152 x 8 BITS Hyper , um rated voltages to this high im pedance circuit. 1 MB81V17805A-60/-60L/-70/-70L â  ABSOLUTE , MB81 V17805A-xxPFTN and MB81V17805A-xxLPFTN (Low Power) 2 MB81V17805A-60/-60L/-70/-70L Fig. 1 , MB81V17805A-60/-60L/-70/-70L â  PIN ASSIGNMENTS AND DESCRIPTIONS 28-Pin SOJ (TOP VIEW) , connection MB81V17805A-60/-60L/-70/-70L â  RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min -
OCR Scan
Abstract: × 8 BITS HYPER PAGE MODE DYNAMIC RAM MB81V17805A-60/60L/-70/70L CMOS 2,097,152 × 8 BITS Hyper , impedance circuit. 1 To Top / Lineup / Index MB81V17805A-60/-60L/-70/-70L s ABSOLUTE MAXIMUM , Power) 2 To Top / Lineup / Index MB81V17805A-60/-60L/-70/-70L Fig. 1 ­ MB81V17805A DYNAMIC , Capacitance, DQ1 to DQ8 CDQ 7 pF 3 To Top / Lineup / Index MB81V17805A-60/-60L/-70/-70L s , power supply No connection To Top / Lineup / Index MB81V17805A-60/-60L/-70/-70L s RECOMMENDED Fujitsu
Original
DS05-10195-2E
Abstract: FUJITSU LIMITED 1 3?HT?Sb DD2G4S1 E7b - PRELIMINARYEdition 2.0 MB81V17805A-60/70 MB81V17805A-60L , 4 t]7Sti GGSGHSE 1D2 -P R E L IM IN A R Y E d i t i o n 2 .0 MB81V17805A-60/70 MB81V17805A-60L , Y Edition 2.0 MB81V17805A-60/70 MB81V17805A-60L770L DC CHARACTERISTICS (Recommended , MB81V17805A-60/70 MB81V17805A-60U70L AC CHARACTERISTICS otherwise noted.) (At recommended operating , Edition 2.0 MB81V17805A-60/70 MB81V17805A-60L/70L AC CHARACTERISTICS (Continued) (At -
OCR Scan
MB81V 374S7S MB81V17805A-60/70 MB81V17805A-60L/70L QD2D47S 0D2D47L
Abstract: ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ­ PRELIMINARY ­ Edition 2.0 MB81V17805A-60/70 MB81V17805A-60L/70L Fig. 1 , PRELIMINARY ­ Edition 2.0 MB81V17805A-60/70 MB81V17805A-60L/70L PIN ASSIGNMENTS AND DESCRIPTIONS 28 , ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ­ PRELIMINARY ­ Edition 2.0 MB81V17805A-60/70 MB81V17805A-60L/70L RECOMMENDED OPERATING , MB81V17805A-60/70 MB81V17805A-60L/70L DC CHARACTERISTICS (Recommended operating conditions unless , ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ­ PRELIMINARY ­ Edition 2.0 MB81V17805A-60/70 MB81V17805A-60L/70L AC CHARACTERISTICS Fujitsu
Original
MB81V17805A-60/70/60L/70L

f2804

Abstract: DYNAMIC RAM MB81V17805A-60/60L/-70/70L CMOS 2,097,152 × 8 BITS Hyper Page Mode Dynamic RAM s , higher than maximum rated voltages to this high impedance circuit. 1 MB81V17805A-60/-60L/-70/-70L , MB81V17805A-××PFTN and MB81V17805A-××LPFTN (Low Power) 2 MB81V17805A-60/-60L/-70/-70L Fig. 1 ­ MB81V17805A , Capacitance, DQ1 to DQ8 CDQ 7 pF 3 MB81V17805A-60/-60L/-70/-70L s PIN ASSIGNMENTS AND , connection MB81V17805A-60/-60L/-70/-70L s RECOMMENDED OPERATING CONDITIONS Parameter Notes Symbol
Fujitsu
Original
f2804 F9705

A6070M

Abstract: 780sa (Average power supply current) MB81V17805A-60/60 L d Q(L) -10 - 10 120 10 120 mA 110 1.0 , HAS = CAS = V |_ | 1.0 - - 500 120 - - 110 lCC2 CMOS level MB81V17805A-60/60 L ICC3 MB81V17805A- 70/70 L MB81V17805A-60/60 L ICC4 MB81V17805A-70/70L MB81V17805A-60/60 L ICC5 MB81V17805A-70/70L , S = min. to 300ns V ih ^ V cc-0.2 V , V|L < 0.2V MB81V17805A-60/70 Battery backup current , supply current) MB81V17805A -60L770L - 300 MB81V17805A-60/60L ^C C 9 MB81V17805A-70/70 L
-
OCR Scan
A6070M 780sa 7805A PI 81v17805a 81V17805 LCC-28P-M MB81V1780SA V17805
Abstract: DRAM (5) i DRAM - Low Voltage Versions (CMOS) Vcc= +3.3V±0.3V, Ta=0°C to +706C Power Consumption max. (mW) Standby Operating Mods (CMOS level) Organization (Wxb) Part Number Access Time max. (ns) Cycle Time min. (ns) Packages SOJ TSOP MB81V17800A-60 M B81V 17800A-70 M B81V17800A-60L MB81V17800A-70L ®MB81 V17800B-50 ©MB81V17800B-60 ©MB81V17800B-50I ©MB81V17800B-60L 2Mx8 MB81V17805A-60 MB81V17805A-70 MB81V17805A-60L MB81V17805A-70L ©MB81V17805B-50 ®MB81 V17805B-60 ©MB81V17805B -
OCR Scan
MB81V17805B-50L V17805B-60L

3654P

Abstract: DRAM 4464 -50L 50[13]*1 90[35]*3 468 MB81V17800B-60L 60[15]*1 110[40]*3 396 MB81V17805A-60 60[35]*2 104[25]*4 432 MB81V17805A-70 70[40]*2 124[30]*4 396 MB81V17805A-60L
Fujitsu
Original
MB814405D MB814260 3654P DRAM 4464 jeida dram 88 pin 4464 dram 1024M-bit MB814400A MB814400D MB814405C MB814400C MB814100D

60JG

Abstract: MB81V17805A-60PJ May 1996 Revision 1.0 DATA SHEET DM2M2V645-60JG-IS 16MByte (2M x 64) CMOS EDO DRAM Module - 3.3V General Description The DM2M2V645-60JG-IS is a high performance, EDO (Extended Data Out) 16-megabyte dynamic RAM module organized as 2M words by 64 bits, in a 168-pins, dual-in-line (DIMM) memory modules. The module utilizes eight, Fujitsu MB81V17805A-60PJ CMOS 2Mx8 EDO dynamic RAMs in a surface mount package on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved
Fujitsu
Original
60JG MP-DRAMM-DS-20309-5/96

MB81V17805A-60PJ

Abstract: June 1996 Revision 1.0 DATA SHEET EDC2UV6482-(60/70)(J/T)G-S 16MByte (2M x 64) CMOS EDO DRAM Module - 3.3V General Description The EDC2UV6482-(60/70)(J/T)G-S is a high performance, EDO (Extended Data Out) 16-megabyte dynamic RAM module organized as 2M words by 64 bits, in a 168-pins, dual-in-line (DIMM) memory modules. The module utilizes eight, Fujitsu MB81V17805A-60PJ CMOS 2Mx8 EDO dynamic RAMs in a surface mount package on an epoxy laminate substrate. Each device is accompanied by a
Fujitsu
Original
MP-DRAMM-DS-20309-6/96

2MX16

Abstract: DRAM (5) i DRAM - Low Voltage Versions (CMOS) Vcc= +3.3V±0.3V, Ta=0°C to +706C Power Consumption max. (mW) Standby Operating Mods (CMOS level) Organization (Wxb) Part Number Access Time max. (ns) Cycle Time min. (ns) Packages SOJ TSOP MB81V17800A-60 M B81V 17800A-70 M B81V17800A-60L MB81V17800A-70L ®MB81 V17800B-50 ©MB81V17800B-60 ©MB81V17800B-50I ©MB81V17800B-60L 2Mx8 MB81V17805A-60 MB81V17805A-70 MB81V17805A-60L MB81V17805A-70L ©MB81V17805B-50 ®MB81 V17805B-60 ©MB81V17805B
Fujitsu
Original
2MX16 DM2M2V725- MP-DRAMM-DS-20315-5/96