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LVDCI18

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: _15, LVDCI_18, LVDCI_25, and LVDCI_33. IOB R Z0 Virtex-II DCI UG002_c2_047_120400 Figure 2-96 , LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_15 LVDCI_DV2_25 LVDCI_DV2_33 The following , _15, LVDCI_18, LVDCI_25, LVDCI_33 Using these buffers configures the outputs as controlled impedance drivers Xilinx
Original
DS031

LVDS25

Abstract: LVDS-25 _33 (1) LVDCI_25 (1) LVDCI_DV2_25 (1) LVDCI_18 (1) LVDCI_DV2_18 (1) LVDCI_15 (1) LVDCI_DV2_15 (1) GTL_DCI , (I & II), LDT, ULVDS, BLVDS LVCMOS18, GTL, GTLP, LVDCI_18, LVDCI_DV2_18 HSTL (I, II, III, & IV , , BLVDS, ULVDS_25 1.8V LVCMOS18, LVDCI_18, LVDCI_DV2_18, LVDS_33, LVDS_25, LDT, ULVDS_25 1.5V LVCMOS15 , _33, LVDS_25, LVDSEXT_25, LDT, BLVDS, ULVDS_25 LVCMOS18, LVDCI_18, LVDCI_DV2_18, LVDS_33, LVDS_25, LDT , _25, LVDCI_DV2_25, LVDS_33, LVDSEXT_33, LVDS_25, LVDSEXT_25, LDT, BLVDS, ULVDS_25 LVCMOS18, LVDCI_18
Xilinx
Original
LVDS25 LVDS-25 LVDSEXT25 LVDSEXT-25 16X1S DS031-2 LVCMOS33 LVCMOS25 PCI33 PCI66 DS031-1

LVDCI25

Abstract: LVDCI18 are: LVDCI_15, LVDCI_18, LVDCI_25, and LVDCI_33. Figure 2-97 illustrates a controlled impedance driver , following are valid DCI attributes for output drivers: · · · · 342 LVDCI_15 LVDCI_18 LVDCI_25 LVDCI , . LVDCI_15, LVDCI_18, LVDCI_25, LVDCI_33 Using these buffers configures the outputs as controlled
Xilinx
Original
LVDCI25 LVDCI18 HSTL_ UG012

LVDSEXT-25

Abstract: 16x1D 2.5 N/A Series LVDCI_DV2_25 (1) 2.5 2.5 N/A Series LVDCI_18 (1) 1.8 1.8 , _25, LVDCI_DV2_25, SSTL2_DCI (I & II), LDT, ULVDS, BLVDS 1.8 V LVCMOS18, GTL, GTLP, LVDCI_18, LVDCI_DV2 , _25, LVDS_33, LVDSEXT_33, LVPECL_33, LVDS_25, LVDSEXT_25, LDT, BLVDS, ULVDS_25 LVCMOS18, LVDCI_18 , _25, SSTL2_I_DCI, SSTL2_II_DCI LVCMOS18, LVDCI_18, LVDCI_DV2_18, LVDS_33, LVDSEXT_33, LVPECL_33, LVDS , _33, LVPECL_33, LVDS_25, LVDSEXT_25, LDT, BLVDS, ULVDS_25 LVCMOS18, LVDCI_18, LVTTL, LVDCI
Xilinx
Original
16x1D LVPECL33 LVDS-33 LVDCI15 LVDS33 XC2V80 DS031-3 DS031-4

SPARTAN-3 XC3S400

Abstract: SPARTAN-3 XC3S400 PQ208 - 0.20VCCO 0.70VCCO LVCMOS18, LVDCI_18, LVDCI_DV2_18(4) 1.7 1.8 1.9 - - , LVCMOS12(4) 24 ­24 Note 3 Note 3 LVDCI_15, LVDCI_DV2_15 LVCMOS18(4) LVDCI_18 , _25 0.18 0.21 ns LVCMOS18 0.24 0.28 ns RSDS_25 0.43 0.50 ns LVDCI_18 , HSTL_II_DCI_18 0.75 0.86 ns LVDCI_18 0.81 0.94 ns HSTL_III_18 0.28 0.32 ns
Xilinx
Original
SPARTAN-3 XC3S400 SPARTAN-3 XC3S400 PQ208 XC3S1500 SPARTAN-3 BOARD XC3S400 SPARTAN-3 XC3S400 tq144 UG112 DS099-3 DS099-1 DS099-2 DS099-4

SPARTAN-3 XC3S400 PQ208

Abstract: SPARTAN-3 XC3S400 tq144 _18, HSTL_II_DCI_18 HSTL_III_18, HSTL_III_DCI_18 LVCMOS12(3) LVCMOS15, LVDCI_15, LVDCI_DV2_15(3) LVCMOS18, LVDCI_18 , _18 LVCMOS12(4) 2 4 6 LVCMOS15(4) 2 4 6 8 12 LVDCI_15, LVDCI_DV2_15 LVCMOS18(4) 2 4 6 8 12 16 LVDCI_18 , , LVDCI_15, LVDCI_DV2_15 LVCMOS18, LVDCI_18, LVDCI_DV2_18 LVCMOS25, LVDCI_25, LVDCI_DV2_25 LVCMOS33, LVDCI , 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVDCI_18 LVDCI_DV2_18 LVCMOS25 ­0.18 ­0.15 ­0.15 ­0.13 0.08 0.07 , Timing Measurement at I/Os (Continued) Inputs VREF Signal Standard LVCMOS18 LVDCI_18 LVDCI_DV2
Xilinx
Original
BLVDS-25 xc3s200 xc3s50 xilinx 3040 XC3S400 PQ208 dcm XC3S400 FG1156

SPARTAN-3 XC3S400 PQ208

Abstract: SPARTAN-3 XC3S400 tq144 _15, LVDCI_DV2_15(4) LVCMOS18, LVDCI_18, LVDCI_DV2_18(4) LVCMOS25(4,5), LVDCI_25, LVDCI_DV2_25(4) LVCMOS33, LVDCI , _18 LVCMOS12(4) 2 4 6 LVCMOS15(4) 2 4 6 8 12 LVDCI_15, LVDCI_DV2_15 LVCMOS18(4) 2 4 6 8 12 16 LVDCI_18 , _15 LVCMOS18 LVDCI_18 LVDCI_DV2_18 LVCMOS25 0.44 0.36 0.51 0.29 0.51 0.51 0.51 0.37 0.36 0.39 0.45 0.63 0.42 , 1.51 1.32 Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVDCI_18 LVDCI_DV2 , _15 LVDCI_DV2_15 LVCMOS18 LVDCI_18 LVDCI_DV2_18 LVCMOS25 LVDCI_25 LVDCI_DV2_25 LVCMOS33 LVDCI_33 LVDCI_DV2
Xilinx
Original
HSLVDCI33 LVPECL25 FG320 HSLVDCI18 XC3S1500 XC3S2000 XC3S4000 XC3S5000

XC3S400 pin inputs

Abstract: SPARTAN-3 XC3S400 pin _18, HSTL_III_DCI_18 LVCMOS12(3) LVCMOS15, LVDCI_15(3) LVCMOS18, LVDCI_18(3) LVCMOS25, LVDCI_25(3,4) LVCMOS33, LVDCI , _18 HSTL_II_18, HSTL_II_DCI_18 HSTL_III_18, HSTL_III_DCI_18 LVCMOS12(3) LVCMOS15, LVDCI_15(3) LVCMOS18, LVDCI_18
Xilinx
Original
XC3S400 pin inputs SPARTAN-3 XC3S400 pin TMS 3450 DS099

hyperlynx

Abstract: Device Reliability report XILINX impedance controlled driver. The results shown in Figure 4-42 show the waveforms from an LVDCI_18 driver
Xilinx
Original
hyperlynx Device Reliability report XILINX ibis format FG256 FG456 FF672 FF896 XC2VP20 FF1152

XC3S400

Abstract: HSLVDCI25 ) LVCMOS15, LVDCI_15, LVDCI_DV2_15(4) LVCMOS18, LVDCI_18, LVDCI_DV2_18(4) LVCMOS25(4,5), LVDCI_25, LVDCI_DV2 , _18 LVCMOS12(4) 2 4 6 LVCMOS15(4) 2 4 6 8 12 LVDCI_15, LVDCI_DV2_15 LVCMOS18(4) 2 4 6 8 12 16 LVDCI_18 , LVDCI_15 LVDCI_DV2_15 LVCMOS18 LVDCI_18 LVDCI_DV2_18 LVCMOS25 LVDCI_25 LVDCI_DV2_25 0.44 0.36 0.51 0.29 , 6 mA 8 mA 12 mA 16 mA LVDCI_18 LVDCI_DV2_18 LVCMOS25 Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Fast
Xilinx
Original
HSLVDCI25 XC3S400FT XC3S200 minimum system HSLV SSTL18II Spartan-3 FPGA Family SSTL18 DS312 DS313 DS314-1

XQR5VFX130

Abstract: XQR5VFX130C VCCO ­ 0.4 Note (2) Note (2) LVCMOS18, LVDCI18 ­0.3 35% VCCO 65% VCCO VCCO + 0.3 , LVDCI_33 0.92 2.13 2.13 ns LVDCI_25 0.92 2.16 2.16 ns LVDCI_18 1.00
Xilinx
Original
DS692 UG190 UG191 UG193 UG198 UG197 XQR5VFX130 XQR5VFX130C Virtex-5QV XQR5VFX130-CF1752 XQR5V UG194

xc2v1000

Abstract: XC2V80 _18 HSTL IV_18 SSTL2 I SSTL2 II SSTL3 I SSTL3 II AGP LVDCI_33 LVDCI_25 LVDCI_18 0.00 0.00 0.11 0.42 0.98 , _33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_33 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI GTLP_DCI , LVDCI25 LVDCI18 3.3 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8 1.5 1.5 1.25 1.25 0.9 0.9 0 3.3 LVDCI15 HSTL
Xilinx
Original
xc2v1000 XC2V6000-ff1152 XC2V40

XQR5VFX130-CF1752

Abstract: XQR5VFX , LVDCI18 â'"0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO â'" 0.45 Note (3) Note (3 , LVDCI_33 1.11 2.51 2.51 ns LVDCI_25 0.92 2.40 2.40 ns LVDCI_18 1.00
Xilinx
Original
XQR5VFX DS192 UG520 UG203

Virtex-II

Abstract: XAPP623 _18 LVDCI_18 0.42 0.43 0.49 ns Data Input Delay Adjustments Standard-specific data input , ns TOLVDCI_18 LVDCI_18 0.84 0.87 0.95 ns TOLVDCI_15 LVDCI_15 1.82 1.88 , 3.3 LVDCI25 1M 0 1.25 0 PCI-X - rising edge 25 0 0.94 LVDCI18 1M 0
Xilinx
Original
Virtex-II XAPP623 XC2V6000 XC2V1500 XC2V2000 XC2V250 XAPP689 XC2V8000

XQR5VFX130

Abstract: XQR5VFX130-CF1752 0.7 1.7 VCCO + 0.3 0.4 VCCO ­ 0.4 Note (2) Note (2) LVCMOS18, LVDCI18 ­0.3 , LVDCI_33 1.11 2.51 2.51 ns LVDCI_25 0.92 2.40 2.40 ns LVDCI_18 1.00
Xilinx
Original
FPGA Virtex 6 Ethernet CF1752 XAPP858

XC6VLX550T

Abstract: XC6VLX130T ) LVCMOS18, LVDCI18 ­0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO ­ 0.45 Note(4) Note , _25 0.54 0.61 0.70 2.05 2.14 2.26 2.05 2.14 2.26 ns LVDCI_18 0.58 0.65
Xilinx
Original
XC6VLX550T XC6VLX130T XC6VSX475T XC6VLX240T XC6VSX315T-FF1156 XC6VLX760-FF1760 DS152

2V3000

Abstract: power supply module for calculator SR 51 II _18 LVDCI_18 0.39 0.43 0.49 ns Data Input Delay Adjustments Standard-specific data input , ns TOLVDCI_18 LVDCI_18 1.40 1.54 1.77 ns TOLVDCI_15 LVDCI_15 2.96 3.26
Xilinx
Original
2V3000 power supply module for calculator SR 51 II 2V4000 2V1000 ULVDS-25 XC2V1000 Pin-out TREG32

XC2VP30-FF896

Abstract: XC2VP7FF896 _18 HSTL_III_18 HSTL_IV_18 SSTL2_I SSTL2_II LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2 , 12 mA 16 mA LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI
Xilinx
Original
XC2VP70 XC2VP30-FF896 XC2VP7FF896 xc2vp70ff1517 xc2vp40ff1148 XC2VP100 XC2VP100FF1704 DS083-3

LVDCI25

Abstract: XC2VP20 I SSTL3 II LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI , Standard LVCMOS15, Fast, 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2
Xilinx
Original
rocket battery 150 XC2VP50
Abstract: , LVDCI18 â'"0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO â'" 0.45 Note (3) Note (3 , _25 0.92 2.40 2.40 ns LVDCI_18 1.00 2.89 2.89 ns LVDCI_15 1.10 2.69 Xilinx
Original

BF957

Abstract: wireless encrypt _25 LVDCI_DV2_25 LVDCI_18 LVDCI_DV2_18 LVDCI_15 LVDCI_DV2_15 GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI , _25, SSTL2_DCI (I & II), LDT, ULVDS, BLVDS LVCMOS18, GTL, GTLP, LVDCI_18, LVDCI_DV2_18 HSTL (I, II, III, & IV , _25 LVDCI_18 LVDCI_15 DCI Half Impedance LVDCI_DV2_33 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 SSTL2 Class
Xilinx
Original
BF957 wireless encrypt CS144 FG676 FF1517 BG575 BG728

XC5VLX220

Abstract: XC5VSX95T LVTTL LVCMOS33, LVDCI33 LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 PCI33_3(5) PCI66 , (Continued) TIOPI I/O Standard -3 LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2
Xilinx
Original
XC5VLX220 XC5VSX95T 16-bit adder code using xilinx code XC5VLX85T DS202

16x1D

Abstract: "Digital Delay Lines" 2.5 N/R Series LVDCI_18 (1) 1.8 1.8 N/R Series LVDCI_DV2_18 (1) 1.8 1.8 , LVTTL N/R N/R N/R LVCMOS18 N/R N/R N/R LVCMOS33 N/R N/R N/R LVDCI_18 , Buffers 3.3 V LVDCI_33 LVDCI_DV2_33 LVDCI_25 LVDCI_DV2_25 LVDCI_18 LVDCI_DV2_18 1.5
Xilinx
Original
XC2V3000 1 of 8 multiplexer circuit diagram of 32-1 multiplexer circuit diagram of 8-1 multiplexer design logic Xilinx jtag cable pcb Schematic

XC6VLX130T

Abstract: XC6VLX240T DC Input and Output Levels I/O Standard LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 , LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 LVPECL_25 HSTL_I_12 HSTL_I_DCI , _25, HSLVDCI_25 LVDCI_18, HSLVDCI_18 LVDCI_15, HSLVDCI_15 I/O Standard Attribute RREF ( ) 100 100 1M 1M
Xilinx
Original
XC6VLX75T DSP48E1

xc5vlx110t models

Abstract: XC5VLX110T-FF1738 LVTTL LVCMOS33, LVDCI33 LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 PCI33_3(5) PCI66 , LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI GTLP_DCI LVPECL
Xilinx
Original
xc5vlx110t models XC5VLX110T-FF1738 XC5VSX35T FF1760

virtex5 rocketio

Abstract: vdrint LVTTL LVCMOS33, LVDCI33 LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 PCI33_3(5) PCI66 , (Continued) TIOPI I/O Standard -3 LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2
Xilinx
Original
virtex5 rocketio vdrint
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