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LF3312s

Catalog Datasheet MFG & Type PDF Document Tags

LF3312

Abstract: independent data/video streams can be written into a shared linear address space using multiple LF3312s. , space. A PIP solution using LF3312s can buffer and synchronize up to 16 independent video/data streams. This is made possible by placing N LF3312s in a `semi-cascade' mode, where all inputs and outputs are , LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). The write enables AWEN/BWEN and AIEN , Note Application: Two Cascaded LF3312s ­ 2-frame PIP or Multi-source Buffering Connection In the
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LF3312

LF3312

Abstract: LF3312s Depth Expansion through Cascading LF3312 - Application Note OVERVIEW Cascading multiple LF3312s for depth expansion is easy. The usable 24bit address space is simply extended for every , LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables AWEN/BWEN and AIEN , Application Note Device Connection: Two Cascaded LF3312s - General Purpose Connection NOTE: The above diagram connects two cascaded LF3312s in the most general-purpose case. Here, all pointer-control pins
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12FC00 LF3312s LF33 12FBFF 25F7FF

LF3312

Abstract: LF3312BGC manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth and width , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , . Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read , cascade. When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write , -0 determines the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial
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LF3312BGC position sensitive diode circuit

LF3312

Abstract: video stream frame-based synchronization. For high-resolution video, multiple LF3312s can be cascaded and used in the same , synchronization), the LF3312's Input Masking feature should be used. The two input mask control pins are AIEN and
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video stream
Abstract: Pointers can be manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth , user requiring more storage can cascade up to sixteen LF3312s into a larger array. A great deal of , space. When cascading LF3312s, each device's write and read pointers behave identically. The LF3312 was , used to define each device's place in the cascade. When cascading LF3312s, only singe-channel modes are , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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AOUT11 AIN11 AOUT10 AIN10 BOUT11 BOUT10

LF3312 m

Abstract: LF3312 manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth and width , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , . Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read , cascade. When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write , -0 determines the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial
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LF3312 m BIN11 BIN10

LF3312

Abstract: verilog code for image rotation Pixel Mapping - Video Flipping LF3312 - Application Note OVERVIEW With the LF3312's flexible memory address architecture, a sequence of input data can easily be mapped to any locations within the memory space. The following paper clearly illustrates a selectable video flipping application whereby an input image can be buffered by the LF3312 and emerge unchanged or rotated by 180degrees. ADDRESS , following pin diagram shows the correct port and pin connections of one of the LF3312s in this application
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verilog code for image rotation synchronous counter using 4 flip flip green pixel rotation Vertical line driver for Full Frame image rotation verilog

LF3312

Abstract: FIFO manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth and width , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , . Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read , cascade. When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write , Address (CA6-0) CHIP_ADDR6-0 determines the LF3312's address on the two-wire microprocessor bus. Each
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FIFO LF3312 o marking apf 12MBIT
Abstract: external 24bit address LF3312s may be Cascaded for depth and width, supporting HDTV, Multiframe SDTV, and , storage can cascade up to sixteen LF3312s into a larger array. A great deal of memory addressing , space. When cascading LF3312s, each device's write and read pointers behave identically. The LF3312 was , used to define each device's place in the cascade. When cascading LF3312s, only singe-channel modes are , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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Abstract: manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth and width , user requiring more storage can cascade up to sixteen LF3312s into a larger array. A great deal of , , the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read pointers , . When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables AWEN , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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Abstract: Pointers can be manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth , user requiring more storage can cascade up to sixteen LF3312s into a larger array. A great deal of , space. When cascading LF3312s, each device's write and read pointers behave identically. The LF3312 was , used to define each device's place in the cascade. When cascading LF3312s, only singe-channel modes are , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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AFLD marking

Abstract: manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth and width , storage can cascade up to sixteen LF3312s into a larger array. A great deal of memory addressing , port (ADDR). CHIP_ADDR6-0 - Chip Address (CA6-0) CHIP_ADDR6-0 determines the LF3312's address on the , interface. WEB - Parallel Microprocessor Interface Write Enable When LOW, WE enables writing to the LF3312's , Enable When LOW, RE enables reading from the LF3312's Instruction Registers with the parallel
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AFLD marking

marking apf

Abstract: LF3312 · Write or Read Pointers can be manipulated in real-time based on external 24bit address LF3312s , up to sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered , , the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read pointers , cascade. When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write , -0 determines the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial
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Abstract: Pointers can be manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth , user requiring more storage can cascade up to sixteen LF3312s into a larger array. A great deal of , space. When cascading LF3312s, each device's write and read pointers behave identically. The LF3312 was , used to define each device's place in the cascade. When cascading LF3312s, only singe-channel modes are , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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Abstract: address LF3312s may be Cascaded for depth and width, supporting HDTV, Multiframe SDTV, and other high , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , . Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read , . When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables AWEN , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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Abstract: address LF3312s may be Cascaded for depth and width, supporting HDTV, Multiframe SDTV, and other high , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , . Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read , . When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables AWEN , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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Abstract: manipulated in real-time based on external 24bit address LF3312s may be Cascaded for depth and width , user requiring more storage can cascade up to sixteen LF3312s into a larger array. A great deal of , additional device that is cascaded. Internally, the LF3312 has a 24bit address space. When cascading LF3312s , device's place in the cascade. When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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LF3312

Abstract: Features in the Two Random Access (nonFIFO) Modes: · Up to 100 MHz Data Rate LF3312s may be Connected in , more storage can cascade up to sixteen LF3312s into a larger array. The device is controlled by sixteen , the ADDR CHIP_ADDR6-0 - Chip Address CHIP_ADDR6-0 determines the LF3312's address on the two-wire , enables writing to the LF3312's Instruction Registers with the parallel micrprocessor interface. PRE - Parallel Microprocessor Interface Read Enable When LOW, RE enables reading from the LF3312's Instruction
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ITUR-656 LF3312QC10
Abstract: address LF3312s may be Cascaded for depth and width, supporting HDTV, Multiframe SDTV, and other high , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , . Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device's write and read , . When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables AWEN , the LF3312's address on the two-wire microprocessor bus. Each LF3312 chip's 7-bit two-wire serial Logic Devices
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Abstract: or Read Pointers can be manipulated in real-time based on external 24bit address LF3312s may be , up to sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered , cascading LF3312s, each deviceâ'™s write and read pointers behave identically. The LF3312 was designed to , ] (BASE_ADDR) is used to define each deviceâ'™s place in the cascade. When cascading LF3312s, only Logic Devices
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Abstract: : · Up to 83 MHz Data Rate LF3312s may be Connected in Parallel for HDTV, Multiframe SDTV, etc , sixteen LF3312s into a larger array. The device is controlled by sixteen instruction words of eight bits , Chip Address (CA6-0) CHIP_ADDR6-0 determines the LF3312's address on the two-wire microprocessor bus , Write Enable When LOW, WE enables writing to the LF3312's Instruction Registers with the parallel , the LF3312's Instruction Registers with the parallel micrprocessor interface. LOGIC Devices Logic Devices
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LF3312QC12
Abstract: or Read Pointers can be manipulated in real-time based on external 24bit address LF3312s may be , sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the , 24bit address space. When cascading LF3312s, each deviceâ'™s write and read pointers behave identically , LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables AWEN/BWEN and AIEN Logic Devices
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