500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

KXY 23

Catalog Datasheet MFG & Type PDF Document Tags

HMS51232J4V

Abstract: marking HX 6 pin _ } kx^ kx] kx\ kx[ } kxZ kxY kxX kxZX h] h\ h[ hZ hY hX hW } hXZ hXY hXX hXW h` h_ h^ kxW 15ns access kxX^ kxX_ kxX` } kxYW kxYX kxYY kxYZ } kxY[ kxY\ kxY] kxY^ } kxY_ kxY` kxZW hX_ Access time : 15, 17, 20 and 25ns High-density 2MByte design , -18 512Kx8 512Kx8 8 512Kx8 8 8 DQ8-15 DQ0-7 512Kx8 8 DQ16-23 DQ24
HANBiT Electronics
Original
HMS51232J4V marking HX 6 pin KXY 23 HMS51232M4/Z4

lc4128v-5t100c

Abstract: 8B10B include 256 data characters named Dx.y and 12 control characters named Kx.y. Figure 2. The 8b/10b Coding Scheme Dx.y code group Kx.y or LSB MSB 8b H G F b c E d LSB , 10100 001011 21 10101 101010 22 10110 011010 23 10111 111010 or 000101 , 's the corresponding Kx.y row in Table 3 1, If dataout has 6 one's 1 10-bit dataout from the (RD+) column of 0, If dataout has 4 one's the corresponding Kx.y row in Table 3 1, If dataout has 5 one
Lattice Semiconductor
Original
RD1012 LFX1200B-03FE680C lc4128v-5t100c 8B10B 8B10B ansi encoder K2371 LC4128V-5T100C 5000MX LC5512MV-5Q208C OR4E02-3BA352

KYY 72

Abstract: F31FSS-04V-KX . Circuit No. J-310 5 4 3 2 1 3.8 (.150) Land on the soldering side: 2-3 (.118) dia , (.200±.002) 1.27±0.05 (.050±.002) 1.1±0.1 (.043 ±.004) dia. Land on the soldering side: 2-3 (.118 , (.300) 3.81 (.150) pitch F31FMS-06V-KXY 100 Keying [16.7 (.657)] Keying No. Series No , ) Land on the soldering side: 2-3 (.118) dia. min. Q'ty / box Note: Contact JST for the headers , B06B-F31MK-GGXYR Y Y F31FMS-06V-KXY 116 XY Type S06B-F31MK-GGXYR X XY Type X XY Type
JST
Original
KYY 72 F31FSS-04V-KX F31FDS-08V-K BF3M-002GF-M2 S03B-F31SK-GGXR S03B-F31SK-GGYR B-F32SK-GGXR F32MSF- F32MSP- J320M F32FMS- J320S

CZE3

Abstract: / / N:2? :8 E= 01 23 7 86 ; 3456 9: ; 1 >2?@>8 : 2356 , : Y 6 :4? 4 :3 =6 / S / c S @=P Lc Z de` N fVU P < P @= 23 1 / 272462>4: ? QR7= @ , ?@> - :? 5@A 0 LE= 06G:= : 3 / LE= / @77:= : C 23[ 3 , kit iv sxy kxy jxy zxy sxy kixy ksxy jixy jjxy wwxy zpxy u{xy kiixy ksixy jjixy wwixy zpixy suixy u{ixy {jixy kiiixy kv s|y jv j|y wv w|y zv p|y uv {|y ki|y iv sxy kxy
Fenghua Advanced Technology
Original
CZE3 464E68 O77342

lattice machxo lcmxo1200c

Abstract: set-3b named Dx.y and 12 control characters named Kx.y. Figure 2. The 8b/10b Coding Scheme Dx.y code group Kx.y or LSB MSB 8b H G F b c E d LSB 10b a MSB e , 21 10101 101010 22 10110 011010 23 10111 111010 or 000101 24 11000 , 's the corresponding Kx.y row in Table 3 1, If dataout has 6 one's 1 10-bit dataout from the (RD+) column of 0, If dataout has 4 one's the corresponding Kx.y row in Table 3 1, If dataout has 5 one
Lattice Semiconductor
Original
LCMXO1200C-3T100C LFXP2-5E-5M132C LFECP6E-5T144C LC51024MB-52F484C lattice machxo lcmxo1200c set-3b K2801 5000MX6 LC4256B-3T100C

TK3723

Abstract: wizardlink 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 , 17 18 19 21 23 24 25 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 , conditions PARAMETER VDD TEST CONDITIONS MIN Supply voltage 2.3 NOM MAX 2.5 2.7 , , worst case pattern (1) TX_CLK Static, VDDA and VDD = Max PLL startup lock time VDD, VDDC = 2.3 V , IOH = ­1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN
Texas Instruments
Original
TLK2541 TK3723 wizardlink epon SLLS779B

TK3723

Abstract: Teknovus 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 , 17 18 19 21 23 24 25 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 , 2.3 NOM MAX 2.5 2.7 Frequency = 2.5 Gbps, PRBS pattern PD Power dissipation , startup lock time VDD, VDDC = 2.3 V Data acquisition time (1) mA mW 825 Low Power Mode , High-level output voltage IOH = ­1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL
Texas Instruments
Original
Teknovus serdes wireless

TK3723

Abstract: Teknovus 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 , 17 18 19 21 23 24 25 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 , conditions PARAMETER VDD TEST CONDITIONS MIN Supply voltage 2.3 NOM MAX 2.5 2.7 , , worst case pattern (1) TX_CLK Static, VDDA and VDD = Max PLL startup lock time VDD, VDDC = 2.3 V , IOH = ­1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN
Texas Instruments
Original
Abstract: 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 , 17 18 19 21 23 24 25 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 , CONDITIONS MIN Supply voltage 2.3 NOM MAX 2.5 2.7 Frequency = 2.5 Gbps, PRBS pattern , , VDDC = 2.3 V Data acquisition time TA V 700 Frequency = 2.5 Gbps, PRBS pattern Supply , 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN GND 0.25 tr(slew) Slew Texas Instruments
Original
ISO/TS16949

SC04B-F35DK-GGR

Abstract: -06V-KXX F31FMS-06V-KYY F31FMS-06V-KXY 100 YY XY 100 100 Material (16.7) Glass-filled PBT, UL94V , A A A B B06B-F31MK-GGXY S06B-F31MK-GGXY Y F31FMS-06V-KXY Y XY Type X , . J300 SERIES/J320M Receptacle housing Circuits Keying F32FMS-06V-KXX F32FMS-06V-KYY F32FMS-06V-KXY F32FMS-10V-KXX F32FMS-10V-KYY F32FMS-10V-KXY F32FMS-12V-KXX F32FMS-12V-KYY F32FMS-12V-KXY F32FMS , housing (Free hanging type) C Line No. Circuits Keying F32MDF-06V-KXX F32MDF-06V-KYY F32MDF-06V-KXY
JST Manufacturing
Original
SC04B-F35DK-GGR F31FDS-20V-K J310D F31PFS-10KU J340F F34PFF-20VKA F34PFF-20SCA
Abstract: 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 , RXD17 RXD18 RXD19 RX_CLK 75 78 79 1 3 4 5 6 8 9 12 13 14 16 17 18 19 21 23 24 25 63 62 61 58 57 56 55 , Frequency = 2.6 Gbps, worst case pattern (1) TX_CLK Static, VDDA and VDD = Max VDD, VDDC = 2.3 V Frequency = 1.25 Gbps or 2.5 Gbps, K28.5 D16.2 pattern (3 sigma values) ­40 0.1 TEST CONDITIONS MIN 2.3 NOM 2.5 280 , % ns ns TYP 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns tsu RXD[0:19] setup to RX_CLK th RXD[0:19 Texas Instruments
Original

TK3723

Abstract: 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 , RXD17 RXD18 RXD19 RX_CLK 75 78 79 1 3 4 5 6 8 9 12 13 14 16 17 18 19 21 23 24 25 63 62 61 58 57 56 55 , Frequency = 2.6 Gbps, worst case pattern (1) TX_CLK Static, VDDA and VDD = Max VDD, VDDC = 2.3 V Frequency = 1.25 Gbps or 2.5 Gbps, K28.5 D16.2 pattern (3 sigma values) ­40 0.1 TEST CONDITIONS MIN 2.3 NOM 2.5 280 , 0.5 2.5 2.5 1.5 1.5 45% 50% 55% ns ns TYP 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns tsu RXD[0:19
Texas Instruments
Original
TLK25
Abstract: -06V-KXX F31FMS-06V-KYY F31FMS-06V-KXY 100 YY XY 100 100 Material (16.7) Glass-filled PBT , F31FMS-06V-KXY Y XY Type X XY Type X XY Type Note: Packaging method is indicated in â , -06V-KYY F32FMS-06V-KXY F32FMS-10V-KXX F32FMS-10V-KYY F32FMS-10V-KXY F32FMS-12V-KXX F32FMS-12V-KYY F32FMS-12V-KXY , -06V-KYY F32MDF-06V-KXY F32MDF-12V-KXX F32MDF-12V-KYY F32MDF-12V-KXY 16.4 16.97 20.32 7.62 X X , 20 YY 4.0 5.0 XY F32MDP-06V-KXX F32MDP-06V-KYY F32MDP-06V-KXY F32MDP-12V-KXX F32MDP -
Original
F34PFF-20VKB F34PFF-20SCB J-340 F34FFC-20V-K J4000 J4200S

TK3723

Abstract: Teknovus 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 , RXD17 RXD18 RXD19 RX_CLK 75 78 79 1 3 4 5 6 8 9 12 13 14 16 17 18 19 21 23 24 25 63 62 61 58 57 56 55 , Frequency = 2.6 Gbps, worst case pattern (1) TX_CLK Static, VDDA and VDD = Max VDD, VDDC = 2.3 V Frequency = 1.25 Gbps or 2.5 Gbps, K28.5 D16.2 pattern (3 sigma values) ­40 0.1 TEST CONDITIONS MIN 2.3 NOM 2.5 280 , % ns ns TYP 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns tsu RXD[0:19] setup to RX_CLK th RXD[0:19
Texas Instruments
Original
Abstract: 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 , RXD17 RXD18 RXD19 RX_CLK 75 78 79 1 3 4 5 6 8 9 12 13 14 16 17 18 19 21 23 24 25 63 62 61 58 57 56 55 , Frequency = 2.6 Gbps, worst case pattern (1) TX_CLK Static, VDDA and VDD = Max VDD, VDDC = 2.3 V Frequency = 1.25 Gbps or 2.5 Gbps, K28.5 D16.2 pattern (3 sigma values) ­40 0.1 TEST CONDITIONS MIN 2.3 NOM 2.5 280 , 0.5 2.5 2.5 1.5 1.5 45% 50% 55% ns ns TYP 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns tsu RXD[0:19 Texas Instruments
Original
SLLS779A

TK3723

Abstract: 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 , RXD17 RXD18 RXD19 RX_CLK 75 78 79 1 3 4 5 6 8 9 12 13 14 16 17 18 19 21 23 24 25 63 62 61 58 57 56 55 , Frequency = 2.6 Gbps, worst case pattern (1) TX_CLK Static, VDDA and VDD = Max VDD, VDDC = 2.3 V Frequency = 1.25 Gbps or 2.5 Gbps, K28.5 D16.2 pattern (3 sigma values) ­40 0.1 TEST CONDITIONS MIN 2.3 NOM 2.5 280 , 0.5 2.5 2.5 1.5 1.5 45% 50% 55% ns ns TYP 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns tsu RXD[0:19
Texas Instruments
Original

TK3723

Abstract: TLK2541 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 , 17 18 19 21 23 24 25 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 , conditions PARAMETER VDD TEST CONDITIONS MIN Supply voltage 2.3 NOM MAX 2.5 2.7 , , worst case pattern (1) TX_CLK Static, VDDA and VDD = Max PLL startup lock time VDD, VDDC = 2.3 V , IOH = ­1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN
Texas Instruments
Original
Abstract: 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 , RXD17 RXD18 RXD19 RX_CLK 75 78 79 1 3 4 5 6 8 9 12 13 14 16 17 18 19 21 23 24 25 63 62 61 58 57 56 55 , Frequency = 2.6 Gbps, worst case pattern (1) TX_CLK Static, VDDA and VDD = Max VDD, VDDC = 2.3 V Frequency = 1.25 Gbps or 2.5 Gbps, K28.5 D16.2 pattern (3 sigma values) ­40 0.1 TEST CONDITIONS MIN 2.3 NOM 2.5 280 , % ns ns TYP 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns tsu RXD[0:19] setup to RX_CLK th RXD[0:19 Texas Instruments
Original

B10B-JPF3MK-GKXXR

Abstract: jfa-j300 . Q'ty / box XX 3.81 F31FMS-06V-KXX F31FMS-06V-KYY F31FMS-06V-KXY 100 YY XY 100 100 , F31FMS-06V-KXY Y XY Type X XY Type X XY Type Note: Packaging method is indicated in . , -06V-KXX F32FMS-06V-KYY F32FMS-06V-KXY F32FMS-10V-KXX F32FMS-10V-KYY F32FMS-10V-KXY F32FMS-12V-KXX F32FMS-12V-KYY F32FMS-12V-KXY F32FMS-20V-KXX Under planning Under planning XX A Line No. 5.08 YY 6 , -06V-KYY F32MDF-06V-KXY F32MDF-12V-KXX F32MDF-12V-KYY F32MDF-12V-KXY 16.4 16.97 20.32 X 7.62
-
Original
B10B-JPF3MK-GKXXR jfa-j300 P18B-F36TK-GFAR JPF3FMS-10V-KXX BF3F-71GF-P2 F35FDC-02V-K J42PF-02SCA J42PF-02SCB J-4200

TK3723

Abstract: TLK2541 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 , 17 18 19 21 23 24 25 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 , conditions PARAMETER VDD TEST CONDITIONS MIN Supply voltage 2.3 NOM MAX 2.5 2.7 , , worst case pattern (1) TX_CLK Static, VDDA and VDD = Max PLL startup lock time VDD, VDDC = 2.3 V , IOH = ­1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN
Texas Instruments
Original
Showing first 20 results.