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LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939CMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
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LTC2938HDE#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939HMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy

IC 7447 PIN CONFIGURATION FIGURE

Catalog Datasheet MFG & Type PDF Document Tags

ubx-g5010

Abstract: UBX-G5000-BT ) UBX-G5000-BT u-blox 5 Baseband Processor, 100 pin CVBGA UBX-G0010-QT u-blox 5 RF Front-End IC , u-blox 5 RF Front-End IC, 24 pin MLF(QFN) Architecture Low IF: 3 MHz I and Q RTC Input , Digital I/O Configurable time pulse 2 EXTINT interrupt inputs 10 Configuration Pins (UBX-G5010) 12 Configuration Pins (UBX-G5000) 2.5 m CEP 2.0 m CEP Cold starts: Warm starts , Limits -40°C to 85°C Single Package Chipset 515 m/s (1000 knots) UBX-G5010: 56 Pin
u-blox
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UBX-G0010 IC 7447 PIN CONNECTION DIAGRAM 7447 pin configuration ic 7447 pin configuration IC 7447 PIN CONFIGURATION FIGURE 32 pin 5 x 5 mlf UBLOX UBX-G5000/UBX-G0010 G5-X-06042-A1

TIM-LC-0-000-0

Abstract: U-blox tim-lc TTL input compatible) serial ports and easyto-use boot time configuration pins. The combination of , Extensively configurable · Boot-time configuration pins · Fully EMI shielded · Active antenna support , time-frequency search bins · 4 Hz position update rate · ANTARIS Positioning Engine · ATR0600 RF front-end IC · ATR0620 Baseband IC with ARM7TDMI inside · DGPS and SBAS (WAAS, EGNOS) support · FixNOWTM power saving mode · Operating voltage 2.7 to 3.3 V · Battery supply pin for internal backup memory and real
u-blox
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TIM-LC-0-000-0 U-blox tim-lc AEK-LS-0-000-0 DGPS Receiver module U-blox AG GPS chip of 5v G3-MS3-03002-F

xtal 32.768

Abstract: xtal 32768 UBX-G5000-A00-BT u-blox 5 Baseband Processor, 100 pin BGA UBX-G0010-A00-QT u-blox 5 RF Front-End IC, 24 , channel tracking engine The UBX-G5000 baseband IC will be capable, via a simple software upgrade into , OTP 32 bits One-Time Programmable memory for device configuration 10 s 10 s 10 s External , Multipath Suppression NMEA, UBX Binary General-Purpose I/O Ports Package: BGA 56 Pin QFN GPIOs , Functionality Single Package 56 Pin QFN, 8 x 8 x 0.9 mm LNA Built-In (no external LNA required
u-blox
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xtal 32.768 xtal 32768 UBX-G5010-A00-ST ic 7447 pin diagram of ic 7447 IC 7447 diagram circuit G5-X-06042-P4

atmel 0742

Abstract: ATR0610 .5 3 Pin Configuration , -06006-P1 Preliminary Mechanical Specification Page 5 your position is our focus 3 Pin Configuration 3.1 Pinout Figure 3-1: Pinning PLLP6 (Not Scaled) 3.2 Signal Description Pin 1 2 3 4 5 6 , +41 1722 7447 info@u-blox.com ATR0610 ANTARIS 4 GPS Low Noise Amplifier Features · Low power consumption < 10 mW · Very small, PLLP6 package (1.6 x 2.0 mm) · Low noise figure ·
u-blox
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CH-8800 atmel 0742 0920 ATMEL IC 7447 16 PIN CONNECTION DIAGRAM ATR0610-PQQ 8 905 958 460 G4-X-06006-P1 2002/95/EC

8085 interfacing 8155

Abstract: binary to bcd conversion 8085 ): (Pin 21): . 0 4 ';-8) 8 LED DISPLAY WHEN USING 7447 SEGMENT DECODER 1 0 , 7447 TE R11 9 R12 15 8 AD7555 IC' R13 14 TO DGND R7-R13 200" I , inexpensive, medium-precision amplifiers a scale factor drift of o.2ppmf C is achieved. ~ PIN CONFIGURATION VREF> f1l . , os . DATA ORDERING - AD7555 TOP VIEW Model Do , Temperature Range ~~- AD7555BD - ,- -AD7555KN " 28 Pin Side Brazed Ceramic -25°C to +85°C
Analog Devices
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8085 interfacing 8155 binary to bcd conversion 8085 IC 7447 bcd to 7 segment decoder IC 7447 BCD circuit of bcd to 7 segment decoder using ic 7447 Two Digit counter by using 7447 AD7555/MCS-85 28-PIN ALLOY42

TIM-LA-0-000-0

Abstract: GPS.G3-X-03002 not used 8 GPSMODE5 I Boot time configuration pin Internal pull-down, leave open if not used 9 GPSMODE3 I Boot time configuration pin 10 VDD18_Out O 1.8V supply output , used 24 GPSMODE2 I Boot time configuration pin Internal pull-up, leave open if not used 25 GPSMODE6 I Boot time configuration pin Internal pull-up, leave open if not used 26 GPSMODE7 I Boot time configuration pin Internal pull-up, leave open if not used 27 AADET_N
u-blox
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TIM-LA-0-000-0 GPS.G3-X-03002 ic 7447 block diagram u-blox America tim-la GPS.G3-MS3-01001 G3-MS3-04022 G3-MS3-01001 G3-X-03002

TIM-LF

Abstract: internal diagram of 7447 IC +41 1722 7447 info@u-blox.com TIM-LL GPS Receiver Module Abstract This document describes the , ] I/Os VBAT LDO Address Bus Data Bus ATR0620 1.8V LDO Figure 1: Block Diagram , rate · ANTARIS Positioning Engine ATR0600 RF front-end IC · ATR0620 Baseband IC with ARM7TDMI inside · ATR0610 Low noise amplifier IC · · FLASH memory · DGPS and SBAS (WAAS, EGNOS , pin for internal backup memory and real time clock · Industrial operating temperature range ­40
u-blox
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TIM-LF internal diagram of 7447 IC tim-lf-9 TIM-LL ttl 7447 data sheet TIM-LL-0-000 G3-MS3-04035

ATR0601

Abstract: u-blox GPS BASEBAND : ± 0.05 mm 4 Pin Configuration 4.1 Pinout Figure 4-1: Pinning QFN24 ATR0601 - Data Sheet , .7 4 Pin Configuration , -06005-P2 Preliminary Pin Configuration Page 8 your position is our focus 5 Electrical Specification 5.1 , +41 1722 7447 info@u-blox.com ATR0601 ANTARIS 4 GPS RF Front-End Features · Very low power , Basis: 04/06 P2 12. July 2006 GzB Basis: 06/06: Figure 7.3, Table 7.3 and Table 7.4
u-blox
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u-blox GPS BASEBAND GPS chip qfn24 ublox GPS A115 ATR0601-PFQW ATR0621 G4-X-06005-P2

EWTS82

Abstract: panasonic gyroscope +41 1722 7447 info@u-blox.com TIM-LR Sensor-Based GPS Module Abstract This document describes , Modified section 1.7 and 5 B 6. July 04 GzB Modified figure 1, section 1.4: Min. 4 Mbit Flash , [32 Bit] RTC I/O s VBAT LDO VCC ATR0620 VCC LDO VCC Figure 1: Block , rate · ANTARIS Positioning Engine ATR0600 RF front-end IC · ATR0620 Baseband IC with ARM7TDMI inside · ATR0610 Low noise amplifier IC · · · FLASH memory Dead Reckoning (DR) with Enhanced
u-blox
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EWTS82 panasonic gyroscope env-05g MURATA ENV-05g EWTS84 ENV-05F G3-MS3-04002-D G3-MS3-04048

GPS.G3-X-03002

Abstract: connecting diagram for ic 7447 10 9 8 7 6 5 4 3 2 1 Figure 3: SAM-LS Interface and Pin Assignment Connector: Flat flex cable , +41 1722 7447 info@u-blox.com SAM-LS GPS Smart Antenna Module Abstract This document , Modified section 5 A 6. July 04 GzB Modified figure 1, section 1.4, removed section 1.6 B , Memory Bus VCC ATR0620 LDO GND VCC Figure 1: Block Diagram SAM-LS - Data Sheet , ATR0600 RF front-end IC · ATR0620 Baseband IC with ARM7TDMI inside · ATR0610 Low noise amplifier IC ·
u-blox
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connecting diagram for ic 7447 SAM-LS-0-000 IC 7447 specification FPC CONNECTOR 20pin IPC-SM-840B design of Circular Patch Antenna G3-SA-03002-B

truth table for ic 74138

Abstract: ALU IC 74183 cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS , ation. Figure 1. A+PLUS Block Diagram A+PLUS Simulation Virtual Logic Analyzer (V LA) Functional , , 7443, 7444, 7445, 7446, 7447, 7448, 7449, 74138, 74139, 74154, 74155, 74156 7470, 7471, 7472, 7473 , levels, and a d u al-w in d o w display m ode sim plifies schem atic entry. See Figure 2. Schem atics can
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OCR Scan
truth table for ic 74138 ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table

7447B

Abstract: mc7457vg1000 Thermal Characteristics . . . . . . . . . . . 10 6. Pin Assignments . . . . . . . . . . . . . . . . . . . , MPC7447 is identical to the MPC7457 except that it does not support the L3 cache interface. Figure 1 shows , Figure 1. MPC7457 Block Diagram 512-Kbyte Unified L2 Cache Controller L1 Service Queues Line Block 0 , duration as shown in Figure 2. Figure 2 shows the undershoot and overshoot voltage on the MPC7457 , 0.7 V Not to exceed 10% of tSYSCLK Figure 2. Overshoot/Undershoot Voltage The MPC7457 provides
Freescale Semiconductor
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7447B mc7457vg1000 MPC7457EC MPC7450 MPC7455 MPC7445 MPC7451 MPC7441

IC 7448

Abstract: IC 7446 | | Pin Configuration Pin Description 7443/44 1 7445/46 2 Pin 7447/48 2 7449/50 2 , Outputs · 140ms(min) Reset Timeout Period · Small 5-Pin and 6-Pin SOT23 Packages (Push-Pull , brownout conditions (see Figure 8 Typical Operating Circuit). /RESET changes from high to low whenever , output logic state for VDD inputs 1V. Figure 1 Typical Operating Circuit · Manual Reset Input , channel-select button for 6.72s to reset the system.) Figure 2 PT7M7443/7444 Manual Reset Timing 210ms
Pericom Technology
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IC 7448 IC 7446 IC 7446 pin diagram 7448 ic diagram pin configuration of ic 7448 pin configuration ic 7448 PT7M7443-52 PT7M7449 PT7M7447/7448/7451/7452 PT7M7443 PT0289
Abstract: Thermal Characteristics . . . . . . . . . . . 11 6. Pin Assignments . . . . . . . . . . . . . . . . . . . , . Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design , Reservation Reservation Station Station Station Station Figure 1. MPC7457 Block Diagram 512-Kbyte Unified , . 10.Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. Figure 2 shows the undershoot and overshoot voltage on the MPC7457. MPC7457 RISC Microprocessor Freescale Semiconductor
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MC 7447

Abstract: GPR practical circuit . . . . 10 6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7. Pinout , except that it does not support the L3 cache interface. Figure 1 shows a block diagram of the MPC7457 , Station Station Figure 1. MPC7457 Block Diagram Vector Permute Unit Vector Integer Unit 2 , . 10. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. Figure 2 shows the undershoot and overshoot voltage on the MPC7457. OVDD/GVDD + 20% OVDD/GVDD + 5% OVDD
Freescale Semiconductor
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MC 7447 GPR practical circuit CI 7447 draw pin configuration of ic 7447

ME1084

Abstract: 1084 GE Figure 2 Error Amp. Bandgap Reference ADJ/GND Figure 1 1 Analog Microelectronics, Inc. 5A Low Dropout Positive Voltage Regulator AME1084 n Pin Configuration AME 1084 AME1084 , regulation typically 0.05% Adjust pin (ADJ) current less than 90µA Overcurrent protection Thermal , pin current Test Conditions Symbol VD Typ. Max. 1.262 TJ =25OC IO = 10mA Over , . 3.333 Units Adjust pin current change IADJ 2. 1084DXXX Parameter Output voltage (fixed
Analog Microelectronics
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ME1084 1084 GE ccs 9620 1084D GE 1884 1084DCCS AME1084V

CI 7447

Abstract: IC 7447 resistive 50- load (see Figure 4). Input and output timings are measured at the pin; time-of-flight delays , Thermal Characteristics . . . . . . . . . . . 10 6. Pin Assignments . . . . . . . . . . . . . . . . . . . , interface. Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design , Management · Performance Monitor Additional Features Features Figure 1. MPC7457 Block Diagram , overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. Figure 2 shows the
Freescale Semiconductor
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IC 7447 counter PowerPC 950 TT 2076 MPC7400 PPC7457 ic counter 7447 512-K

158 RSISTOR

Abstract: pin configuration of IC 1619 cp Reference ADJ/GND Figure 2 Figure 1 1 AME, Inc. 1.5A Low Dropout Positive Voltage Regulator AME1086 n Pin Configuration To-263 Front View To-263-2 Front View AME 1086 AME , typically 0.05% Adjust pin (ADJ) current less than 90µA Overcurrent protection Thermal protection , to the output pin of the AME1086. When so connected, RP is not multiplied by the divider ratio. For fixed output versions, the top of R1 is internally connected to the output and ground pin can be
Analog Microelectronics
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158 RSISTOR pin configuration of IC 1619 cp AME1086ACBT AME1086ACCS AME1086ACDS AME1086ACDT 1015-DS1086-C

IC 7448

Abstract: 7448 | Pin Configuration Pin Description 7443/44 1 7445/46 2 Pin 7447/48 2 7449/50 2 7451/52 2 Name GND , Small 5 and 6-Pin SOT23 Packages Ordering Information Part Number PT7M7443xTAE PT7M7444xTAE , brownout conditions (see Figure 8 Typical Operating Circuit). /RESET changes from high to low whenever the , for VDD inputs 1V. Figure 1 Typical Operating Circuit · Manual Reset Input Options Unlike , system.) Figure 2 PT7M7443/7444 Manual Reset Timing 210ms MR1 6.72s MR2 RESET Figure 3
Pericom Technology
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7448 IC 7446 diagram circuit marking CODE GV* SOT23-5 7448 IC application sot23-6 marking code gc MARKING HF SOT23-5 PT7M7445/7446 PT7M7447/7448 PT7M7451/7452

pin configuration of ic 7448

Abstract: IC+7448+truth+table | | Pin Configuration Pin Description 7443/44 1 7445/46 2 Pin 7447/48 2 7449/50 2 , '¢ Active-Low Outputs â'¢ 140ms(min) Reset Timeout Period â'¢ Small 5 and 6-Pin SOT23 Packages , power-up, power-down and brownout conditions (see Figure 8 Typical Operating Circuit). /RESET changes , guaranteed to be in the proper output logic state for VDD inputs ≥ 1V. Figure 1 Typical Operating Circuit , on/off button and the channel-select button for 6.72s to reset the system.) Figure 2 PT7M7443
Pericom Technology
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IC+7448+truth+table data sheet IC 7448 marking HX 6pin
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