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ISL1561IRZ Intersil Corporation Fixed Gain Dual Port Class-G Differential xDSL Line Driver; QFN24; Temp Range: -40° to 85°C visit Intersil Buy
ISL1591IRTZ Intersil Corporation Fixed Gain, Dual Port, VDSL2 Line Driver; TQFN24; Temp Range: -40° to 85°C visit Intersil Buy
EL1881CS-T13 Intersil Corporation SYNC SEPARATOR IC, PDSO8, SO-8 visit Intersil
EL1883ISZ-T7 Intersil Corporation Sync Separator with Horizontal Output; SOIC8; Temp Range: -40° to 85°C visit Intersil Buy
EL4511CUZ Intersil Corporation Super Sync Separator; QSOP24; Temp Range: 0° to 70° visit Intersil Buy
HC5503CB96 Intersil Corporation TELECOM-SLIC, PDSO24, PLASTIC, MS-013AD, SOIC-24 visit Intersil

IC 74240

Catalog Datasheet MFG & Type PDF Document Tags

ic 74138

Abstract: IC 7402, 7404, 7408, 7432, 7400 LEAPER-1 HANDY DIGITAL IC TESTER Supported Devices Features EMC Standards 1.Easy-operating Tester, particularly ( per 89/336/EEC ) be designed for the Digital IC / 44 Serial. 3.Small, portable, light and powersaving, usable with batteries. 4.Average search time: 0.8 second 5.Display: 16 characters in 1 line LCD 6.Test Pins: 14 to 24 pins Standard Accessories Main unit Operation manual , 74191 74192 74193 74194 74195 74196 74197 74198 74199 74230 74231 74240 74241 74242 74243 74244 74245
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ic 74138 IC 7402, 7404, 7408, 7432, 7400 ic 74139 IC 74147 IC 74373 74148 IC EN50081-1 EN50082-1 EN55022 IEC801-2 EN60555-2 IEC801-3

ssc 6200

Abstract: 74590 . T Y P IC A L ifi% 74210 1 1 1 74215 1 1 74220 1.1 1 74225 1 1 74230 1 1 1 74235 2 1 74240 2 1 T Y P IC A L IN T E R ­ M A X V A L U E IN O , PICOâ'™S Pulse Transformers SIZE 1 L E A K A G E IN D . TUANS P IC O W IN D IN G R E S IS T A N C E T Y P IC A L IN T E R ­ E.T. V A L U E IN Mil T Y P IC A L M A X V A L U E , . Lai T Y P IC A L LL LL nH IN 1 - N 2 ) (N 1 -N 3 ) R (N D R(iei H |N3> C1
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ssc 6200 74590 IC 74090 ic 74210

IC 74115

Abstract: CI LM 4800 C T R IC STR EN G TH :. All Units Tested at 500 V RMS · IN SU LA TIO N R ESIST A N C E:. , 8.0 15.0 Cí C2 æ R(N3) fN1-N2) H1-N3, PfíMURY P R IC E (1-91 18.30 18.30 18.30 18.30 18.30 , TYPICAL N IER . ET V A LU EN vH MAX VALU EN OHMS KM3MBC4P RAHNO P IC O TURNS VALUE f i p F VOLTTYPICAL , ) M1-N3 rrwmrrr 74210 74215 74220 74225 74230 74235 74240 74245 74250 74255 74260 74265 74270 74275 74280 , 18 18 18 16 32 48 65 80 16 32 48 65 80 19 38 57 76 95 19 38 57 76 95 19 38 57 76 95 P R IC E (1-9
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IC 74115 CI LM 4800 74555 IC IC 74245 ic 1830 74220 IL-PRF21038 IL-STD-202

IC TTL 7432

Abstract: IC 7402, 7404, 7408, 7432, 7400 : +44 (0)1226 207620 www.abielectronics.co.uk ChipMaster Compact Professional IC List 2.08 Digital IC Tester Software version 2.08 Series 54/74 TTL ICs 7400 7401 7402 7403 7404 7405 7406 7407 , 74237 74238 74240 74241 74242 74243 74244 74245 74246 74247 74248 74249 74251 74253 , Compact Professional IC List 2.08 Analogue IC Tester Software version 2.08 Operational Amplifiers
ABI Electronics
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IC TTL 7432 ttl 74118 74189 memory 74189 ttl memory TTL 74289 RC4458 TLC272 TLC274 TLC277 TLC279 TLC2872 TLE2061
Abstract: DLP-RF2PROTO. The communications interface between the FT232BM USB IC and the DLP-RF2 transceiver is , 16 D5 8 7 6 5 4 3 2 1 D D4 D3 D2 D1 LED x 7 U3 74240 1 2 3 4 5 6 7 DLP Design
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RS232C PQ1L303M2SP

3 volt regulator

Abstract: DB9 drawing DLP-RF2PROTO. The communications interface between the FT232BM USB IC and the DLP-RF2 transceiver is , .01uF 2 5 3 1 2 LED POWER JP9 1 0.1uF 12 14 16 18 9 7 5 3 U3 74240
DLP Design
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3 volt regulator DB9 drawing DB9 MALE drawing power wizard 1.0 C2C15 3.7 volt convertor F/10V

DB9 drawing

Abstract: 7424 .) The communications interface between the FT232BM USB IC and the DLP-RF2 transceiver is bi-direction 3 , JP9 1 0.1uF 12 14 16 18 9 7 5 3 U3 74240 BDM CN2 9 10 11 12 13 14
DLP Design
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7424 sw 901 usb LPT converter X 1018 4 volt regulator

pin DIAGRAM OF IC 74240

Abstract: pin diagram of ic 9430 micro-controller. This IC can share the LCD pin and I/O pin (From 128-dot of LCD driver + 16 Bit I/O Port . 64 , speech (20 seconds at 3K bytes per second), graphic, text etc. This IC is applicable to the small/medium , stable frequency for Slow Mode, and provide IC LCD MO_FXTAL=0R,C oscillation for Fast Clock 1Crystal , (MO_PORE=1) could enable IC build-in Power-on reset circuit. System reset signal Besides, MO_WDTE can , 1575.50 1435.40 1296.80 1158.20 1019.60 881.00 742.40 Y Coordinate -849.55 -989.80 -1130.05
Jess Technology
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HE83715 pin DIAGRAM OF IC 74240 pin diagram of ic 9430 HE80000 768KH HE82/83/89 HE83/89

IC AND GATE 7408 specification sheet

Abstract: 74LS96 file. For each C N F , a Ffierarchy Inte rconnect File (.HIF) and a G raph ic Design File (.GDF) are , logic schem atic in the M A X + P L U S Graph ic Editor. Altera Corporation Page 320 Data Sheet , |d create an ED IF file with V iew log ic softw are, the fo llow ing a pplicatio ns are required: LI , IF netlist writer) version 4.0 o r higher Viewloaic T ab le 3 lists the V ie w lo g ic B U IL T , 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 74258 74259 Mentor Graphics 74LS114A 74LS133
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IC AND GATE 7408 specification sheet 74LS96 74LS183 SN 74168 7486 XOR GATE IC 74LS192

sn 74373

Abstract: SN 74114 graphic and text designs S chem atic captu re with Valid Logic's V alidG KD or V iew log ic's V iew d ra w , relational operations Full A lte ra /V a lid Logic and A l te r a /V ie w lo g ic cro ss-com patibility via , V ie w log ic V iew sim chip- and board-level sim ulators or with Logic A u to m a tio n 's S m artM , are entered either with V a lid G E D by Valid Logic or with V ie w d raw by V iew log ic (see Figure , schem atics are converted into F D IF 2 0 0 netlist files with V ie w lo g ic 's E D IF N E T O netlist
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sn 74373 SN 74114 logic diagram of ic 74112 IC 7486 xor 7486 xor IC sn 74377 QIC-24

LM 74138

Abstract: 74373 latch ic intei 82303 LOCAL I/O SUPPORT CHIP Supports System Board Setup B |ntegrated peripheral Bus Address Latches a Low Power CHMOS Technology m 100.pin p,astic Quad F,at Package High Integration-The 82304, 82303and 82077 Floppy Disk Controller Replace 50 IC's in IBM Design Integrated Parallel Port , form factor constraints by replacing 50 IC devices in an equivalent IBM system. The 82303 integrates , AUT0FC STROBE# AUT0FC# SLCTIN SLCTIN# abcpdO - -O - O ppdren# ^ 3 E N E X P P ^>- 74240
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LM 74138 74373 latch ic ic 74373 D latch function of latch ic 74373 truth table for ic 74138 Latches 74373 M60STR P103RD P103W P101RD CDSU06 CDSU18

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 MAX+PLUSIITTL Macrofunction 74190 74191 74192 74193 74194 74195 74196 74197 74240 74241 74244 74251 74253 74257 , Q u arter-in ch c a rtrid g e tape (Q IC-24, 9 tra ck ) c o n ta in in g all P L S - W S / H P
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74191, 74192, 74193 circuit diagram Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 HP400 IC-24

LEAPER-3

Abstract: 74189 environment of development. Additional, the Company has been qualified by major IC manufacturer such as ATMEL , the"Cartridge modules" you can have all sorts of special IC programming systems. The SU-2000 offers two modes , (2)IC type select (3)blank check (4)verify & check sum (5)program 2. PC based mode: transmit data , -2 EN60555-3 EN50082-1 IEC801-2 IEC801-3 IEC801-4 LEAP LEAPER-2 HANDY LINEAR IC TESTER 10 , Features *Easy-operating Tester, particularly be designed for the Linear IC *Small, portable, light
Leap Electronic
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LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622 PIC16C71/710

IC 3-8 decoder 74138 pin diagram

Abstract: f9444 configuration (2114-type 1K x 4). The bus is buffered by a 74240 inverting 3-state buffer. Buffering is optional , scheme, the I/O bus is buffered (74240); this is op tional. A one-shot (9602) provides a processor cycle , (9602) provides a pulse fo r a TTY reader delay. Dynamic Memory Control Since dynam ic memory is more d , itry to drive dynam ic mem ories (see Figure 9). There are several approaches to dynam ic memory control: Using an LSI special-purpose dynam ic memory co n tro l ler (e.g. F9446), which is by far the sim
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IC 3-8 decoder 74138 pin diagram f9444 74874 Fairchild 9445 74164 counter pin diagram of ic 74164 F9445 F9444 F9447 F9448 F9449 F9470

f9454

Abstract: F9445 Fairchild's Isoplanar Integrated Inje ctio n'L o g ic (l3La ) technology. This bipolar technology and a , rdering Inform ation Page 1 2 2 4 5 15 19 30 31 36 Pin Functions C LK _ F 9445 HR 16-B IT M IC R O P , static RAM con fig ura tio n (2114-type 1K x 4). The bus is buffered by a 74240 inverting 3-state buffer , . In th is scheme, the I/O bus is buffered (74240); this is op tional. A one-shot (9602) provides a , one-shot (9602) provides a pulse fo r a TTY reader delay. Dynamic Memory Control Since dynam ic memory is
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f9454 74l93 9347S F9454 F9445-24 F9445-20 F9445-16

IC 3-8 decoder 74138 pin diagram

Abstract: F9444 ' in+Arrnnl ^aku! r* AAn If iiAn rlrt^ uciOi c aiiuuici ii no i i up i sci vii/c i^ai i oiai i. 11 u ic oc i
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MSI IC 74138 decoder power control F9444 F9445 self-test 74138 FAIRCHILD 74ls240 bus transfer switch F9445-16DM M38510

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC r ty p ic a l p ro p a g a tio n d e la y s a re g e n e ra lly th e slo w est tim e s fo r a n y in , ty p ic a l p ro p a g a tio n d e la y s a re g e n e ra lly th e slo w est tim e s fo r a n y in p , 0 M H z , has 2 2 in p u ts a n d 4 0 o u tp u ts of w h ic h 10 are of 4 m A d riv e s tre n g th a , 74194 74198 74240 74244 74248 74257 74261 74274 74279 74284 74293 74322 74351 74355 74366 74374 74378 , (L o a d U n it) Is th e In p u t c a p a c ita n c e of o n e b a s ic gate. T y p ic a l va lu e s
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74LS82 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 TC140G SC12D4 SC18D4 SC27D4 SC37D4 SC44D4

741S373

Abstract: 74LSOO FAIRCHILD A S chlum berger C om pany F9445 16-Bit Bipolar Microprocessor M ic ro p ro c e s s o r P ro d u cts Description The F9445 is a 16-bit m ic ro p ro c e s s o r im p le m e n te d using F a irc h ild 's Is o p la n a r Integra ted In je c tio n L o g ic (l3L" ) te c h n o lo g y . T , ic ro c o m p u te r system s. The s u p p o rt c irc u its in c lu d e th e F9446 D ynam ic M e m o , F9445 Fig. 1 F9445 Functional Diagram A rchitecture The F9445 m ic ro p ro c e s s o r c o m p ris
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741S373 74LSOO F9445-based F9444 power control ltiu F9445-16DMQB IB13C 1B11C 1B10C

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74195 40 74196 42 74197 41 74198 92 74199 70 74225 450 74226 116 74240 24 74241 24 74242 26 74243 26 , workstation workstation â'¢ Product idea diagram including IC Logic diagram layout Breadboard , '¢ Processing â'¢ Wafer test Siemens â'¢ Mounting IC Fabrication â'¢ Test â'¢ Delivery of prototypes
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74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder

74373 cmos dual s-r latch

Abstract: 74373 verilog technologies. Here are a few notes that w ill fam iliarize you w ith o u r new library fam ily. SEC A S IC has , has 80 A and the 5 V process has 120 A . Using these two processes, SEC AS IC offers 6 libraries, 3 , ill d eliver the best perform ance and the desired I/O interface. SEC A S IC 0.5^,171 Processes , er dissipation ( P DC) and d ynam ic pow er d issipation (P AC). P TOTAL = P d C + PAC , sink. The dynam ic pow er dissipation is caused by three com ponents: input buffers (P a c j n p u t ).
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74373 cmos dual s-r latch 74373 verilog A022A 74152 PIN DIAGRAM application of ic 74153 T749 KGL80 VSS30 VSS30I VSS30P VSS50
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