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I/O68

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I , I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 , /O109 I/O113 NC I/O126 I/O127 I/O128 P I/O68 I/O67 NC I/O74 I/O79 I , - 3.3V ISR - 5V tolerant · Up to 192 I/Os - Plus 5 dedicated inputs including 4 clock inputs · Cypress Semiconductor
Original
CY37256V 256-M 160-L 208-L 256-L CY37256

CY37256P160-125UMB

Abstract: CY37256P160-83UMB /O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /TDO I , /O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , changes · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High speed - fMAX = , Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low
Cypress Semiconductor
Original
CY37256P160-125UMB CY37256P160-83UMB CY37256P160-125AI CY37256-125 CY37128/37128V CY37192/37192V CY37384/37384V CY37512/37512V CY7C375 I/O0-I/O11

ULTRA37000

Abstract: /O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 , I/O78 I/O79 VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I , /O56 I/O53 I/O70 I/O68 I/O65 GND I/O61 I/O58 I/O55 I/O69 I/O67 I/O64 , Features · 3.3V or 5.0V I/O operation · Available in 160-pin TQFP, CQFP, and PGA packages · 128 macrocells in eight logic blocks · 128 I/O pins Functional Description · Five dedicated inputs
Cypress Semiconductor
Original
ULTRA37000 ULTRA37000TM 128-M FLASH370 22V10

U208

Abstract: TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 , I/O105 I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I , I/O52 I/O55 I0 I/O61 I/O64 I/O65 I/O68 I/O71 I/O88 I/O91 I/O94 I/O95 I/O74 I/O77 I/O81 2 GND NC I , I/O68 I/O67 I/O66 GND GND I/O193 I/O195 I/O196 I/O197 GND GND GND GND , standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - Plus 5 dedicated inputs including 4
Cypress Semiconductor
Original
U208 CY37512V 512-M 352-L 400-L CY37512 CY37256/37256V

tea 1601 t

Abstract: Programmable pull-up or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - , on all major programmers including Data I/O, BP Microsystems, Advin, and System General , 3.3 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static Power (mA) JTAG Compliant PCI Compliant 5 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz , Commercial, C C C -5 C C C C C C C C -55 -6 -65 -7 C, I C, I C, I C, I C, I C, I C, I C C -10 C, I C, I C, I
Lattice Semiconductor
Original
tea 1601 t 182MH M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64

208-Lead

Abstract: CY37512 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , I/O67 VCC GND GND GND GND GND I/O68 I/O69 I/O70 GND GND GND , changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - plus 5 , rate control on individual I/Os Low power option on individual logic block basis User-Programmable
Cypress Semiconductor
Original
208-Lead ultraISR CABLE CY37512VP208-66NI CA95134 I/O12-I/O23 I/O24-I/O35 I/O36-I/O47 I/O48-I 2VP208-66NI

ultraISR CABLE

Abstract: CY37256 /O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCCO GND VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 , I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold
Cypress Semiconductor
Original
I/O48-I/O59 I/O60-I/O71 I/O72-I/O83 I/O84-I/O95 256-P 38-00474-E
Abstract: VCCIO Document #: 38-03029 Rev. *A VCCINT I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I , /O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND , I/O44 I/O41 B I/O80 I/O79 I/O77 I/O70 I/O68 I/O65 GND I/O61 I/O58 , · 128 I/O pins · Five dedicated inputs including 4 clock pins · In-System Reprogrammable (ISRTM) Flash technology - JTAG Interface · Bus Hold capabilities on all I/Os and dedicated inputs · No hidden Cypress Semiconductor
Original

tea 1601 t

Abstract: tea 1601 or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - Individual , Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General , 3.3 V Devices Feature Macrocells User I/O options M4A3-322 M4A3-642 M4A3-962 M4A3 , -962 M4A5-1282 M4A5-1921 M4A5-2562 Macrocells 32 64 96 128 192 256 User I/O , -5 M4A3-323 M4A5-323 -55 -6 -65 -10 -12 C, I C -7 C, I I M4A3
Lattice Semiconductor
Original
tea 1601 O2-A2 160 e7 led matrix circuits ISPMACH ispMACH 4A Family M4A3-192/96 M4A3-256/128 M4A3-256/1601 M4A3-256/1921 M4A3-384/160 M4A3-384/192
Abstract: or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - Individual , Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# ISPM4A Amendment/0 Rev: I Issue Date: May 2001 Table 1. ispMACH 4A Device Features 3.3 , -384 M4A3-512 Macrocells 32 64 96 128 192 256 384 512 User I/O options 32 , User I/O options 32 32 48 64 96 128 tPD (ns) 5.0 5.5 5.5 5.5 6.0 -
Original
M4A3-256/160 M4A3-256/192 M4A3-512/160 M4A3-512/192 M4A3-512/256 M4A5-32/32

ULTRA37000

Abstract: 160-Lead I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND I , I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 GND , VCC GND VCC GND I/O66 I2 I/O60 I/O56 I/O53 I/O70 I/O68 I/O65 GND , Features · 3.3V or 5.0V I/O operation · Available in 160-pin TQFP, CQFP, and PGA packages · 128 macrocells in eight logic blocks · 128 I/O pins Functional Description · Five dedicated inputs
Cypress Semiconductor
Original
160-Lead

37256p

Abstract: CY37256-125 GND I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCCO GND VCC I/O64 I/O65 I/O66 I/O67 I/O68 I , I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 I2 VCC0 GND VCC , /O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I , don't cause pinout changes - Design changes don't cause timing changes · Up to 192 I/Os - Plus 5 , slew rate control on individual I/Os Low-power option on individual logic block basis 5V and 3.3V I/O
Cypress Semiconductor
Original
37256p IEEE 1149.1 JTAG I/O180-I/O191 I/O168-I/O179 I/O156-I/O167 I/O144-I/O155 I/O132-I/O143 I/O120-I/O131

CY37512

Abstract: CY37512V I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 , /O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I , I/O67 VCC GND GND GND GND GND I/O68 I/O69 I/O70 GND GND GND , changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - plus 5 , rate control on individual I/Os Low power option on individual logic block basis User-Programmable
Cypress Semiconductor
Original
208-P CY37512VP256-66BGI BG256 CY37512VP352-66BGI BG352 352-P

CY37256

Abstract: CY37256V /O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I , I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 , 3.3V ISR - 5V tolerant · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High , Programmable slew rate control on individual I/Os Low power option on individual logic block basis
Cypress Semiconductor
Original
O116 38-00606-C 160-P 51-85069-B

O2-A2

Abstract: VCCIO11 or Bus-FriendlyTM inputs and I/Os - Hot-socketing - Programmable security bit - Individual , 32 64 96 128 192 256 384 512 User I/O options 32 32/64 48 64 , -128 M4A5-192 M4A5-256 Macrocells 32 64 96 128 192 256 User I/O options 32 , Speed Grade Device M4A3-32 M4A5-32 -5 -55 -6 -65 -10 -12 C, I C -7 C, I I M4A3-64/32 M4A5-64/32 C C, I C, I I M4A3-64/64 C C, I C, I I
Lattice Semiconductor
Original
VCCIO11 Lattice Mach OX2 ispMACH M4A3 M4A5-192 application note PAL 007 O64i M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 VNI48 M4A3-256/128-7YC-10YI

O158

Abstract: O2-A2 voltage system designs - Programmable pull-up or Bus-FriendlyTM inputs and I/Os - Hot-socketing - , 64 96 128 192 256 384 512 User I/O options 32 32/64 48 64 96 , -128 M4A5-192 M4A5-256 Macrocells 32 64 96 128 192 256 User I/O options 32 , Speed Grade Device -5 M4A3-32 M4A5-32 -55 -6 -65 -10 -12 C, I C -7 C, I I M4A3-64/32 M4A5-64/32 C C, I C, I I M4A3-64/64 C C, I C, I I
Lattice Semiconductor
Original
O158 1M4A3 12864a o248 512256 VNC48

CY37256

Abstract: CY37256V /O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I , I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 , - 5V tolerant · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High speed , Programmable slew rate control on individual I/Os Low power option on individual logic block basis
Cypress Semiconductor
Original
Abstract: /O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 /SDO I/O77 I/O78 I/O79 VCCIO , /O80 GND Document #: 38-03029 Rev. * I/O78 I/O79 VCC I/O64 I/O65 I/O66 I/O67 I/O68 I , /O56 I/O53 I/O70 I/O68 I/O65 GND I/O61 I/O58 I/O55 I/O69 I/O67 I/O64 , · · · 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock , all I/Os and dedicated inputs · No hidden delays · High speed - fMAX = 125 MHz The CY7C375i is Cypress Semiconductor
Original

CERAMIC QUAD FLATPACK CQFP 14 pin

Abstract: CERAMIC QUAD FLATPACK CQFP /O78 I/O79 VCCIO VCCINT I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 , VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76 , /O70 I/O68 I/O65 GND I/O61 I/O58 I/O55 I/O69 I/O67 I/O64 I/O63 I/O62 , blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology - JTAG Interface · Bus Hold capabilities on all I/Os and dedicated inputs · No hidden delays
Cypress Semiconductor
Original
CERAMIC QUAD FLATPACK CQFP 14 pin CERAMIC QUAD FLATPACK CQFP CERAMIC PIN GRID ARRAY CPGA

M4A3-256

Abstract: I/Os - Hot-socketing - Programmable security bit - Individual output slew rate control Advanced , Macrocells User I/O options tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static Power (mA) JTAG Compliant PCI Compliant 5 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static , -512 Note: 1. C = Commercial, I = Industrial C C C -5 C C C C C C C C -55 -6 -65 -7 C, I C, I C, I C, I C, I C, I C, I C C -10 C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I -12 I I I I I I I I I C, I
Lattice Semiconductor
Original
M4A3-256 M4A3256/128-7YC-10YI

pasic 3

Abstract: QL3004-1PL68C I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I , /O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I , I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 , /O109 I/O113 NC I/O126 I/O127 I/O128 P I/O68 I/O67 NC I/O74 I/O79 I
QuickLogic
Original
pasic 3 QL3004-1PL68C QL3004 QL3012-1PF144C QL3004E Military Plastic pASIC 3 Family
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