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I/O190 Datasheet

Part Manufacturer Description PDF Type
IO1900-NF12 Laird Technologies RF Antennas, RF/IF and RFID, ANT 900MHZ SPHERE 3DBI M FEMALE Original
IO1900-SM36 Laird Technologies RF Antennas, RF/IF and RFID, ANT 900MHZ SPHERE 3DBI SMA MALE Original

I/O190

Catalog Datasheet MFG & Type PDF Document Tags

MQFPF256

Abstract: O349 (Global Clock) I/O262, FCLK4 (Fast Clock) 84 I/O191, D8 (Data) I/O261 85 I/O190 I , Clock) 131 I/O83 I/O191, D8 (Data) 132 VSS I/O190 133 I/O72, FCLK2 (Fast Clock , 1 1.9 PIN ASSIGNMENT Function Pin MQFP-F160 MQFP-F256 1 VDD I/O384, GCLK8 (Global Clock), A15 (Address) 2 I/O384, GCLK8 (Global Clock), A15 (Address) I/O383, A14 (Address) 3 I/O383, A14 (Address) I/O382 4 I/O382 I/O381 5 I/O381 I/O378 6
European SPace COmponents Coordination
Original
MQFPF256 O349 AT40KEL040

U208

Abstract: 20 A GND I/O21 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 , VCC GND GND NC VCC VCC I/O150 I/O151 NC I/O153 I/O190 I/O191 I/O168 I/O152 I/O187 I/O188 I/O189 NC , I/O167 NC I/O154 I/O155 I/O187 I/O190 U I/O83 NC GND I/O111 I/O112 I , standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - Plus 5 dedicated inputs including 4 , I/Os Low-power option on individual logic block basis User-Programmable Bus Hold capabilities on all
Cypress Semiconductor
Original
U208 CY37512V 512-M 208-L 256-L 352-L 400-L
Abstract: A GND I/O21 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I , /O163 I/O164 D I/O32 I/O31 I/O30 NC I/O17 I/O13 I/O8 I/O3 I/O190 I , - 3.3V ISR - 5V tolerant · Up to 192 I/Os - Plus 5 dedicated inputs including 4 clock inputs · , Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis User-Programmable Bus-Hold capabilities on all I/Os Simple Cypress Semiconductor
Original
CY37256V 256-M 160-L CY37256 CY37128/37128V CY37192/37192V

CY37512

Abstract: CY37512V I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A , /O73 I/O110 I/O153 I/O190 I/O191 I/O168 Y I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I , changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - plus 5 , rate control on individual I/Os Low power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 208-pin PQFP
Cypress Semiconductor
Original
CY37512 CY37256/37256V CY37384/37384V CA95134 I/O0-I/O11 I/O12-I/O23

208-Lead

Abstract: CY37512 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A , /O73 I/O110 I/O153 I/O190 I/O191 I/O168 Y I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I , changes · IEEE standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 264 I/Os - plus 5 , rate control on individual I/Os Low power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 208-pin PQFP
Cypress Semiconductor
Original
208-Lead ultraISR CABLE CY37512VP208-66NI I/O24-I/O35 I/O36-I/O47 I/O48-I 2VP208-66NI 208-P CY37512VP256-66BGI

qml-38535

Abstract: AT40KEL040KZ1MQ /O192_GCK4 I/O191_D8 I/O190 I/O189 I/O184_D9 I/O183_D10 I/O180 I/O179 GND I/O168 I/O167 I/O166_D11 I/O165_D12 , /O193_D7 RESETN CON I/O192_GCK4 I/O191_D8 I/O190 I/O189 I/O186 GND Vcc I/O184_D9 I/O183_D10 I/O181 I/O180 I , characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full , table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the , A REVISION LEVEL 5962-03250 SHEET 5 b. Subgroups 5 and 6 of table I of method 5005 of
DEPARTMENT OF DEFENSE
Original
AT40KEL040KZ1MQ qml-38535 5962-E265-04 MIL-PRF-38535 MIL-HDBK-103 QML-38535 5962-0325001QXC 5962-0325001VXC

QML-38535

Abstract: at40kfl040kz1sv 113 114 115 116 117 118 119 120 CON GND I/O192_GCK4 I/O191_D8 I/O190 I/O189 I/O184_D9 , I/O192_GCK4 I/O191_D8 I/O190 I/O189 I/O186 GND Vcc I/O184_D9 I/O183_D10 I/O181 I/O180 I , electrical performance characteristics and postirradiation parameter limits are as specified in table I and , subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein , 5962-03250 A REVISION LEVEL B SHEET 5 b. Subgroups 5 and 6 of table I of method 5005 of
DEPARTMENT OF DEFENSE
Original
5962-0325002QXC at40kfl040kz1sv o26f AT40KFL040 5962-E504-06 F7400 AT40KEL040KW1MQ AT40KEL040KW1SV 5962-0325001QYC 5962-0325001VYC

CY37512P208-100UMB

Abstract: CY37512 /O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 , /O175 VCCO I/O174 I/O173 I/O172 VCCO I/O171 I/O170 I/O169 I/O153 I/O190 I/O191 I/O168 I/O152 I/O187 I , changes don't cause pinout changes - Design changes don't cause timing changes · Up to 264 I/Os - Plus 5 , rate control on individual I/Os Low-power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant Available in
Cypress Semiconductor
Original
CY37512P208-100UMB CY37512P208-83UMB CY37512-125 37512p208 NT208 CY37512P208-100UM 37256/37256V BG256 BG352 51-85069-B

339-04

Abstract: QML-38535 CON GND I/O192_GCK4 I/O191_D8 I/O190 I/O189 I/O184_D9 I/O183_D10 I/O180 I/O179 GND I/O168 , Vcc I/O203 I/O196 I/O195 I/O194_GCK5 I/O193_D7 RESETN CON I/O192_GCK4 I/O191_D8 I/O190 I , postirradiation parameter limits are as specified in table I and shall apply over the full case operating , specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The , 5 b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. For device
DEPARTMENT OF DEFENSE
Original
339-04 smd marking 242 5962-E AT40KEL040KZ1SV

CY37512

Abstract: CY37512V NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC , /O190 I/O191 I/O168 Y I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I/O188 I/O189 AA AB , Design changes don't cause pinout changes - Design changes don't cause timing changes · Up to 264 I/Os , Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI
Cypress Semiconductor
Original
AE O47 I/O48-I/O59 I/O60-I/O71 FLASH370

CY37512P256-125BGI

Abstract: O249 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC , /O190 I/O191 I/O168 Y I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I/O188 I/O189 AA AB , changes don't cause pinout changes - Design changes don't cause timing changes · Up to 264 I/Os - , Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI
Cypress Semiconductor
Original
CY37512P256-125BGI O249 O-220 CY37512P208-125NI io1B

57B8

Abstract: xc4000 pin Independent of Logic Cells 84 - 384 PCI Compliant I/Os ­ 3V/5V Capability ­ Programmable Output Drive ­ , 576 1,024 2,304 RAM Bits 2,048 4,608 8,192 18,432 I/O (max) 128 192 , data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts , programmable I/O. Devices range in size from 5,000 to 50,000 usable gates in the initial family, and 256 to 2 , Array Surrounded by I/O (AT40K20) = I/O Pad = AT40K Cell = Repeater Row = Repeater Column 3
Atmel
Original
57B8 xc4000 pin o4413 dsp o212 PQ304 atmel 144 XC4000 XC5200 0896B

CY37384

Abstract: CY37384V /O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 , tolerant · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High speed - fMAX = 83 , control on individual I/Os Low power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 208-pin PQFP and 256-lead BGA , tolerant nature of the I/Os, the I/Os are not clamped to VCC. Clock/ Input Input Logic Block Diagram
Cypress Semiconductor
Original
CY37384V CY37384 384-M CY37512/37512V I/O72-I/O83 I/O84-I/O95

ultraISR CABLE

Abstract: /O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 , standard 3.3V operation - 3.3V ISR - 5V tolerant · Up to 192 I/Os - Plus 5 dedicated inputs including 4 , individual I/Os Low-power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 208-Lead PQFP and 256-Lead BGA packages , edge rate mode, outputs switch at 1V/ns max. There is a nominal delay for I/Os using the slow edge rate
Cypress Semiconductor
Original
37384VP256-83BGC CY37384VP208-66NC CY37384VP256-66BGC CY37384VP208-66NI CY37384VP256-66BGI

cpld internal

Abstract: CY37384 /O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 , - 5V tolerant · Up to 192 I/Os - plus 5 dedicated inputs including 4 clock inputs · High speed , Programmable slew rate control on individual I/Os Low power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 208 , Note: 1. Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to VCC. Clock/ Input
Cypress Semiconductor
Original
cpld internal 256-P

5962-9951902QYA

Abstract: CY37128P100-125AXC to 512 macrocells - 32 to 264 I/O pins - Five dedicated inputs including four clock pins · Simple timing model - No fanout delays - No expander delays - No dedicated vs. I/O pin delays - , capabilities on all I/Os · Intelligent product term allocator provides: - 0 to 16 product terms to any , user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. VCCO connections provide the capability
Cypress Semiconductor
Original
CY37032P44-125JXC CY37128P100-125AXC 5962-9951902QYA CY37032V CY37064 CY37064V CY37128 37000TM 22V10 CY37032P44-200AXC CY37032P44-200JXC CY37032P44-154AXI CY37032P44-154JXI

CY37064P44-154YMB

Abstract: CY37512P208-100UMB High density - 32 to 512 macrocells - 32 to 264 I/O pins - 5 dedicated inputs including 4 clock pins · Simple timing model - No fanout delays - No expander delays - No dedicated vs. I/O pin , ] Programmable Bus-Hold capabilities on all I/Os Intelligent product term allocator provides: - 0 to 16 , user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. V CCO connections provide the capability
Cypress Semiconductor
Original
CY37064P44-154YMB CY37256P160-125UMB CY37032VP44-100AI CY37032 CY37128V CY37192 N208/NT208

CY37032VP44-100AI

Abstract: CY37032 512 macrocells - 32 to 264 I/O pins - 5 dedicated inputs including 4 clock pins · Simple timing model - No fanout delays - No expander delays - No dedicated vs. I/O pin delays - No additional , on all I/Os Intelligent product term allocator provides: - 0 to 16 product terms to any macrocell , timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O
Cypress Semiconductor
Original
100-P 51-85048-B 100-B BB100 160-P

CY37128P100-125AXC

Abstract: CY37032VP44-100AI I/O pins - Five dedicated inputs including four clock pins · Simple timing model - No fanout delays - No expander delays - No dedicated vs. I/O pin delays - No additional delay through PIM - No , versions · PCI-compatible[1] · Programmable bus-hold capabilities on all I/Os · Intelligent product term , )-free packages available Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not , requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os. Ultra37000
Cypress Semiconductor
Original
CY37032P44-125AXC CY37064P44-200AXC CY37064P44-200JXC CY37064P100-200AXC CY37064P44-154AXI CY37064P44-154JXI

CY37512P208-100UMB

Abstract: CY37512P208-100UM 512 macrocells - 32 to 264 I/O pins - 5 Dedicated Inputs including 4 clock pins · High speed - 222 , expander delays - No dedicated vs. I/O pin delays - No additional delay through PIM - No penalty for , versions PCI Compatible[1] Programmable Bus-Hold capabilities on all I/Os Intelligent product term , features user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply, can support 5V or 3.3V I/O levels. VCCO connections provide the
Cypress Semiconductor
Original
CERAMIC leaded CHIP CARRIER CLCC 68 CY37256P160-83UM 222-MH

3256E

Abstract: 20 A GND I/O21 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 , VCC GND GND NC VCC VCC I/O150 I/O151 NC I/O153 I/O190 I/O191 I/O168 I/O152 I/O187 I/O188 I/O189 NC , I/O167 NC I/O154 I/O155 I/O187 I/O190 U I/O83 NC GND I/O111 I/O112 I
Lattice Semiconductor
Original
3256E 0212/3256E 3256E-100LM 304-P 3256E-100LB320 320-B

3256E

Abstract: kc 59 246 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A , /O73 I/O110 I/O153 I/O190 I/O191 I/O168 Y I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I
Lattice Semiconductor
Original
kc 59 246 3256E-100LQ 3256E-70LQ 3256E-70LB320 2-0041/3256E
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