NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 9912 LOW POWER HALF ADDER This element is a multipurpose combination of three basic circuits that can be used as a complete half adder, an exclusive OR gate, gated-set flip-flop or any other similar logic construction. H = HIGH L = LOW POSITIVE LOGIC: H = 1 = TRUE L = 0 = FALSE NEGATIVE LOGIC: L = 1 = TRUE H = 0 = FALSE FUNCTIONS POSITIVE LOGIC: 7 = (1 + 2)_- (3 + 5) 6=1-2 + 3-5 NEGATIVE LOGIC: 7 = Ij2 , APPLICATIONS (POSITIVE LOGIC) OAB+AB EXCLUSIVE OR GATE OR HALF ADDER DATA A O CONTROL C O- CONTROL C O-DATABO- ... | OCR Scan |
1 pages, |
for half adder applications of half adder HALF ADDER datasheet abstract |
|
|||
| Abstract: fairchild micrologic half adder ... | OCR Scan |
1 pages, |
930 dtl 946 dtl dtl 930 dtl 946 UJ 9A DTL Fairchild rs-flip-flop "Monostable Multivibrator" rtl micrologic micrologic datasheet abstract |
|
|||
| Abstract: 904 Half Adder F10 3F,5B ^ F15 905 Half Shift F11 3F.5B - 719 928'- JK Flip«FI©f* F16 3F,5F cpif1 906 Half Shift F20 3F,5B f^O 927 Quad Inverter F17 3F,5F 8 907 4-lnput NOR F12 3F,5B ^ 958 Decade Counter F21 5B,6A- 908 Adder F1 3F,5B If- ^22 959 4-Bit Latch F 22 6B 909 Buffer F2 3F,5B ¿1 , F4 3F.5B if 325 989 Binary Counter F21 5B.6A =3/13 912 Half Adder F5 3F,5B c V rv DTL DTL ... | OCR Scan |
1 pages, |
rtl micrologic BCD-Decoder dtl 960 DTL Fairchild Fairchild 958 counter rtl nand gate rtl decade counter dtl 946 fairchild micrologic rs-flip-flop micrologic 930 dtl half adder datasheet abstract |
|
|||
| Abstract: 16 915 Dual 3-NOR F14 3F,5F 4 903 3-lnput NOR F9 3F,5B 17 921 Dual 2-Expander F7 3F,5B 5 904 Half Adder F10 3F,5B 18 923 JK Flip-Flop F15 5B 6 905 Half Shift F11 3F,5B 19 926 JK Flip-Flop F16 3F,5F 7 906 Half Shift F20 3F,5B 20 927 Quad Inverter F17 3F,5F 8 907 4-lnput NOR F12 3F,5B 21 958 Decade Counter F21 5B.6A 9 908 Adder F1 3F,5B 22 959 4-Bit Latch F22 6B 10 909 Buffer F2 3F,5B 23 960 BCD , 989 Binary Counter F21 5B,6A 13 912 Half Adder F5 3F,5B DTL DTL MICROLOGIC Item DEVICE NO. ... | OCR Scan |
2 pages, |
946 dtl DTL Fairchild Fairchild 902 fairchild 909 fairchild 927 Fairchild 958 fairchild rtl micrologic rtl micrologic 900 rtl micrologic A J16 dtl 932 DIGITAL-RTL datasheet abstract |
|
|||
| Abstract: 3-NOR F14 3F,5F 4 903 3-lnput NOR F9 3F,5B 17 921 Dual 2-Expander F7 3F,5B 5 904 Half Adder F10 3F,5B 18 923 JK Flip-Flop F15 5B 6 905 Half Shift F11 3F,5B 19 926 JK Flip-Flop F16 3F,5F 7 906 Half , Counter F21 5B,6A 13 912 Half Adder F5 3F,5B DTL DTL MICROLOGIC Item DEVICE NO. Description Logic , 5B.6A 9 908 Adder F1 3F,5B 22 959 4-Bit Latch F22 6B 10 909 Buffer F2 3F,5B 23 960 BCD Decoder/Dvr F23 ... | OCR Scan |
2 pages, |
rtl nand gate 912 f5 930 DTL dtl 960 Fairchild 902 fairchild 927 fairchild 937 fairchild 946 rtl micrologic 904 f10 DIGITAL-DTL 949 dtl rtl inverter micrologic datasheet abstract |
|
|||
| Abstract: Dual 2-Expander F7 3F,5B 5 904 Half Adder F10 3F,5B 18 923 JK Flip-Flop F15 5B 6 905 Half Shift F11 3F,5B 19 926 JK Flip-Flop F16 3F,5F 7 906 Half Shift F20 3F,5B 20 927 Quad Inverter F17 3F,5F 8 907 4-lnput NOR F12 3F,5B 21 958 Decade Counter F21 5B.6A 9 908 Adder F1 3F,5B 22 959 4-Bit Latch F22 6B 10 , 5B 12 911 4-lnput NOR F4 3F,5B 25 989 Binary Counter F21 5B,6A 13 912 Half Adder F5 3F,5B DTL ... | OCR Scan |
2 pages, |
dtl 960 Fairchild 902 fairchild 927 fairchild 944 Fairchild 958 counter 4 bit binary adder IC rtl micrologic rs-flip-flop dtl 932 dtl 946 g2-1802 DTL Fairchild Fairchild 958 datasheet abstract |
|
|||
| Abstract: 903 3-lnput NOR F9 3F,5B 17 921 Dual 2-Expander F7 3F,5B 5 904 Half Adder F10 3F,5B 18 923 JK Flip-Flop F15 5B 6 905 Half Shift F11 3F,5B 19 926 JK Flip-Flop F16 3F,5F 7 906 Half Shift F20 3F,5B 20 927 Quad Inverter F17 3F,5F 8 907 4-lnput NOR F12 3F,5B 21 958 Decade Counter F21 5B.6A 9 908 Adder , 13 912 Half Adder F5 3F,5B DTL DTL MICROLOGIC Item DEVICE NO. Description Logic/Connection ... | OCR Scan |
2 pages, |
rtl micrologic 900 951 monostable 951 Monostable Multivibrator BCD-Decoder Fairchild 902 fairchild 927 fairchild 945 Fairchild 958 counter half adder inverter diagrams DTL Fairchild 945 DIGITAL-DTL 930 DTL datasheet abstract |
|
|||
| Abstract: Half Adder 6JC 39 x 36 MCC705 MCC705 MCC805 MCC805 MCC905 MCC905 Half Shift Register C02 40 x 40 MCC706 MCC706 MCC806 MCC806 MCC906 MCC906 Half , MCC808 MCC808* MCC908 MCC908 Half Adder 3JB 43 x 34 MCC709 MCC709 MCC809 MCC809* MCC909 MCC909 2-lnput Buffer C15 32 x 39 MCC710 MCC710 MCC810 MCC810 , MCC812 MCC812* MCC912 MCC912 Half Adder 3JB 43 x 34 MCC713 MCC713 MCC813 MCC813* MCC913 MCC913 Type D Flip Flop 1JD 48 x 57 MCC714 MCC714 MCC814 MCC814 , MCC975 MCC975 Dual Half Adder 19K 36 x 37 MCC776 MCC776 MCC876 MCC876* MCC976 MCC976 Dual J-K Flip Flop E90 50 x 58 MCC777 MCC777 MCC877 MCC877 , 50 x 50 MCC783 MCC783 MCC883 MCC883 MCC983 MCC983 Dual Half Shift Register 54K 43 x 37 MCC784 MCC784 MCC884 MCC884 MCC984 MCC984 Dual Half ... | OCR Scan |
2 pages, |
"J-K Flip flop" MCC784 mcc789 MCC800 MCC801 MCC806 r-s flip flop quad jk flip flop MCC713 MCc700 MCC783 4 input d flip flop JK flip flop MCC890 datasheet abstract |
|
|||
| Abstract: 903/G 903/G,H 16 5 - 12 Half Adder 904/G 904/G.H 16 5 - 14 Half-Shift Register 905/G 905/G,H 13 4 - 22 Half-Shift Register (w/o Inverter) 90g/G,H 13 4 - 22 4-lnput NOR Gate 907/G 907/G.H 16 5 - 12 Half Adder 908/G 908/G,H - - 4 , 911/G 911/G.H - - 4 60 Half Adder 912/G 912/G.H - - 4 66 Type D Flip-Flop 913/G 913/G,H - - 3 75 Dual 2-lnput NOR , J-K Flip-Flop 974/G 974/G.H 16 5 - 35 Dual Half Adder 975/C 975/C,A 16 5 - 20 Dual J-K Flip-Flop 976/C 976/C.A - - , 3-lnput NOR Gate 993/C 993/C,A - 4 27 Serial-Parallel Shift Register 894/C 894/C 16 5 - 55 Dual Full Adder 996 ... | OCR Scan |
4 pages, |
9824 motorola 9813 916-C rtl decade counter bcd subtractor half adder BCD adder and subtractor datasheet abstract |
|
|||
| Abstract: ,5F 4 903 3-lnput NOR F9 3F,5B 17 921 Dual 2-Expander F7 3F,5B 5 904 Half Adder F10 3F,5B 18 923 JK Flip-Flop F15 5B 6 905 Half Shift F11 3F,5B 19 926 JK Flip-Flop F16 3F,5F 7 906 Half Shift F20 3F,5B 20 927 Quad Inverter F17 3F,5F 8 907 4-lnput NOR F12 3F,5B 21 958 Decade Counter F21 5B.6A 9 908 Adder , 13 912 Half Adder F5 3F,5B DTL DTL MICROLOGIC Item DEVICE NO. Description Logic/Connection ... | OCR Scan |
3 pages, |
rtl nand gate 951 monostable 951 Monostable Multivibrator dtl 946 Fairchild 902 Fairchild 958 counter rtl micrologic half adder micrologic DIGITAL-DTL 949 dtl 946 dtl 930 dtl datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| . - The design consists of two kinds of cells: - LSB cell, a half-adder and repeating cells of full-adders. | - - ADD_UC : N of LSB cell, half adder - LIBRARY IEEE; USE _uc_hadder; - architecture delcaration for LSB cell, half adder ARCHITECTURE struct OF add_uc_hadder IS COMPONENT adder; - #Description: ADD_UC adds two n-bits unsigned-binary words I0 and I1, - and www.datasheetarchive.com/download/5692482-988247ZC/wcd03623.zip (add_uc.vhd) |
Xilinx | 12/02/1999 | 571.77 Kb | ZIP | wcd03623.zip |
| . - The design consists of two kinds of cells: - LSB cell, a half-adder and repeating cells of full-adders. | - - ADD_UC : N of LSB cell, half adder - LIBRARY IEEE; USE _uc_hadder; - architecture delcaration for LSB cell, half adder ARCHITECTURE struct OF add_uc_hadder IS COMPONENT adder; - #Description: ADD_UC adds two n-bits unsigned-binary words I0 and I1, - and www.datasheetarchive.com/download/93627041-987072ZC/wcd02e3f.zip (add_uc.vhd) |
Xilinx | 13/07/1998 | 571.77 Kb | ZIP | wcd02e3f.zip |
| _uc_con; - - entity declaration of LSB cell, half adder ; - architecture delcaration for LSB cell, half adder ARCHITECTURE struct OF hadder IS COMPONENT and2 . - - ADD_UC : N-bit unsigned I0 + I1 adder CONSTANT c_period: time := 10 ns; - default adder delay BEGIN - behave PROCESS ; - - entity declaration of repeating cell, full adder www.datasheetarchive.com/download/5692482-988247ZC/wcd03623.zip (add_uc.vhd) |
Xilinx | 12/02/1999 | 571.77 Kb | ZIP | wcd03623.zip |
| _uc_con; - - entity declaration of LSB cell, half adder ; - architecture delcaration for LSB cell, half adder ARCHITECTURE struct OF hadder IS COMPONENT and2 . - - ADD_UC : N-bit unsigned I0 + I1 adder CONSTANT c_period: time := 10 ns; - default adder delay BEGIN - behave PROCESS ; - - entity declaration of repeating cell, full adder www.datasheetarchive.com/download/93627041-987072ZC/wcd02e3f.zip (add_uc.vhd) |
Xilinx | 13/07/1998 | 571.77 Kb | ZIP | wcd02e3f.zip |
| . AND, OR, and NOR gates (2, 3, 4, 5, and 8) One-bit adders and half adders 2-of-3 majority shows how an N-bit ripple-carry adder can be created from N one-bit adders. library GTECH; use www.datasheetarchive.com/files/xilinx/docsan/vhd/vhd3_4.htm |
Xilinx | 12/11/1998 | 12 Kb | HTM | vhd3_4.htm |
| AD210 AD210 AD210 AD210;AD220 AD220 AD220 AD220;Adder: 1 Bit Half Adder AN210 AN210 AN210 AN210;AN220 AN220 AN220 AN220;AND Gate: 2-input AN310 AN310 AN310 AN310;AN320 AN320 AN320 AN320;AND Gate: 3-input AN410 AN410 AN410 AN410;AN420 AN420 AN420 AN420;AND Gate: 4-input AN510 AN510 AN510 AN510;AN520 AN520 AN520 AN520;AND Gate: 5-input AN810 AN810 AN810 AN810;AN820 AN820 AN820 AN820;AND Gate: 8-input BF001 BF001 BF001 BF001;BH001 BH001 BH001 BH001;Boolean Gate: Y = -(A1+B1*B2) BF002 BF002 BF002 BF002;BH002 BH002 BH002 BH002;Boolean Gate: Y = -(A1+B1*B2*B3) BF003 BF003 BF003 BF003;BH003 BH003 BH003 BH003;Boolean Gate: Y = -(A1*A2)+(B1*B2) BF006 BF006 BF006 BF006;BH006 BH006 BH006 BH006;Boolean Gate: Y = -(A1+A2+B1*B2) BF011 BF011 BF011 BF011;BH011 BH011 BH011 BH011;Boolean Gate: Y = -(A1*A2+B1*B2+C1*C2) BF015 BF015 BF015 BF015;BH015 BH015 BH015 BH015;Boolean Gate: Y = -(A1+B1*(C1+C2) BF022 BF022 BF022 BF022;BH022 BH022 BH022 BH022 www.datasheetarchive.com/files/texas-instruments/sc/docs/military/product/asic/tgc1000/working/core.txt |
Texas Instruments | 07/11/1996 | 7.29 Kb | TXT | core.txt |
| TI MILTARY ASIC TGC1000 TGC1000 TGC1000 TGC1000 MILITARY SERIES 0.7-um CMOS GATE ARRAYS February 1992 - Revised October 1995 core macros Core Macro Selection Guide FUNCTION MACRO NORMAL DRIVE HIGH DRIVE Adder: 1 Bit Half Adder AD210 AD210 AD210 AD210 AD220 AD220 AD220 AD220 AND Gate: 2-input AN210 AN210 AN210 AN210 AN220 AN220 AN220 AN220 AND Gate: 3 www.datasheetarchive.com/files/texas-instruments/sc/docs/military/product/asic/tgc1000/fds/core.htm |
Texas Instruments | 07/11/1996 | 23.09 Kb | HTM | core.htm |
| left. The two partial products are added with two half-adders. When there are more bits in the partial product terms, full-adders will be necessary to produce the sum. Note that the least significant bit does not need to go through an adder stage since it is formed by the output of the first AND gate and ( j - 1) k -bit full-adders are required to produce a product of j + k bits -Tap FIR filter design uses serial adders to sum the two taps with equal coefficients. This serial www.datasheetarchive.com/files/xilinx/weblinx/appnotes/dspx5dev.htm |
Xilinx | 13/01/1997 | 25.74 Kb | HTM | dspx5dev.htm |
| left. The two partial products are added with two half-adders. When there are more bits in the partial product terms, full-adders will be necessary to produce the sum. Note that the least significant bit does not need to go through an adder stage since it is formed by the output of the first AND gate and ( j - 1) k -bit full-adders are required to produce a product of j + k bits -Tap FIR filter design uses serial adders to sum the two taps with equal coefficients. This serial www.datasheetarchive.com/files/xilinx/docs/wcd00013/wcd013d6.htm |
Xilinx | 16/02/1999 | 26.74 Kb | HTM | wcd013d6.htm |
| left. The two partial products are added with two half-adders. When there are more bits in the partial product terms, full-adders will be necessary to produce the sum. Note that the least significant bit does not need to go through an adder stage since it is formed by the output of the first AND gate and ( j - 1) k -bit full-adders are required to produce a product of j + k bits -Tap FIR filter design uses serial adders to sum the two taps with equal coefficients. This serial www.datasheetarchive.com/files/xilinx/docs/wcd00010/wcd010b1-v1.htm |
Xilinx | 17/07/1998 | 26.65 Kb | HTM | wcd010b1-v1.htm |