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Part | Manufacturer | Description | Samples | Ordering |

Catalog Datasheet | MFG & Type | Document Tags |

Abstract: two-multiplier adder units (2 two-multiplier adder units per half block). Therefore, there are eight 18 × 18 , From Previous Half DSP Block Half DSP Block Output Register Bank Round/Saturate Adder , two-multiplier adder in the other half block. This increases DSP block resource efficiency and allows you to , the first-stage adder. There are four first-stage adders in a DSP block (two adders per half DSP , can route the chainout results to the input of the next half block's chainout adder input or to the ... | Altera Original |
36 pages, |
EP4SGX70 clock select adder with sharing EP4SE230 EP4SE360 EP4SE530 EP4SE820 EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX360F1932 0x0000100 32-bit adder datasheet for full adder and half adder SIV51004-3 SIV51004-3 TEXT |

Abstract: . There are four first-stage adders in a DSP block (two adders per half DSP block). The first-stage adder , multipliers using the two-multiplier adder mode. A single half DSP block can implement one 18-bit complex , two-multiplier adders, with multiplier precision of 18 × 36 (one two-multiplier adder per DSP half block). This , Multipliers Four Multiplier Adder Mode High Precision Multiplier Adder Mode 18 × 18 18 × 36 , . Basic Two-Multiplier Adder Building Block A0[17.0] B0[17.0] +/- A1[17.0] Q B1[17.0 ... | Altera Original |
42 pages, |
16 bit full adder half adder datasheet EP3SE50 4 bit multiplier barrel shifter block diagram 32-bit adder multiplier bit half adder datasheet for full adder and half adder circuit diagram of half adder SIII51005-1 TEXT |

Abstract: . There are four first-stage adders in a DSP block (two adders per half DSP block). The first-stage adder , implement complex multipliers using the two-multiplier adder mode. A single half DSP block can implement , adder per half DSP block). These modes are useful for implementing one-dimensional and two-dimensional , Multipliers Multipliers Multipliers Complex Multipliers Four Multiplier Adder Mode 18 × 18 EP3SL50 EP3SL50 , Two-Multiplier Adder Building Block A0[17.0] B0[17.0] +/- A1[17.0] D Q B1[17.0] D P ... | Altera Original |
50 pages, |
half adder datasheet EP3SE50 BUTTERFLY DSP 0x0000100 32-bit adder datasheet for full adder and half adder circuit diagram of half adder SIII51005-1 TEXT |

Abstract: two-bit adder stage. Again, for a given size adder, using two-bit adders involves half as many stages , 24-Bit Adder Implementation in a CPLD To build an adder of any size, simply cascade any number , higher order stage. However, such an adder incurs an additional propagation delay for each stage as the , -bit adder in a Lattice Complex Programmable Logic Device, or CPLD. It is possible to implement a full 24-bit adder in just three levels of logic, allowing the adder to run at slightly over one-third the maximum ... | Lattice Semiconductor Original |
7 pages, |
xor and or full adder half adder datasheet datasheet of half adder pin 8 bit half adder Half Adders for full adder and half adder datasheet for full adder and half adder TEXT |

Abstract: stage for a given size adder. As a result, the highest order CIN equation requires half as many product , 24-Bit Adder Implementation in a CPLD Introduction High speed DSP and arithmetic functions are in , illustrate how to optimize a 24-bit adder in a Lattice Complex Programmable Logic Device (CPLD). It is possible to implement a full 24-bit adder in just three levels of logic, allowing the adder to run at , In-System Programmable (ISPTM) CPLDs in the industry. Since the implementation of an adder in a CPLD ... | Lattice Semiconductor Original |
7 pages, |
for full adder and half adder TEXT |

Abstract: performance (Figure 2). The adder is divided into two sections. The lower half operates normally, but in the , conditional-sum technique. In the upper half of a conditional-sum adder, two complete adders are implemented , simple adder uses two function generators and a carry chain multiplexer, as shown in Figure 1. However, not all of the function generator's capability is utilized in the basic adder. In the input function generator, the adder input, bi, can be any function of the three inputs that are available. For example ... | Xilinx Original |
3 pages, |
bit-slice data sheet half adder Function GENERATOR Half Adders 4 bit parallel adders XC4000 XC520 type of Adders Adders half adder Applications of "XOR Gate" half adder datasheet half adder XOR Gates datasheet for half adder "function generator" multiplier using CARRY SELECT adder xor gate schematic XOR Gates "XOR Gate" 5 bit multiplier using adders TEXT |

Abstract: Each half DSP block can implement four 18-bit multipliers and have a built-in adder tree to combine , . The results from each half DSP block can then be added together using the chain out adder. The input , Included chain out adder for efficient cascaded adder structure implementation Built-in rounding and , In most circumstances, these half-blocks are identical in functionality. Each half DSP block can be , 36 x 36 multiplier. In multiply and add mode, each half DSP block can implement four multipliers ... | Altera Original |
24 pages, |
multiplier accumulator unit with VHDL design of FIR filter using vhdl AN5041 32 bit carry select adder in vhdl clock select adder with sharing TEXT |

Abstract: two-bit adder stage. Again, for a given size adder, using two-bit adders involves half as many stages , 24-Bit ADDER Implementation in a CPLD To build an adder of any size, simply cascade any number , higher order stage. However, such an adder incurs an additional propagation delay for each stage as the , -bit adder in a Lattice Complex Programmable Logic Device, or CPLD. It is possible to implement a full 24-bit adder in just three levels of logic, allowing the adder to run at slightly over one-third the maximum ... | Lattice Semiconductor Original |
7 pages, |
for full adder and half adder applications of half adder abel compiler TEXT |

Abstract: block contains four two-multiplier adder units (2 two-multiplier adder units per half block). Therefore , single DSP block to operate a 9 × 9 multiplier in one half block and an 18 × 18 two-multiplier adder in , input of the next half block's chainout adder input or to the general fabric (functioning as regular , Multiplier Adder Mode Independent Input and Output Multiplication Operators DSP Blocks Device 9×9 12 × 12 18 × 18 Multipliers Multipliers Multipliers Four Multiplier Adder Mode 18 × 18 ... | Altera Original |
32 pages, |
EP2AGX65 EP2AGX45 EP2AGX260 EP2AGX190 EP2AGX125 barrel shifter block diagram Altera Arria V Video circuit diagram of half adder datasheet for full adder and half adder AIIGX51004-3 TEXT |

Abstract: two-bit adder stage. Again, for a given size adder, using two-bit adders involves half as many stages , 24-Bit ADDER Implementation in a CPLD To build an adder of any size, simply cascade any number , higher order stage. However, such an adder incurs an additional propagation delay for each stage as the , -bit adder in a Lattice Complex Programmable Logic Device, or CPLD. It is possible to implement a full 24-bit adder in just three levels of logic, allowing the adder to run at slightly over one-third the maximum ... | Lattice Semiconductor Original |
8 pages, |
for full adder and half adder applications of half adder TEXT |

Abstract | Saved from | Date Saved | File Size | Type | Download |

TI MILTARY ASIC TGC1000 TGC1000 MILITARY SERIES 0.7-um CMOS GATE ARRAYS February 1992 - Revised October 1995 core macros Core Macro Selection Guide FUNCTION MACRO NORMAL DRIVE HIGH DRIVE Adder: 1 Bit Half Adder AD210 AD210 AD220 AD220 AND Gate: 2-input AN210 AN210 AN220 AN220 AND Gate: 3-input AN310 AN310 AN320 AN320 AND Gate: 4-input AN410 AN410 AN420 AN420 AND Gate: 5-input
/datasheets/files/texas-instruments/sc/docs/military/product/asic/tgc1000/fds/core.htm |
Texas Instruments | 07/11/1996 | 23.09 Kb | HTM | core.htm |

AD210 AD210;AD220 AD220;Adder: 1 Bit Half Adder AN210 AN210;AN220 AN220;AND Gate: 2-input AN310 AN310;AN320 AN320;AND Gate: 3-input AN410 AN410;AN420 AN420;AND Gate: 4-input AN510 AN510;AN520 AN520;AND Gate: 5-input AN810 AN810;AN820 AN820;AND Gate: 8-input BF001 BF001;BH001 BH001;Boolean Gate: Y = -(A1+B1*B2) BF002 BF002;BH002 BH002;Boolean Gate: Y = -(A1+B1*B2*B3) BF003 BF003;BH003 BH003;Boolean Gate: Y = -(A1*A2)+(B1*B2) BF006 BF006;BH006 BH006;Boolean Gate: Y = -(A1+A2+B1*B2) BF011 BF011;BH011 BH011;Boolean Gate: Y = -(A1*A2+B1*B2+C1*C2) BF015 BF015;BH015 BH015;Boolean Gate: Y =
/datasheets/files/texas-instruments/sc/docs/military/product/asic/tgc1000/working/core.txt |
Texas Instruments | 07/11/1996 | 7.29 Kb | TXT | core.txt |

No abstract text available
/download/5692482-988247ZC/wcd03623.zip () |
Xilinx | 12/02/1999 | 571.77 Kb | ZIP | wcd03623.zip |

No abstract text available
/download/93627041-987072ZC/wcd02e3f.zip () |
Xilinx | 13/07/1998 | 571.77 Kb | ZIP | wcd02e3f.zip |

/tbinH) ;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder of number to be multiplied by 10 .def adder =r19 ;value to add after multiplication ;* Code mul10a: ;* multiplies "mp10H:mp10L" with 10 and adds "adder" high nibble swap adder mul10b: ;* multiplies "mp10H:mp10L" with 10 and adds "adder" low nibble mov copyL,mp10L ;make copy mov copyH,mp10H copy to original adc mp10H,copyH andi adder,0x0f ;mask away upper nibble of adder add mp10L,adder
/datasheets/files/atmel/atmel/software/avr204.asm |
Atmel | 30/01/2000 | 11.66 Kb | ASM | avr204.asm |

,mp10L/tbinL,mp10H/tbinH) ;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder of number to be multiplied by 10 .def adder =r19 ;value to add after multiplication ;* Code mul10a: ;* multiplies "mp10H:mp10L" with 10 and adds "adder" high nibble swap adder mul10b: ;* multiplies "mp10H:mp10L" with 10 and adds "adder" low nibble mov copyL,mp10L ;make copy mov copyH,mp10H mp10L,copyL ;add copy to original adc mp10H,copyH andi adder,0x0f ;mask away upper nibble of adder
/datasheets/files/atmel/atmel/software/avr204-v1.asm |
Atmel | 13/01/1998 | 12.06 Kb | ASM | avr204-v1.asm |

] Description=Rectifies the negative half cycles of the waveform, as the previous cell is an inverting ADDer Caption=REC [TopCell3] Description=Rectifies the positive half cycles of the waveform Caption=REC [TopCell4] Caption=NIP [TopCell5] Description=Adds the positive and inverted negative half cycles of the rectified differences between the positive and negative half cycles. (Not needed in simulation) Caption=ADD
/datasheets/files/zetex/fas/download/samples/fuwavrct.ptd |
Zetex | 22/07/1999 | 1.34 Kb | PTD | fuwavrct.ptd |

6 BIT BINARY SOURCE 6bitbiny.amp ADDER Adder.amp BIPOLAR HALF WAVE RECTIFIER Hawavrec.amp INTEGRATING OSCILLATOR Integosc.amp INTEGRATING OSCILLATOR int-osc.ptd HALF WAVE RECTIFIER hawaverec.ptd
/datasheets/files/zetex/fas/t_dlib.htm |
Zetex | 13/04/1999 | 10.06 Kb | HTM | t_dlib.htm |

6 BIT BINARY SOURCE 6bitbiny.amp ADDER Adder.amp BIPOLAR HALF WAVE RECTIFIER Hawavrec.amp INTEGRATING OSCILLATOR Integosc.amp INTEGRATING OSCILLATOR int-osc.ptd HALF WAVE RECTIFIER hawaverec.ptd
/datasheets/files/zetex/fas/t_dl~584.htm |
Zetex | 21/12/1998 | 10.05 Kb | HTM | t_dl~584.htm |

of the cascade adder can optionally be full-wave or half wave rectified under the control of BCR0[7,6 : The input block (shifter, cascade adder and rectifier unit),a statistics monitor,the data con- output block (output adder and multiplexers). A detailed diagram of the Backend Post-Processor is given other- wise stated. IMSA110 IMSA110 5/26 5.1 Shifter, Cascade Adder and Rectifier Data from the mac array enters by the status bits BCR0[5-1]. The output of the shifter passes into the cascade adder where it is
/datasheets/files/stmicroelectronics/books/ascii/docs/1126.htm |
STMicroelectronics | 25/05/2000 | 69.51 Kb | HTM | 1126.htm |