NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| EP20K100E-1 | Altera Corporation | Programmable Logic Device |
114 pages, |
Original |  |
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| EP20K100E-1BGA356 | Altera Corporation | Programmable Logic Device |
116 pages, |
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| EP20K100E-1-BGA356 | Altera Corporation | Programmable Logic Device |
8 pages, |
Original | |
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| EP20K100E-1LBGA144 | Altera Corporation | Programmable Logic Device |
56 pages, |
Original | |
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| EP20K100E-1-LBGA144 | Altera Corporation | Programmable Logic Device |
116 pages, |
Original | |
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| EP20K100E-1LBGA324 | Altera Corporation | Programmable Logic Device |
12 pages, |
Original | |
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| EP20K100E-1-LBGA324 | Altera Corporation | Programmable Logic Device |
116 pages, |
Original | |
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| EP20K100E-1PQFP208 | Altera Corporation | Programmable Logic Device |
56 pages, |
Original | |
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| EP20K100E-1-PQFP208 | Altera Corporation | Programmable Logic Device |
8 pages, |
Original | |
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| EP20K100E-1PQFP240 | Altera Corporation | Programmable Logic Device |
56 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: EP20K100E-1 5 16 16 64 3,022 4 98 1 IFFT EP20K100E-1 5 16 16 64 3,027 4 98 1 FFT EP20K100E-1 5 16 16 512 3,116 10 96 27 IFFT EP20K100E-1 5 16 16 512 3,121 10 101 26 FFT EP20K100E-1 5 16 16 1,024 3,126 20 100 52 IFFT EP20K100E-1 5 16 16 1,024 3,131 20 96 ... | Original |
36 pages, |
EP20K100E-1 CY7C1335 COS ROM CODE IN MATLAB Altera fft megacore 8 point fft code in vhdl verilog code for FFT vhdl code for FFT how to test fft megacore verilog for 8 point fft vhdl code for 16 point radix 2 FFT verilog code for FFT 16 point verilog code for FFT 32 point datasheet abstract |
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| Abstract: Logic Frequency Special Features Apex 20KE EP20K100E-1 3,069 LEs 68 MHz 3 ESB ... | Original |
2 pages, |
EP20K100E-1 EP1S10-C5 dct verilog code datasheet abstract |
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| Abstract: off-chip. Altera Device Apex 20KE EP20K100E-1 Apex-II EP2A15-C7 EP2A15-C7 Cyclone EP1C6-C6 Stratix EP1S10-C5 EP1S10-C5 ... | Original |
2 pages, |
EP20K100E-1 dct verilog code datasheet abstract |
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| Abstract: APEX 20K vs. Virtex Technical Brief 57 October 1999, ver.1 Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408)544-7000 http://www.altera.com https://websupport.altera.com 163-1332 6-5-1 32F 1594 TEL. 03-3340-9480 FAX. 03-3340-9487 http://www.altera.com/japan E-mail:japan@altera.com CPLDComplex Programmable Logic Device FPGAField Programmable Gate Array CPLD FPGA APEX 20KTM 20KTM EP20K100 EP20K100 Virtex XCV150 XCV150 Hewl ... | Original |
6 pages, |
XCV150 EP20K100E EP20K100 8110A 8840a FLUKE 8840a 20KTM 20KTM abstract |
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| Abstract: Power Consumption Comparison: APEX 20K vs. Virtex Devices Technical Brief 57 October 1999, ver. 1 Introduction Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com https://websupport.altera.com Many factors, such as supply voltage, current consumption, die size, and routing structure, affect semiconductor power consumption. For devices with the same supply voltages, the device current determines power consumption. Although modeling ... | Original |
6 pages, |
"Dual-Port RAM" XCV150 8840a Dualport ram fluke 77 EP20K100 EP20K100E FLUKE 75 lcd graphics display 64128 Xilinx XCV150 FLUKE 8840a EP20K100 abstract |
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| Abstract: 1. Altera Configuration Devices CF52001-2 CF52001-2.3 Introduction During device operation, Altera® FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can configure Stratix® series, Cyclone® series, APEXTM II, APEX 20K, MercuryTM, ACEX® 1K, FLEX® 10K, and FLEX 6000 devices using data stored in an Altera configuration device. Altera configuration devices are offered in differe ... | Original |
8 pages, |
EP20K200E EP20K400E EP20K60E EP2S15 EP2S30 EP2S60 epc1213 EPC1441 EPC16 EPCS16 EPCS64 CF52001-2 CF52001-2 abstract |
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| Abstract: Chapter 1. Altera Configuration Devices CF52001-2 CF52001-2.0 Introduction During device operation, Altera® FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can configure Stratix® series, CycloneTM series, APEXTM II, APEX 20K, MercuryTM, ACEX® 1K, FLEX® 10K, and FLEX 6000 devices using data stored in an Altera configuration device. Altera configuration devices are offered i ... | Original |
8 pages, |
EPF10K100 EP20K400E EP20K60E EP2S15 EP2S30 EP2S60 epc1213 EPC1441 EPC16 EPCS4 EPCS64 EP20K200E EPCS16 CF52001-2 CF52001-2 abstract |
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| Abstract: Preliminary Information APEX 20K Programmable Logic Device Family Data Sheet APEX 20K ® 1999 8 ver. 2.02J Data Sheet s Preliminary Information s System-on-a-Programmable-ChipTM PLD - LUT MultiCoreTM - ESB - LUT - ESBFIFOFirst-In First-Out RAMCAMContent-Addressable Memory - 60,0001,500,000 - 54,720LE 720LE - 466,944RAM 944RAM - 3,648 APEX 20K(1)(2) EP20K60E EP20K60E EP20K100E EP20K100E EP20K160E EP20K160E EP20K200E EP20K200E EP20K300E EP20K300E EP20K400E EP20K400E EP20K600E EP20K600E EP20K1000E EP20K1000E EP20K1500E EP20K1500E ... | Original |
68 pages, |
EP20K60E BE13 EP20K100 EP20K1000E EP20K100E EP20K1500E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400E EP20K600E BC35 BE35 datasheet abstract |
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| Abstract: ® May 1999, ver. 1.0 Introduction Using the ClockLock & ClockBoost Features in APEX Devices Application Note 115 APEXTM 20K devices have the ClockLockTM and ClockBoostTM features, which use PLLs to increase performance and provide clock-frequency synthesis. The ClockLock feature minimizes clock delay and clock skew within the device, reducing clock-to-output and setup times while maintaining zero hold times. The ClockBoost feature allows designers to run the internal logic of ... | Original |
28 pages, |
EP20K300E led using clock circuit diagram with EP20K200E EP20K200 EP20K160E EP20K100E EP20K100 DC MOTOR SPEED CONTROL USING VHDL vhdl code for PLL synchronisation EP20K400E frequency multiplier in Mhz pulse width measure counter delay clock schematic diagram motor control datasheet abstract |
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| Abstract: 5. Configuration Devices for SRAM-Based LUT Devices Data Sheet CF52005-2 CF52005-2.1 Features f Altera Corporation August 2005 Configuration device family for configuring Stratix® series, CycloneTM series, APEXTM II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX® 1K, and FLEX® (FLEX 10KE, and FLEX 10KA) devices Easy-to-use 4-pin interface to Altera® FPGAs Low current during configuration and near-zero standby current 5.0-V and 3.3- ... | Original |
34 pages, |
EPCS64 EPCS16 EPC16 EPC1441 EPC1213 EPC1064 CF52005-2 CF52005-2 abstract |
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