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SN74LS05DBLE Texas Instruments IC LS SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SSOP-14, Gate ri Buy
SN74LS05N3 Texas Instruments IC LS SERIES, HEX 1-INPUT INVERT GATE, PDIP14, PLASTIC, DIP-14, Gate ri Buy
SN74LS05DR Texas Instruments Hex inverters with open collector outputs 14-SOIC 0 to 70 ri Buy

Datasheet of IC 74ls05

Catalog Datasheet Results Type PDF Document Tags
Abstract: SN74LS05DN SN74LS05DN U1 IC, 74LS05 surface mount 3 1 RS6A103G RS6A103G RN1 Description 10k ohm 6 pin Sip , standard I2C drivers or the Raytheon Raydemo software. · Evaluation of Raytheon demo boards · System , Port 74LS05 Rev. 0.9.0 PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They , 25 13 1 SCL +5V SDA GND 74LS05 15-83-0064 U1B 4 3 74LS05 U1C 6 5 74LS05 ... Original
datasheet

4 pages,
21.82 Kb

TMC2070P7C TMC2068P7C RAYTHEON SEMICONDUCTOR 74ls05 ic datasheet DB25 Parallel DB25 Parallel connector marking 722 15-83-0064 datasheet connector DB25 74LS05 of IC 74ls05 RAYTHEON Raytheon Electronics TMC2070P7C abstract
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Abstract: MiniReel: 444-810 C1 10uf 16v 2 1 SN74LS05DN SN74LS05DN U1 IC, 74LS05 surface mount 3 1 , drivers or the Fairchild Raydemo software. · Evaluation of Fairchild demo boards · System , Port 74LS05 Rev. 0.9.0 PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They , 25 13 1 SCL +5V SDA GND 74LS05 15-83-0064 U1B 4 3 74LS05 U1C 6 5 74LS05 ... Original
datasheet

4 pages,
28.11 Kb

TMC2070P7C TMC2068P7C Fairchild marking format DB25 Parallel connector 74LS05 c1 10uf 16v parallel i2C 74Ls05 TMC2070P7C abstract
datasheet frame
Abstract: supply your own 18 pin ZIF socket. Use the 14 pin IC socket to mount the 74LS05 or 74LS06 74LS06. You will need , KIT 119. SERIAL 8 & 18 PIN PIC PROGRAMMER This is a kit of parts to use the P16PRO P16PRO software of , parallel ports of a PC. A serial programmed PIC refers to the programming algorithm by which data enters , toggled. You must download the latest version of the P16PRO P16PRO software from: www.geocities.com , them in the device.ini file of the software. Schematic. You may download the schematic for the 8/18 ... Original
datasheet

1 pages,
7.28 Kb

PIC12CE67X PIC16C61 PIC16C620 PIC16C67 PIC16C67X PIC16C710 PIC16C711 74ls05 ic datasheet 470uf,35v PIC16F83 40 pin zif socket not 74Ls05 18 PIN IC PIC16C715 P16PRO 16C5X P16PRO abstract
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Abstract: selection of Texas Instruments products will save you about 6-20% off TI and competitive prices, as illustrated on page 1. And if your project doesn't require a specific brand of IC, select from the , doesn't require a specific brand of IC, select from the functionally equivalent Jameco Value Offering , family of high speed advanced bipolar logic DIP SOIC Save Up To 20% When Purchasing Texas , Jameco Value Offering Jameco now offers two ways to save! Our selection of Texas Instruments products ... Original
datasheet

1 pages,
33.74 Kb

of ic 74ls08n of IC 74ls10 74LSxx 74lsxxx Datasheet of IC 74ls10 74ls04 dip 74ls10 IC 74ls10n datasheet of ic 74ls00 74ls04 hex inverter 74LS11N IC 74LS14 74LS02N datasheet abstract
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Abstract: ill becom e low, and w hen A is low, Y w ill becom e high. Note that this IC differs from the 74LS05 , DESCRIPTION The M74HC05 M74HC05 is a semiconductor integrated circuit con sisting of six inverters with open-drain , 25 "C , quiescent state) High noise m argin: 30% of VCc, min (V Cc = 4.5V, 6V) C apa ble of driving , 14P2N 14P2N 14P2P 14P2P * : O p e n -d ra in o u tp u t Use of silicon gate technology allows the M74HC05 M74HC05 to m aintain the low pow er dissipation and high noise margin cha racte ristics of the standard C M O S logic ... OCR Scan
datasheet

9 pages,
418.93 Kb

of IC 74ls05 M74HC05P/FP/DP M74HC05P/FP/DP abstract
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Abstract: OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS05 Tw B1R , the same high speed perirmance of LSTTL combined with true CMOS low awer consumption. he internal circuit is composed of 3 stages inclu ng buffer output, which enables high noise immuty and stable output. , oruary 1993 1/4 127 M 54/M 74HC05 74HC05 TRUTH TABLE A L H Z = High im pedance IEC LOG IC SY M B , Outputs Ground (0V) Positive Supply Voltage (9) ( 11) ( 13) ( 12) ' cv L O G IC D IA G R A M (P ... OCR Scan
datasheet

4 pages,
89.2 Kb

M74HC05C1 M54HC05 M74HC05 54/74LS05 M54HC05 abstract
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Abstract: b e rs s h o w n a re fo r D , J . N PRODUCTION DATA documents contain information currant as of publication date. Products conform to specifications per the terms of Taxas Instruments standard warranty. Production processing does not necessarily induoe testing of all parameters. | I v iC T D l Ifc ir M T C I , for operation over the full military temperature range of - 5 5 ° C to 125°C . The S N 7 4 0 5 , S N 7 , PACKAG E D O R N PACKAG E SN 74LS05, S N 74S05 74S05 . IT O P V IE W ) 1A 1Y 2A 2Y 3A 3Y G N D C 1 U m ... OCR Scan
datasheet

5 pages,
101.19 Kb

SN5405 SN54LS05 SN54S05 SN7405 74LS0 SN74S05 SN5405 abstract
datasheet frame
Abstract: Voltage Range V cc(opr.)=2V -6V · Open D rain Structure · Pin and Function Com patible with 74LS05 , UNIT V V V mA mA mA mA mW *500mW in the range of Ta= -40*C~ 65^0. From Ta=65'C to 85*C a derating factor of -lO m W /t shall be applied until 300mW. t °C R E C O M M E N D E D O P E R A T IN G C , (VCC=2.0V) 0 ~ 500(VOC=4.5V) 0 ~ 400(VCC=6.0V) o~voe o~voe UNIT V V V t ns DC E L E C T R IC A L C H A R A C T E R IS T IC S PARA M ETER SYMBOL H igh-L evel Input Voltage Low-Level Input Voltage ... OCR Scan
datasheet

3 pages,
76.67 Kb

TC74HC05AP/AF TC74HC05A TC74HC04A 74LS05 TC74HC05AP/AF abstract
datasheet frame
Abstract: a. TY P IC A L 7 4LS 04 74LS05 b. T Y P IC A L IN V E R T IN G C IR C U IT (SEE NO TE 12) N O N , DUAL LOGIC INTERFACE OPTOCOUPLER H rp. T E C H N IC A L D A T A DECEM BER 1981 9.40 , TEST VOLTAGE · OPEN COLLECTION OUTPUTS · RECOGNIZED UNDER THE COMPONENT PROGRAM OF UNDERWRITERS , provide enough o utput current fo r proper operation of 1 LSTTL gate under worst-case conditions when used in the recom mended circuits. The CTR of the HCPL2533 HCPL2533 is 15% m inim um at I f = 8 mA. The HCPL-2533 HCPL-2533 ... OCR Scan
datasheet

5 pages,
1057.47 Kb

TRANSISTOR BH RW datasheet abstract
datasheet frame
Abstract: function compatible with 74LS05 Weight DIP14-P-300-2 DIP14-P-300-2.54 SOP14-P-300-1.27A : 0.96 g (typ.) : 0.18 g (typ. , (SOP) -65~150 Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in , (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = -40 ... Original
datasheet

7 pages,
219.88 Kb

74LS05 inverter TC74HC05AP/AF TC74HC05AP TC74HC05AF TC74HC05AP/AF abstract
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Datasheet Content (non pdf)

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C PD (*) Power Dissipation Capacitance 6.5 pF (*) C PD is defined as the value of the IC's internal COMPATIBLE WITH 54/74LS05 The M54/74HC05 M54/74HC05 M54/74HC05 M54/74HC05 is a high speed CMOS HEX OPEN DRAIN INVERTER fabricated in silicon gate C 2 MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages includ- ing buffer output, which enables consequences of use of such information nor for any infringement of patents or other rights of third parties
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1883-v2.htm
STMicroelectronics 14/06/1999 6.97 Kb HTM 1883-v2.htm
Dissipation Capacitance 6.5 pF (*) C PD is defined as the value of the IC's internal equivalent COMPATIBLE WITH 54/74LS05 The M54/74HC05 M54/74HC05 M54/74HC05 M54/74HC05 is a high speed CMOS HEX OPEN DRAIN INVERTER fabricated in silicon gate C 2 MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages includ- ing buffer output Microelectronics assumes no responsability for the consequences of use of such information nor for any
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1883.htm
STMicroelectronics 20/10/2000 9.28 Kb HTM 1883.htm
Dissipation Capacitance 6.5 pF (*) C PD is defined as the value of the IC's internal equivalent FUNCTION COMPATIBLE WITH 54/74LS05 The M54/74HC05 M54/74HC05 M54/74HC05 M54/74HC05 is a high speed CMOS HEX OPEN DRAIN INVERTER fabricated in silicon gate C 2 MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages includ- no responsability for the consequences of use of such information nor for any infringement of
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1883-v3.htm
STMicroelectronics 25/05/2000 8.79 Kb HTM 1883-v3.htm
C PD (*) Power Dissipation Capacitance 6.5 pF (*) C PD is defined as the value of the IC's internal COMPATIBLE WITH 54/74LS05 The M54/74HC05 M54/74HC05 M54/74HC05 M54/74HC05 is a high speed CMOS HEX OPEN DRAIN INVERTER fabricated in silicon gate C 2 MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages includ- ing buffer output, which enables consequences of use of such information nor for any infringement of patents or other rights of third parties
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/1883-v1.htm
STMicroelectronics 02/04/1999 7.01 Kb HTM 1883-v1.htm
* Library of 74LS Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights Reserved. * * * $Revision: 1.4 $ * $Author: RPEREZ $ * $Date: 17 Apr 1998 09:57:46 $ * * *$ *- tphlty=10ns tphlmx=15ns + ) *$ *- * 74LS05 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS05 params: MNTYMXDLY=0 IO_LEVEL=0 * Note: In this IC, there are 2 inverting, & 2 non-inverting delay gates
www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74ls.lib
Spice Models 29/07/2012 571.07 Kb LIB 74ls.lib
* Library of 74LS Family Digital Models * * Copyright Cadence Design Systems, Inc. 2002 All Rights Reserved. * * * $Revision: 1.5 $ * $Author: HIRASUNA $ * $Date: 11 May 2000 13:26:32 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *- * 74LS05 Hex interface and model names * .subckt 74LS05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params params: MNTYMXDLY=0 IO_LEVEL=0 * Note: In this IC, there are 2 inverting, & 2 non-inverting delay gates
www.datasheetarchive.com/files/spicemodels/misc/74ls.lib
Spice Models 19/12/2001 571.09 Kb LIB 74ls.lib
No abstract text available
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Spice Models 29/07/2012 425.7 Kb ZIP tdliblist.zip