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DSP56800+16-bit+Digital+Signal+Processor+Family+M

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: the DSP56800 16-bit DSP core. This core is a generalpurpose central processing unit (CPU), designed , PLL Data 16-Bit DSP CPU Core Debug Port JTAG I/O AA0012 Figure 1-1 DSP56800-Based DSP , programmable 16-bit CMOS digital signal processor that consists of a 16-bit data arithmetic logic unit (ALU), a 16-bit address generation unit (AGU), a program decoder, On-Chip Emulation (OnCE), associated , cycle 16 x 16-bit parallel multiply-accumulator · Two 36-bit accumulators including extension bits · Motorola
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AA0005 PROCESS CONTROL TIMER BASED TOPICS addressing modes of dsp processors Parallel FIR Filter
Abstract: core architecture is a 16-bit multiple-bus processor designed for efficient real-time digital signal , Switch External Data Bus Switch Program Controller Data ALU 16 x 16 + 36 36-Bit Mac Three 16-Bit , Address DSP 16-Bit Core PLL Program RAM/ROM Expansion Data Peripheral Modules XDB2 , operations on data operands. It consists of the following: · Three 16-bit input registers (X0, Y0, and Y1 , Block Diagram · One data limiter · One 16-bit barrel shifter · One parallel (single cycle Motorola
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Abstract: reasons, most DSP applications used a DSP and a microcontroller. This paper presents a new 16-bit DSP , the DSP56800 16-bit fixed point DSP microcontroller Central Processing Unit (CPU) core. This core is , GPIO Address PLL 16-Bit DSP CPU Core Ext. Bus Interface Debug Port Data JTAG I/O , DSP56L811 16-bit Chip Architecture The first chip available in the DSP56800 family is the DSP56L811. In , DSP56800 Features ¥ DSP56800 core ¥ Phase Lock Loop (PLL) ¥ 1 K ´ 16-bit Program RAM ¥ Motorola
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008B 009F microprocessor architecture programming DSP56800WP1/D
Abstract: new 16-bit DSP architecture from Motorola that maintains the performance of the DSP, while adding , THE DSP56800 FAMILY The DSP56800 family is a group of chips built around the DSP56800 16-bit fixed , Address PLL 16-Bit DSP CPU Core Ext. Bus Interface Debug Port Data JTAG I/O Figure , , digital control, and controller applications in need of more processing power. 4.1 DSP56L811 16-bit , DSP56800 core ¥ Phase Lock Loop (PLL) ¥ 1 K ´ 16-bit Program RAM ¥ Three General 16-bit Motorola
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realtime PID controller DSP56800 features dsp56800 instruction opcode microcontroller Motorola 20 pin motorola memory data book
Abstract: 16-bit Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Loading Pointer from , -bit pointer registers and the Modifier register, M01 · A secondary 16-bit offset register to further , . A compatibility issue can arise due to the 16-bit width of the DSP56800's AGU registers, address , DSP56800 Result (16-bit AGU Arithmetic) DSP56800E Result (24-bit AGU Arithmetic) Comments , effect on 16-bit AGU registers). Nevertheless, most code written in this matter is covered by special Freescale Semiconductor
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56800E FreescaleDSP56800 DSP56800ERG
Abstract: . Description Test a 36-bit accumulator Test a 16-bit register or memory location1 These instructions do , . BFTSTH and BFTSTL can test any field of the bits within a 16-bit word. BFSET, BFCLR, and BFCHG can test any field of the bits within a 16-bit word and then set, clear, or invert bits in this word , no-overhead looping. The last address of the DO loop is specified as a 16-bit absolute address. No locations , Allows multiplication result to be inverted if desired Fractional multiplication, 16-bit result Motorola
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001C C00F CA79
Abstract: Introduction 1.1 INTRODUCTION This manual describes the DSP56L811 16-bit digital signal processor (DSP , uses an efficient MPU-style, general-purpose, 16-bit DSP core, program and data memories, and support , Data ALU 16 x 16 + 36 36-Bit Mac Three 16-Bit Input Registers Two 36-Bit Accumulators MODA/IRQA , Clock Generator On-Chip Expansion Area X Memory RAM/ROM Expansion Address 16-bit , interface (SSI) port for codec support, three 16-bit general purpose timer/event counters, real-time and Motorola
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DSP56800FAM/AD DSP568L11/D A14-A0 AA0127
Abstract: ALU contains the following: · Three 16-bit input registers (X0, Y0, and Y1) · Two 32 , shifter (AS) · One data limiter · One 16-bit barrel shifter · One parallel (single cycle, non-pipelined , Overview and Architecture · Arithmetic and logical shifts · Rotates · Multi-bit shifts on 16-bit , of the data ALU are: · Three 16-bit input registers (X0, Y0, and Y1) · Two 32-bit accumulator , ) · One data limiter · One 16-bit barrel shifter · One parallel (single cycle, non-pipelined Motorola
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8000-Maximum AA0034 AA0035 ARITHMETIC3-15 AA0049 XX0100 011XXX 1110XX XX0101
Abstract: parallel reads) Description: Multiply the two signed 16-bit source operands (S1 and S2), and store the , are performed or when D is the 16-bit X0, Y1, or Y0. Usage: This instruction is used for , Multiplication on page 3-23). When the destination is a 16-bit register, this instruction is useful only for , 4000 Y1 F456 Y1 F456 Explanation of Example: Prior to execution, the 16-bit X0 register contains the value $4000 (0.5), the 16-bit Y1 register contains the value $F456 (-0.0911255), and the 36 Motorola
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A988 FE8B SR-0005
Abstract: Motorola's 16-bit DSP56800 Family of digital signal processors. It maintains compatibility with the , architecture represents the next step in the evolution of Motorola's 16-bit DSP56800 Family of digital signal , ." 1.2 References and Tools This application note refers to the DSP56800E 16-Bit Digital Signal , application note. The following documents provide necessary information on these topics: · DSP56800 16-Bit , application was tested and developed using a 16-bit address model for program and data memory space. Although Motorola
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DSP56824 motor mcps AN2095/D
Abstract: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. DSP56800 16-Bit Digital Signal , from an Accumulator. . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.4 Using 16-Bit Results of , 36-Bit Accumulator to 16-Bit Portion . . . . . . . . . . . . . . . .3-13 3.3 Fractional and Integer , -Bit Destinations - CC Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.6.5 16-Bit , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.2.2 General 16-Bit Shifts . . Freescale Semiconductor
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ic nn 5198 k b0835 b1151 -y audio amplifier book B1151 Y LMC 324 DSP56800FM/D
Abstract: Product Preview 16-BIT DIGITAL SIGNAL PROCESSOR The DSP56L812 is a member of the DSP56800 core-based , 16 RAM PAB 16-bit DSP56800 Core Address Generation Unit XAB1 XAB2 JTAG/ OnCETM , Data ALU 16 x 16 + 36 36-bit MAC Three 16-bit Input Registers Two 36-bit Accumulators 3 Bus , Digital Signal Processing Core ­ Efficient 16-bit DSP56800 core ­ Up to 20 million instructions per second (MIPS) at 40 MHz ­ Single-cycle 16 x 16-bit parallel multiply-accumulator ­ Two Motorola
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4 bit barrel shifter circuit DSP56800 manual DSP56812 PROCESSOR POWER DISTRIBUTION DIAGRAM DSP56L812P/D
Abstract: result Set if a carry (or borrow) occurs from bit 35 of A or B result See 16-bit Destinations on page , :(R0)+,Y0 Before Execution X:(R3)+,X0 ; 16-bit add, update Y0,X0,R0,R3 After Execution 0 , accumulator contains the value $0:0100:0000. The ADD instruction automatically appends the 16-bit value in , the result to the 36-bit A accumulator. Thus, 16-bit operands are always added to the MSP of A or B (A1 or B1), with the result correctly extending into the extension register (A2 or B2). 16-bit Motorola
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00FF A-31 MR1211
Abstract: DSP56800 16-bit Digital Signal Processor Family Manual Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598 TABLE OF CONTENTS , . . . 3-9 3.2.2.3 Converting from 36-bit Accumulator to 16-bit Portion 3-10 3.2.3 , . . . . . . . 3-34 3.4.5 16-bit Destinations . . . . . . . . . . . . . . . . . . . . . . . . . . . , DSP56800 Family Manual Table of Contents 8.3.2 General 16-bit Shifts . . . . . . . . . . . . . . . Motorola
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audio equalizer national audio handbook 015m01 MOTOROLA Cross Reference Search 96002 JVC receiver a88 de ec net DSP56800FM/AD
Abstract: 56824ADS 56F805ADS 56F803ADS 56L811ADS 56801ADS 56807ADS 56826ADS 56827ADS · One open 16-bit ISA Metrowerks
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DSP-263 dsp-104 ocdemon DSP-35 JG10 56827EVM CWDSP56800TM/D M56800E
Abstract: DSP56F803 16-bit Digital Signal Processor · · · · Up to 40 MIPS at 80 MHz core frequency DSP and MCU , supports both DSP and controller functions: MAC, bit manipulation unit, 19 addressing modes 32K × 16-bit words Program Flash 512 × 16-bit words Program RAM 4K × 16-bit words Data Flash 2K × 16-bit words Data RAM 2K × 16-bit words BootFLASH · · · · · · · · · · · Up to 64K × 16-bit words external Program and , Address Generation Unit Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36 Motorola
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DSP56F803PB/D 3-20-1M
Abstract: Instruction Words BFTSTH #xxxx,X: ; 16-bit mask allowed JCS label ; 19-bit jump address allowed ; JRCLR Operation ; Emulated in 5 Icyc (4 Icyc if false), 4 Instruction Words BFTSTL #xxxx,X: ; 16-bit , Icyc if false), 3 Instruction Words BFTSTL #xxxx,X: ; 16-bit mask allowed BCC label ; 7 , operations allow jumps to anywhere in the 512K word program address space and can specify a 16-bit mask. The , : ; 16-bit mask allowed JCS label ; 19-bit jump address allowed 8-4 DSP56800 Family Motorola
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ASR12 ASR16 DSP56100 sp37 32-BIT
Abstract: DSP56F805 16-bit Digital Signal Processor · Up to 40 MIPS at 80 MHz core frequency · · DSP and MCU functionality in a unified, C-efficient architecture Up to 64K × 16-bit words each of external , 31.5K × 16-bit words Program Flash · 512 × 16-bit words Program RAM · 4K × 16-bit words Data Flash · Up to four General Purpose Quad Timers · 2K × 16-bit words Data RAM · JTAG/OnCETM port for debugging · 2K × 16-bit words BootFLASH · 14 Dedicated and 18 Shared GPIO Motorola
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DSP56F805FV80 DSP56F807 ELEVATOR LOGIC CONTROL PLC MIPS 16-bit bus architecture DSP56F805PB/D
Abstract: DSP56F805 16-bit Digital Signal Processor · · · · Up to 40 MIPS at 80 MHz core frequency DSP and MCU , supports both DSP and controller functions: MAC, bit manipulation unit, 19 addressing modes 32 K × 16-bit words Program Flash 512 × 16-bit words Program RAM 4K × 16-bit words Data Flash 2K × 16-bit words Data RAM 2K × 16-bit words BootFLASH · · · · · · · · · · · Up to 64K × 16-bit words external Program and , 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit 4 2 4 Motorola
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Abstract: Advance Information 16-BIT DIGITAL SIGNAL PROCESSOR 16 to 32 GPIO lines 4 8 8 4 4 in , PLL Interrupt GPIO (SPI0) (SPI1) (SSI) or or GPIO GPIO or GPIO or GPIO GPIO Clock Gen. 16-bit , Controller Data ALU 16 ´ 16 + 36 ® 36-bit MAC Three 16-bit Input Registers Two 36-bit Accumulators , Features DSP56812 FEATURES Digital Signal Processing Core ¥ Efficient 16-bit DSP56800 family DSP , 16-bit parallel Multiplier-Accumulator (MAC) ¥ Two 36-bit accumulators including extension bits Motorola
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DSP56812P/D
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