NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: C410NF t592 29 31 33 3 M.4VITEB DL4 DL3 DL2 DL1 LED LED LED LED RR1 10K 1206 T12 ... | Original |
1 pages, |
VNI4140K DL2 DL1 1K 1206 SM15T39 TLP281-4 stat2 IN4 diode datasheet abstract |
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| Abstract: process DI8 32 DL10 s 33 2 DL2/LEN FEATURES 1 SM5 8 3 7 A F DL0/SDI DL1 , , DL0/SDI, DL1/SICK, DL2/LEN, DL3 to DL10, OE and RSTN. 3. Pins DO0 to DO11. AC Characteristics VDD , setting DL10 DL9 DL8 DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0 Delay length 0 , data input when PARA is LOW. 2 DL1/SICK Ip Delay length set parallel data bit DL1 (bit 1) when PARA is HIGH, and SICK shift clock when PARA is LOW. 3 DL2/LEN Ip Delay length set ... | Original |
8 pages, |
SM5837AF sick DL10 cmos para and or not SM5837AF abstract |
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| Abstract: parallel data filled, a DL2 M DL1 a LCD panel can be configured only with this product. Y78 , from DL1 pin. avoid floating. DL2 and DL3 should be set as either high or low to When SHL is , , DL2 and DL3 are input pins for LCD data. common mode, when SHL is low, DL0 is input pin and DL1 is , and DL1 Register functions as a 20*4-bit Unit Latch Register (Total of DL3 DL2 DL1 DL0 DL3 DL2 DL1 - DL0 Y7 Y6 Y5 Y4 Y3 Y2 When `FCS' is `LOW', it is ... | Original |
16 pages, |
DL2 DL1 COM239 SPLC206A SPLC206A datasheet IC 751 1124 PLC206A PLC206A abstract |
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| Abstract: DU3 12 DL0 13 DL1 14 DL2 15 DL3 Display Data Signal (Upper Half) H (ON , DU3 DU2 DU1 DU0 240 DOT DU3 DU2 DU1 DU0 DU3 DU2 DU1 DU0 241 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 480 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 NOTE: 1 . 2 means 1st row 2nd , CP2 DISP VDD VSS VEE DU0 OFF PIN # 9 10 11 12 13 14 15 SYMBOL DU1 DU2 DU3 DL0 DL1 DL2 DL3 X , DL2 480 . 638 INVALID 241 . 2 241 . 6 241 . 638 INVALID 242 . 2 242 . 638 ... | Original |
20 pages, |
240TH M60-04-30-114P M60-04-30-134P M61M73-04 M63M83-04 mitsumi modulator enc-87941 SHARP LM000106 CCFT SUPPLY lm000106 full color dot matrix 8 x 8 trf 640 a LM64P83 sharp lcd lm64p839 SHARP LM64P839 LM64P839 LM64P839 abstract |
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| Abstract: DU1 10 DU2 11 DU3 12 DL0 13 DL1 14 DL2 15 DL3 Display Data , DU3 DU2 DU1 DU0 DU3 DU2 DU1 DU0 241 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 480 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 NOTE: 1 . 2 means 1st row 2nd column dot. DU3 DU2 DU1 DU0 , VEE DU0 BEZEL BEZEL PIN # SIGNAL 9 10 11 12 13 14 15 DU1 DU2 DU3 DL0 DL1 DL2 , 241 . 1 241 . 5 241 . 637 INVALID 242 . 1 242 . 637 DL2 480 . 638 INVALID ... | Original |
19 pages, |
240TH M60-04-30-114P M60-04-30-134P M61M73-04 M63M83-04 mitsumi modulator mitsumi modulator enc-87941 lm000106 SHARP LM000106 CCFT SUPPLY LM64P89 LM64P89 abstract |
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| Abstract: DU2 DU1 DU0 DU3 DU2 DU1 DU0 241 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 480 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 NOTE: 1 . 2 means 1st row 2nd column dot. DU3 DU2 DU1 DU0 , 9 10 11 12 13 14 15 S CP1 CP2 OFF VDD VSS VEE DU0 DU1 DU2DU3 DL0 DL1 DL2 DL3 5004-13 , Supply for LCD () 8 DU0 9 DU1 10 DU2 11 DU3 12 DL0 13 DL1 14 DL2 15 DL3 Display Data Signal (Upper Half) H (ON), L (OFF) Display Data Signal (Lower ... | Original |
20 pages, |
trf 640 full color dot matrix 8 x 8 M60-04-30-114P M60-04-30-134P M61M73-04 M63M83-04 mitsumi modulator enc-87941 projector room wiring diagram SHARP LM000106 CCFT Inverter 240TH lm000106 LM64K83 SHARP LM000106 CCFT SUPPLY LM64K83 abstract |
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| Abstract: DU2 DU1 DU0 DU3 DU2 DU1 DU0 241 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 480 DOT DL3 DL2 DL1 DL0 DL3 DL2 DL1 DL0 NOTE: 1 . 2 means 1st row 2nd column dot. DU3 DU2 DU1 DU0 , OFF PIN # 9 10 11 12 13 14 15 SYMBOL DU1 DU2 DU3 DL0 DL1 DL2 DL3 2 Interface connector (15 , (OFF) 10 DU2 11 DU3 12 DL0 13 DL1 Display Data Signal (Lower Half) H (ON), L (OFF) 14 DL2 15 DL3 NOTES: 1. Connector used: 53261-1510 (MOLEX) Mating ... | Original |
19 pages, |
trf 640 full color dot matrix 8 x 8 LM64P12 SHARP LCD lm64p122 sharp lm64p SM02 BHR-03VS-1 SHARP LM000106 CCFT SUPPLY lm000106 LM64p122 LM64P122 LM64P122 abstract |
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| Abstract: Y77 Y78 Y79 DL1 DL2 DL3 DL0 DL1 DL2 scan direction SR1- SR2- , DL1 DL0 DL3 DL2 DL1 DL0 - Common signal shift direction A description , : Y80 DL0 Y79 DL1 Y78 DL2 Y77 DL3 Y76 DL0 Y75 DL1 Y73 Y74 DL2 DL3 Y8 DL0 Y7 DL1 Y6 Y5 DL3 Y4 DL0 Y2 Y3 DL1 DL2 When SPLC206A SPLC206A is in such mode , Shift Register Block. Lsat 2nd DL1 - -1st DL0 DL2 DL3 Y1 ... | Original |
15 pages, |
pin diagram for IC 1619 30 pin lcd 2216 COM239 SPLC206A 80-CHANNEL SPLC206A abstract |
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| Abstract: J-STD-020C J-STD-020C DL1 AC1 L / GND DC- / DL2 AC2 All Dimensions in mm TOP VIEW Ordering , Two Data Lines (DL1 & DL2, DL1 & DL3) CLL ¾ 3.5 7 pF VR = 0, f = 1.0MHz , Line Bus Transient Suppressor VBUS/VCC DL1 DL3 DL2 Ground Three Phase, Full-Wave Bridge ... | Original |
3 pages, |
DLPA006-7 DLPA006 transient suppressor spice model BRIDGE-RECTIFIER 61000-4 DLPA006 abstract |
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| Abstract: ¾ pF VR = 0, f = 1.0MHz Capacitance Between Two Data Lines (DL1 & DL2, DL1 & DL3) CLL , Line Bus Transient Suppressor VBUS/VCC DL1 DL3 DL2 Ground Three Phase, Full-Wave Bridge , Moisture Sensitivity: Level 1 per J-STD-020C J-STD-020C / / DL1 AC1 Terminals: Finish ¾ Matte Tin , VCC VCC / GND DC- / All Dimensions in mm DL2 AC2 TOP VIEW Ordering ... | Original |
4 pages, |
DLPA006-7 DLPA006 DLPA006 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| , double a2) { union double_long dl1, dl2; dl1.d = a1; dl2.d = a2; if (SIGND (dl1) && SIGND (dl2) { dl1.l.upper ^= SIGNBIT; dl2.l.upper ^= SIGNBIT; } if (dl1.l.upper < dl2.l.upper) return (-1); if (dl1.l.upper > dl2.l.upper) return (1); if (dl1.l.lower < dl2.l.lower) return (-1); if (dl1.l.lower > dl2.l.lower) return (1); return (0 double */ double _negdf2 (double a1) { union double_long dl1; dl1.d = a1; if (!dl1.l www.datasheetarchive.com/download/79262054-393174ZC/mplabc30v2_05.tgz |
Microchip | 09/11/2006 | 27045.95 Kb | TGZ | mplabc30v2_05.tgz |
| */ long _cmpdf2 (double a1, double a2) { register union double_long dl1, dl2; dl1.d = a1; dl2.d = a2; if (SIGND (dl1) && SIGND (dl2) { dl1.l.upper ^= SIGNBIT; dl2.l.upper ^= SIGNBIT; } if (dl1.l.upper < dl2.l.upper) return (-1); if (dl1.l.upper > dl2.l.upper) return (1); if (dl1.l.lower < dl2.l.lower) return (-1); if (dl1.l.lower > dl2.l.lower) return (fl1.f); } /* negate a double */ double _negdf2 (double a1) { register union double_long dl1 www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DL3 DL2 DL1 DL0 AL3 AL2 AL1 AL0 DL3.0=0: Normal Operation www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7052.htm |
STMicroelectronics | 20/10/2000 | 61.92 Kb | HTM | 7052.htm |
| Bit1 Bit0 R/W 1 0 1 1 0 1 0 DL3 DL2 DL1 DL0 AL3 AL2 AL11 AL0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7304-v1.htm |
STMicroelectronics | 30/10/2000 | 76.34 Kb | HTM | 7304-v1.htm |
| Bit2 Bit1 Bit0 R/W 1 0 1 1 0 1 0 DL3 DL2 DL1 DL0 AL3 AL2 AL11 AL0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7304.htm |
STMicroelectronics | 20/10/2000 | 79.26 Kb | HTM | 7304.htm |
| 20 A25 10 18 0.5 DL1A A22 A24 DA DL2A A25 A22 DA * *GAIN STAGE B GAB B21 20 B35 20 10M 18 0.5 EL2B 20 B25 10 18 0.5 DL1B B22 B24 DA DL2B B25 B22 DA VOLTAGE LIMITING DL1 22 34 DA VOFF1 34 33 5M HCOMP1 32 33 VIS1 182 EP1 32 31 23 25 1 EL1 31 20 10 18 0.5 * DL2 37 22 DA VOFF2 36 37 5M HCOMP2 35 36 VIS1 182 EP2 35 38 23 25 1 EL2 20 38 10 18 www.datasheetarchive.com/files/maxim/modeling-simulation/spice/current-sense-amps/macro/max4195.fam |
Maxim | 04/10/2012 | 4.56 Kb | FAM | max4195.fam |
| EL1A A24 20 10 18 0.5 EL2A 20 A25 10 18 0.5 DL1A A22 A24 DA DL2A A25 A22 DA * *GAIN STAGE *VOLTAGE LIMITS EL1B B24 20 10 18 0.5 EL2B 20 B25 10 18 0.5 DL1B B22 B24 DA DL2B B25 B22 DA VOLTAGE LIMITING DL1 22 34 DA VOFF1 34 33 5M HCOMP1 32 33 VIS1 182 EP1 32 31 23 25 1 EL1 31 20 10 18 0.5 * DL2 37 22 DA VOFF2 36 37 5M HCOMP2 35 36 VIS1 182 EP2 35 38 23 25 1 EL2 20 38 10 18 www.datasheetarchive.com/files/maxim/modeling-simulation/spice/current-sense-amps/macro/max4196.fam |
Maxim | 04/10/2012 | 4.59 Kb | FAM | max4196.fam |
| 24 20 10 18 0.5 EL2A 20 A25 10 18 0.5 DL1A A22 A24 DA DL2A A25 A22 DA * *GAIN STAGE B LIMITS EL1B B24 20 10 18 0.5 EL2B 20 B25 10 18 0.5 DL1B B22 B24 DA DL2B B25 B22 DA VOLTAGE LIMITING DL1 22 34 DA VOFF1 34 33 5M HCOMP1 32 33 VIS1 182 EP1 32 31 23 25 1 EL1 31 20 10 18 0.5 * DL2 37 22 DA VOFF2 36 37 5M HCOMP2 35 36 VIS1 182 EP2 35 38 23 25 1 EL2 20 38 10 18 www.datasheetarchive.com/files/maxim/modeling-simulation/spice/current-sense-amps/macro/max4197.fam |
Maxim | 04/10/2012 | 4.59 Kb | FAM | max4197.fam |
| *VOLTAGE LIMITS EL1A A24 20 10 18 0.5 EL2A 20 A25 10 18 0.5 DL1A A22 A24 DA DL2A A25 A22 DA B24 20 10 18 0.5 EL2B 20 B25 10 18 0.5 DL1B B22 B24 DA DL2B B25 B22 DA 20 45 DB VIS3 46 20 0V FSUP3 10 18 VIS3 1 * *OUTPUT VOLTAGE LIMITING DL1 22 34 DA VOFF1 34 33 5M HCOMP1 32 33 VIS1 182 EP1 32 31 23 25 1 EL1 31 20 10 18 0.5 * DL2 www.datasheetarchive.com/files/maxim/modeling-simulation/spice/current-sense-amps/macro/max4194.fam |
Maxim | 04/10/2012 | 4.42 Kb | FAM | max4194.fam |
| *VOLTAGE LIMITS EL1A A24 20 10 18 0.5 EL2A 20 A25 10 18 0.5 DL1A A22 A24 DA DL2A A25 A22 DA B24 20 10 18 0.5 EL2B 20 B25 10 18 0.5 DL1B B22 B24 DA DL2B B25 B22 DA 20 45 DB VIS3 46 20 0V FSUP3 10 18 VIS3 1 * *OUTPUT VOLTAGE LIMITING DL1 22 34 DA VOFF1 34 33 5M HCOMP1 32 33 VIS1 182 EP1 32 31 23 25 1 EL1 31 20 10 18 0.5 * DL2 www.datasheetarchive.com/files/maxim/modeling-simulation/spice/current-sense-amps/orcad/max4194.lib |
Maxim | 01/04/2004 | 4.35 Kb | LIB | max4194.lib |