NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 2-port PHY. To minimize the width of the interface, SATALite uses double data rate (DDR) transmission , SiI 3012 SATALink 2-Port PHY The SiI 3012 is a dual-channel Serial ATA (SATA) PHY featuring , full 1.5 Gbps rate. The 2-port SiI 3012 provides a cost-effective, high-performance SATA PHY solution ideal for storage solutions that integrate the Serial ATA Link and Transport layers in a control ASIC interfacing to an external PHY. A member of Silicon Image's SATALinkTM family of Serial ATA products, the ... | Original |
2 pages, |
pioneer pll sata phy SiI 3012 DDR PHY ASIC datasheet abstract |
|
|||
| Abstract: available for immediate design-ins. · RapidChip Platform ASIC Market applications for the PHY core , RapidChip Platform ASIC DDR-I SDRAM DDR-1 PHY-Core DDR-1 Controller (CW761030 CW761030) Address/CMD , · The DDR-1 PHY core with the DDR-1 controller core (CW761030 CW761030) together provide a complete , a complete DDR-1 SDRAM interface solution, enabling significant reductions in ASIC development , Office Locations www.lsilogic.com/contacts Figure 2. LSI Logic's RapidChip DDR-1 SDRAM PHY core ... | Original |
2 pages, |
g12 DDR lsi CW761041 CW000722 LSI Rapidchip DDR PHY ASIC ddr phy CW761041 abstract |
|
|||
| Abstract: Comparators SSTL 3.3V Regulators • Op-Amps LVDS LVPECL • Power-on reset DDRII PHY MDDR PHY • DDR PHY , The company offers value-added ASIC services that include taking designs from RTL or Gate Level , party foundries. The ChipX Advantage â- ASIC design experience since 1989 • 100% first-pass Standard , > 550MHz ChipX Offers Analog and Mixed-Signal ASIC Excellence ChipX, Inc. is a leading Analog and Mixed-Signal ASIC company with unique technology that allows you to reduce the cost, development cycle and risk ... | OCR Scan |
4 pages, |
CX6100 CX5000 CX3000 cx-5900 BA22 BA12 ARM926EJ DDR PHY ASIC datasheet abstract |
|
|||
| Abstract: ), LVDS (up to 640 Mbps), PCI, PCI-X, XOSC; DDR, DDRII including PHY and Controller < Silicon-proven DDR , Product Brief CX6100 CX6100 Structured ASIC with PCI Express Product Description The CX6100 CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI Express with the well-proven , , silicon-proven PCI Express PHY, in combination with the ChipX synthesizable processors and PCI Express endpoint , testing. The CX6100 CX6100 product family builds on four generations of ChipX Structured ASIC products (see ... | Original |
2 pages, |
CX6119 cx6112 CX6104 CHIPX DDR PHY ASIC CX6100 CX6100 abstract |
|
|||
| Abstract: Product Brief CX6200 CX6200 Structured ASIC with USB 2.0 PHY Product Description The CX6200 CX6200 product , 0211-6K-070-D 0211-6K-070-D 1 of 2 CX6200 CX6200 Structured ASIC with USB 2.0 PHY ChipX Product Brief Applications The , ASIC architecture to provide industry leading performance using the UMC eight-metal high-speed 0.13- u , , tested, and shipped in just 4 to 5 weeks. The built-in, silicon-proven USB 2.0 HS OTG PHY, in , /O1 1 GHz USB 2.0 OTG PHY Part Number CX6210 CX6210 140 324 (36) 120 4 P 56 QFN ... | Original |
2 pages, |
Structured CHIPX PLL in RTL LCD 1602 CX6214 CX6210 DDR PHY ASIC 88 qfn CX6212 QFN-88 CX6200 CX6211 CX6215 CX6216 CX6220 CX6200 abstract |
|
|||
| Abstract: to 640 Mbps), PCI, PCI-X, XOSC; DDR, DDRII including PHY and Controller Commercial grade, extended , Product Brief CX6100 CX6100 Structured ASIC with PCI Express Product Description The CX6100 CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI Express with the well-proven , , silicon-proven PCI Express PHY, in combination with the ChipX synthesizable processors and PCI Express endpoint , testing. The CX6100 CX6100 product family builds on four generations of ChipX Structured ASIC products (see ... | Original |
2 pages, |
TCA 290 DDR PHY ASIC CX6100 CHIPX CX6100 abstract |
|
|||
| Abstract: CMOS ASIC s e mi con duc t or http://www.semicon.toshiba.co.jp/ 2006-9 ASIC ASIC IC 3 C O N T E N T S ASIC 3 ASIC 4 5 ASIC 8 UniversalArrayTM QTAT Solution for SoC Designs 11 SoC EDA 12 16 18 2 ASIC ASIC ASIC ASIC ASIC ASIC 5V TC320 TC320 65nm TC300 TC300 90nm ... | Original |
18 pages, |
TX49 P-FBGA 169 rsf-11 SoC hdd TC190 TC200 TC200E TC223 TC260 TC280 TC300C toshiba tx99 Celaro TOSHIBA TC203 LSI CMOS GATE ARRAY datasheet abstract |
|
|||
| Abstract: GigaBlaze SerDes (3.2Gb/s) 8 8 HyperPHY SerDes (832Gb/s) 40 DDR PHY bits (167 MHz p2p , RapidChip Foundation Platform ASIC The Cornerstone of Platform ASICs TM OVERVIEW FEATURES High performance Platform ASIC The RapidChip Foundation Platform ASIC IP-rich slices are designed for a broad range of applications. The RapidChipTM Foundation Platform ASIC family delivers the , ASICs. solution including: · Up to 2.8M usable ASIC gates · Up to 2.2Mbit high density on-chip SRAM ... | Original |
2 pages, |
ARM926 LSI Rapidchip RC1812 RC1832 RC1840 RC1845 RC1847 RC1880 serdes LSI DDR PHY ASIC transistor P2P RC1832 abstract |
|
|||
| Abstract: ASIC family designed for storage system providers that want flexibility in their storage controller , providers. Available to OEMs only PCI-X or PCI-Express Interfaces  uses the same ASIC for either , Inter- Core Interrupt Intel XScale Processor 0 512K L 2 Cache FSENG 0 PHY 0 FSENG 1 PHY 1 FSENG 2 PHY 2 FSENG 3 PHY 3 FSENG 4 PHY 4 FSENG 5 PHY 5 FSENG 6 PHY 6 FSENG 7 PHY 7 SAS/SATA 128 - Bit North XSI Bus Multi- Port SRAM Memory ... | Original |
2 pages, |
Emulex SAS controller chip datasheet abstract |
|
|||
| Abstract: Data Sheet CX6200 CX6200 Structured ASIC with USB 2.0 HS OTG PHY Product Description The CX6200 CX6200 , 0210-6K-080-E 0210-6K-080-E 1 of 6 CX6200 CX6200 Structured ASIC with USB 2.0 HS OTG PHY ChipX Data Sheet Applications , CX6200 CX6200 Structured ASIC with USB 2.0 HS OTG PHY Consumer Markets Set-top boxes Video cameras Digital , ASIC with USB 2.0 HS OTG PHY ChipX Data Sheet Figure 1 USB T&MT Board Core Fabric The CX6200 CX6200 , 0210-6K-080-E 0210-6K-080-E October 26, 2009 CX6200 CX6200 Structured ASIC with USB 2.0 HS OTG PHY ChipX Data Sheet ... | Original |
6 pages, |
CHIPX 1602 LCD data sheet DDR PHY ASIC CX6212 88 qfn QFN-88 CX6200 CX6200 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| stream data from DDR-SDRAM to OC-192 OC-192 OC-192 OC-192 serializers. Article PDF 285 KB YouÂ'd like to use DDR-SDRAM as the storage medium for OC-192 OC-192 OC-192 OC-192 test pattern generation to dramatically signals donÂ't meet the timing requirements. Your project budget canÂ't afford an ASIC. How can you get standard architecture used to design a streaming data interface between DDR-SDRAM and OC-192 OC-192 OC-192 OC-192 serializers available as directly instantiated elements (the DDR flip-flop), Xilinx CORE Generator™ modules (MUX x www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_50/xc_taodigital50.htm |
Xilinx | 19/07/2004 | 17.19 Kb | HTM | xc_taodigital50.htm |
| 2.5 volt supply pad 2.5V ASIC core power supply M3 VDD2_5_7 P 2.5 volt supply pad 2.5V ASIC core power supply L3 VDD2_5_6 P 2.5 volt supply pad 2.5V ASIC core power supply K3 VDD2_5_5 P 2.5 volt supply pad 2.5V ASIC core power supply C10 VDD2_5_4 P 2.5 volt supply pad 2.5V ASIC core power supply C11 VDD2_5_3 P 2.5 volt supply pad 2.5V ASIC core power supply C12 VDD2_5_2 P 2.5 volt supply pad 2.5V ASIC core power supply D12 VDD2_5_1 P 2.5 volt supply pad 2.5V ASIC core power supply M4 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7440.htm |
STMicroelectronics | 30/11/2000 | 66.66 Kb | HTM | 7440.htm |
| -speed buses may be dictated by the needs of a specific application. For example, a 266 MHz, 64-bit DDR RAM www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_49/xc_overview-si49.htm |
Xilinx | 26/04/2004 | 16.03 Kb | HTM | xc_overview-si49.htm |
| Gigabit Ethernet standard. The core can interface to an off-chip PHY using the coreÂ's gigabit media DDR-RAM to buffer data on a per-channel basis. The Fibre Channel reference design demonstrates www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_50/xc_gfp50.htm |
Xilinx | 19/07/2004 | 22.48 Kb | HTM | xc_gfp50.htm |
| LVDS pairs, and a standard 50-pin 0.1-inch header for custom expansion. Memory includes Micron™ DDR www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_49/xc_avnet-sma49.htm |
Xilinx | 26/04/2004 | 17.85 Kb | HTM | xc_avnet-sma49.htm |
| will use double data rate (DDR) or Quad Data Rate (QDR™) memory devices in your next high your DDR/QDR memory interface design, export the information as constraint data into ISE, and www.datasheetarchive.com/files/xilinx/files/xcell journal articles/xcell_50/xc_forte-qdr50.htm |
Xilinx | 19/07/2004 | 25.38 Kb | HTM | xc_forte-qdr50.htm |