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Part Manufacturer Description Datasheet BUY
PMP2388 Texas Instruments Flyback, Buck for DSL visit Texas Instruments
PMP2388.3 Texas Instruments Flyback, Buck for DSL (50V @ 50mA) visit Texas Instruments
PMP2388.5 Texas Instruments Flyback, Buck for DSL (1.2V @ 350mA) visit Texas Instruments
PMP2388.4 Texas Instruments Flyback, Buck for DSL (3.3V @ 440mA) visit Texas Instruments
ISL1532IRZ Intersil Corporation Dual Channel Differential DSL Line Driver; QFN24, TSSOP20; Temp Range: -40° to 85°C visit Intersil Buy
ISL1533IVEZ-T13 Intersil Corporation Dual Channel Differential DSL Line Driver; QFN24, TSSOP20; Temp Range: -40° to 85°C visit Intersil Buy

D50 DSL

Catalog Datasheet MFG & Type PDF Document Tags

DSLAM d50

Abstract: nokia 1200 facilitate integration of the D50 with digital loop carrier systems, providing DSL service deep into the , configured to support remote DSL nodes using the remotely located Line Card Shelf or D50 Remote Access , , and voice over DSL Integrated Access Devices (VoDSL IADs) and seamlessly interoperate with our D50 , ." The D50 provides a seamless solution that operates end-to-end. A Multi-Service DSL Solution to , just at the beginning of rapidly expanding market opportunity. The D50 ATM/DSL network solution
Nokia
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Z86E3012PSC

Abstract: EPROM 2764a 45V 5.0V 5TpC 5TpC Reg. SMR - D5=0 No Delay 45V 5.0V 5TpC 5TpC Reg. SM -D5=1 with Delay 11 , Register (F8H: Write Only) R252 FLAGS EE Del DSl D4 D31 D2I D1 H EE D7ID6 D5 D4 03 D2 D1 DO
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OCR Scan

M61511FP

Abstract: 80P6N AC ASW ATT ATT u-com Interface 5.1ch Digital DL DSL DC DR DSR DSW AOUT DATA , ) D00 D10 D20 D30 D40 D50 D60 D70 D80 Master Volume Lch Refer Setting Code
Mitsubishi
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Abstract: logic â'˜ O '. 12 MHz Min Max 12 12 ns ns Reg. SMR - D5=0 No Delay Reg. SMR - D5=1 with , TBD mS ms mS mS mS mS Reg. SMR - D5=0 Reg. WDTMR witn internal RC D0 = 0 D 1=0 DO = 1 , dst â'" dst + 1 (Note 1) C Z S V O H IR * â'¢ * 0 * dst â'" dsl + src + C , R dst â'" dst - 1 IR DECW dsl dst * - dst - 1 40 41 * * 00 01 â'" * RR -
OCR Scan

AF5A

Abstract: MT90222/223/224 4/8/16 Port IMA/TC PHY Device Data Sheet Features IMA · Up to 16 T1, E1, J1, DSL , General · Supports unframed serial streams up to 10 Mb/s per T1/E1 or DSL link · Single chip ATM IMA & TC processor · Versatile TDM interface for most popular T1 or E1 framers and DSL chipsets 1. MT90222 , Processors (1 per group) TDM Ring Control S/P T1/E1/DSL Utopia I/F CTRL Cell Delineator CD Circuits (1 per link) T1/E1/DSL P/S Tx Utopia FIFo Transmission Convergence TDM Ring Control
Zarlink Semiconductor
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AF5A DS5664 MT90222AG MT90223AG MT90224AG AF-PHY-0086 AF-PHY-0130

XPC850DSLCZT50BU

Abstract: b29b Communications Ports Processor (CP) and Program ROM - UTOPIA (850SR & DSL) Timer Communications , equations should be applied to each one of the above parameters: For minima: FFACTOR x 1000 (D50 - 20 x FFACTOR) D= + F For maxima: FFACTOR x 1000 (D50 -20 x FFACTOR) D= + F 1ns(CAP LOAD - 50) / 10 , in MHz D50 is the parameter value defined for 50 MHz CAP LOAD is the capacitance load on the signal
Freescale Semiconductor
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MPC850EC MPC850 MPC860 XPC850DSLCZT50BU b29b MF-102 MPC850 manual XPC850DECZT50BU

AN1231

Abstract: (850SR & DSL) Timer SCC2 TDMa SCC3 SMC1 SMC2 USB SPI I2C Time Slot Assigner , : For minima: FFACTOR x 1000 (D50 - 20 x FFACTOR) D= + F For maxima: FFACTOR x 1000 (D50 -20 x FFACTOR , F is the operation frequency in MHz D50 is the parameter value defined for 50 MHz CAP LOAD is the
Freescale Semiconductor
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AN1231 MPC850DSLCZQ5 MPC850DSLCZQ50BU 200KB 250KB

MPC850

Abstract: MPC850DE Communications Ports Processor (CP) and Program ROM - UTOPIA (850SR & DSL) Timer Communications , equations should be applied to each one of the above parameters: For minima: FFACTOR x 1000 (D50 - 20 x FFACTOR) D= + F For maxima: FFACTOR x 1000 (D50 -20 x FFACTOR) D= + F 1ns(CAP LOAD - 50) / 10 , in MHz D50 is the parameter value defined for 50 MHz CAP LOAD is the capacitance load on the signal
Freescale Semiconductor
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MPC850DE MPC850DSL

7404 signetics

Abstract: GBA ST1 ) ) ) ; /ROMOHI = ( / DSl+{/ , *//MASEL) ; /R0M3HI = / {/(/DSl*/(A16*A17*/A18*//MASEL) ) ) ; /R0M4L0 « (/DSO+/(A16*/A17*A18*//MASEL , D50 IN 21- 1 22- 1 23- 1 2A - 1 25-1 26-1 27-1 * 28- 1 * 29- 1 * 30- 1 * * 31- 1 * 32- 1 * 33
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OCR Scan
7404 signetics GBA ST1 mca ibm ibm hardware mca VSBC-2 PLHS501 ODATO-ODAT15 D0-D15

Z86e4012

Abstract: Z86E40 configured as a Low EMI Port by resetting this bit (D5=0) or configured as a Standard Port by setting this
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OCR Scan
Z86E40 86E4012 Z86e4012 SXGR T-49-19-07 286E40 Z86E4012PSC Z86E4012VSC Z86E4012FSC

734 B34

Abstract: XPC850DECZT66BU ROM Communications Processor Module and 2 Virtual IDMA Channels UTOPIA (850SR & DSL , 1000 (D50 - 20 x FFACTOR) D= + F For maxima: Freescale Semiconductor, Inc. FFACTOR x 1000 (D50 -20 x FFACTOR) 1ns(CAP LOAD - 50) / 10 + + D= F where: D is the parameter value to the frequency required in ns F is the operation frequency in MHz D50 is the parameter value defined for 50 MHz
Motorola
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734 B34 XPC850DECZT66BU MPC850ABEC/D
Abstract: (850SR & DSL) Timer SCC2 TDMa SCC3 SMC1 SMC2 USB SPI I2C Time Slot Assigner , : For minima: FFACTOR x 1000 (D50 - 20 x FFACTOR) D= + F For maxima: FFACTOR x 1000 (D50 -20 x FFACTOR , F is the operation frequency in MHz D50 is the parameter value defined for 50 MHz CAP LOAD is the Freescale Semiconductor
Original
MPC850CZQ50BUR2

851 a12 b1a

Abstract: QMC for MPC850 and 2 Virtual IDMA Channels UTOPIA (850SR & DSL) Timer Peripheral Bus SCC2 TDMa SCC3 , 1000 (D50 - 20 x FFACTOR) D= + F For maxima: FFACTOR x 1000 (D50 -20 x FFACTOR) 1ns(CAP LOAD - 50 , frequency in MHz D50 is the parameter value defined for 50 MHz CAP LOAD is the capacitance load on the
Motorola
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851 a12 b1a QMC for MPC850 851 A15 B1B
Abstract: [11 [1] [1.21 [1.2] [1.31 [1.3] [1.2] [1.2] Reg. SMR - D5=0 No Delay Reg. SMR - D5=1 with -
OCR Scan
Z86C3 Z86C30
Abstract: ) Pulse duration, DS low (read) Setup time, S A D (7 -0 ) valid to D S t Enable time, DS-l to S A D (7 -0 ) driving Delay time, DS-l to S A D (7 -0 ) valid Hold time, S A (8 -0 ), CS, R/W valid after D S t Hold -
OCR Scan
TL16PC564A SLLS172B TL16C550 256-B TL16C450

TDA 9370

Abstract: DC-2583-00 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D5B D59 D60 AN19 AM20 AL2Ì AM22 AP20 , AB23 AB24 AB25 AB26 TERMINAL NAME D52 Vss Vss D53 A24 VSS VSS VSS D49 D50 D51 Vd d A25 A26 A27 v dd , D37 D38 D39 D40 D41 D42 D43 044 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 055 D56 D57 D58 D59 D60 NO
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OCR Scan
DC-2583-00 TDA 9370 TDA 9370 with pin no 64 5401 DM mark code Ls5 tda 2022 Z86C94

ct20j

Abstract: 0x00009f empty (WR71 D5=0), the system can allow for a long response time to the data request without
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OCR Scan
ct20j 0x00009f TMS320C8Q TMS320C80 SPRSQ23B IEEE-754 480M-B
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