NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 12.0 N H I-1 5 9 1 R T Series A d d en d u m (NHI-1561RT NHI-1561RT with Additional Configuration Register) The NHI-1591RT NHI-1591RT is a drop in replacement to the popular NHI-1561RT NHI-1561RT Dual Redundant Remote Terminal with the addition o f the following features. All new features are enabled via the lower byte (D07-D00) of the Configuration Register at Address 9. In order to maintain the value of bits D15-D08 D15-D08, use a Read-Modify-Write sequence when accessing this register. This will also guarantee software compatibility between the ... | OCR Scan |
2 pages, |
NHI-1591RT NHI-1561RT D07-D00 D15-D08 NHI-1582ET NHI-1561RT abstract |
|
|||
| Abstract: ENL, in conjunction with MASTER_EN, controls the lower 8-bit data lines (D07-D00). ENH, in , FUNCTION TABLES Lower 8-Bit Data Bus Transceivers (D07ÂD00, SD07ÂSD00) INPUTS OPERATION MASTER_EN , Isolation. D07ÂD00 and SD07ÂSD00 inputs can float. H X X Isolation, low power mode X = H or L , DIR_OUT DIR(S/CF) VCC_S R INT ENL MASTER_EN D07-D00 8 8 To 7 Other Channels VCC_S R ... | Original |
22 pages, |
SN74LV4320AGKFR SN74LV4320A SD15 SD14 SD13 SCE1 D07-D00 A10-A00 LM320A 16BIT 11BIT 13BIT SCES628 SN74LV4320A abstract |
|
|||
| Abstract: signals will be written into the CY7C964 CY7C964's while the data on D07ÂD00 is ignored. For the VIC64 VIC64 register , on D07ÂD00. Data read from the VIC64 VIC64 would also appear on D07ÂD00. To assure the proper timing on the D07ÂD00 signals with respect to the DS* signal, DS* is driven active on the cycle following PAS* driven , VMEbus signals. To assure the proper timing on the D07-D00 signals with respect to the DS* signal, DS* is ... | Original |
36 pages, |
motorola full line vme 68030 3XXXXX VIC64 CY7C964 PALC22V10D-7 74FCT16245T VIC64 abstract |
|
|||
| Abstract: while the data on D07ÂD00 is ignored. For the VIC64 VIC64 register access, the PAS*, DS*, and CS* are all driven active. Data to be written to the VIC64 VIC64 would be presented on D07ÂD00. Data read from the VIC64 VIC64 would also appear on D07ÂD00. Master Read Cycle Initiation If an address of 2xxxxxxx16, 3xxxxxxx16 , decoded. To assure the proper timing on the D07ÂD00 signals with respect to the DS* signal, DS* is , D07-D00 signals with respect to the DS* signal, DS* is driven active on the cycle following PAS* driven ... | Original |
36 pages, |
VIC64 VIC068A PALC22V10D CY7C964 74FCT16245T Motorola 68040 CY7C335 VIC64 abstract |
|
|||
| Abstract: written into the CY7C964 CY7C964's while the data on D07-D00 is ig nored. The STROBE* signal for CY7C964 CY7C964 , D07-D00. Data read from the VIC64 VIC64 would also appear on D07-D00. An example of VIC64 VIC64 register access is , From these diagrams, the fol T assure the proper timing on the D07-D00 sig o lowing performance , signals. To assure the proper timing on the D07-D00 sig nals with respect to the DS* signal, DS* is ... | Original |
41 pages, |
vme bus specification vhdl VIC64 VIC068A motorola VME 68030 CY7C964 CY7C335 74FCT16245T VME bus 68040 VIC64 abstract |
|
|||
| Abstract: with MASTER_EN, controls the lower 8-bit data lines (D07-D00). ENH, in conjunction with MASTER_EN , 2005 - REVISED APRIL 2005 FUNCTION TABLES Lower 8-Bit Data Bus Transceivers (D07ÂD00, SD07ÂSD00 , Isolation. D07ÂD00 and SD07ÂSD00 inputs can float. Isolation, low power mode POST OFFICE BOX 655303 · , VCC_S DIR_OUT DIR(S/CF) D07-D00 8 8 SD07-SD00 SD07-SD00 To 7 Other Channels To 7 Other Channels ... | Original |
25 pages, |
LM320A SN74LV4320A 16BIT 11BIT 13BIT SCES628A SN74LV4320A abstract |
|
|||
| Abstract: with MASTER_EN, controls the lower 8-bit data lines (D07-D00). ENH, in conjunction with MASTER_EN , 2005 - REVISED APRIL 2005 FUNCTION TABLES Lower 8-Bit Data Bus Transceivers (D07ÂD00, SD07ÂSD00 , Isolation. D07ÂD00 and SD07ÂSD00 inputs can float. Isolation, low power mode POST OFFICE BOX 655303 · , VCC_S DIR_OUT DIR(S/CF) D07-D00 8 8 SD07-SD00 SD07-SD00 To 7 Other Channels To 7 Other Channels ... | Original |
25 pages, |
SN74LV4320A 16BIT 11BIT 13BIT SCES628A SN74LV4320A abstract |
|
|||
| Abstract: with MASTER_EN, controls the lower 8-bit data lines (D07-D00). ENH, in conjunction with MASTER_EN , 2005 - REVISED APRIL 2005 FUNCTION TABLES Lower 8-Bit Data Bus Transceivers (D07ÂD00, SD07ÂSD00 , Isolation. D07ÂD00 and SD07ÂSD00 inputs can float. Isolation, low power mode POST OFFICE BOX 655303 · , VCC_S DIR_OUT DIR(S/CF) D07-D00 8 8 SD07-SD00 SD07-SD00 To 7 Other Channels To 7 Other Channels ... | Original |
25 pages, |
SN74LV4320A 16BIT 11BIT 13BIT SCES628A SN74LV4320A abstract |
|
|||
| Abstract: with MASTER_EN, controls the lower 8-bit data lines (D07-D00). ENH, in conjunction with MASTER_EN , 2005 - REVISED APRIL 2005 FUNCTION TABLES Lower 8-Bit Data Bus Transceivers (D07ÂD00, SD07ÂSD00 , Isolation. D07ÂD00 and SD07ÂSD00 inputs can float. Isolation, low power mode POST OFFICE BOX 655303 · , VCC_S DIR_OUT DIR(S/CF) D07-D00 8 8 SD07-SD00 SD07-SD00 To 7 Other Channels To 7 Other Channels ... | Original |
23 pages, |
SN74LV4320A 16BIT 11BIT 13BIT SCES628A SN74LV4320A abstract |
|
|||
| Abstract: ENL signal controls the lower 8 bits (D07ÂD00), while the ENH signal controls the upper 8 bits (D15ÂD08). LOWER 8-BIT DATA BUS TRANSCEIVERS (1) (D07ÂD00, SD07ÂSD00) INPUTS MASTER_EN L L L H (1) X = H or L ENL L L H X DIR (S/CF) H L X X OPERATION SD data to D bus D data to SD bus Isolation. D07ÂD00 , SOE-INT VCC_S R INT ENL MASTER_EN VCC_S DIR_OUT DIR(S/CF) D07-D00 8 8 SD07-SD00 SD07-SD00 To 7 Other ... | Original |
27 pages, |
22 K 5w resistor CF4320H SCES655A CF4320H abstract |
|
|||
| Abstract: QSFCT2X273T QSFCT2X273T PRELIMINARY Q 16-Bit Register with Asynchronous Reset nchronous R < in QVSOPTM qs74fct2X 273t FEATURES/BENEFITS · Function compatible to the 74F273 74F273 74FCT273 74FCT273 and 74ABT273 74ABT273 · CMOS power levels: ... | OCR Scan |
4 pages, |
QSFCT2X273T QSFCT2X273T abstract |
|
|||
| Abstract: 1229h QSFCT2X273T QSFCT2X273T PRELIMINARY 16-Bit Register with Asynchronous Reset in QVSOPâ„¢ QS74FCT2X273T QS74FCT2X273T FEATURES/BENEFITS Function compatible to the 74F273 74F273 74FCT273 74FCT273 and 74ABT273 74ABT273 TTL-compatible input and output levels Ground bounce controlled outputs Reduced output swing of 0-3.5V JEDEC-FCT spec compatible Std. thru C speed grades with 5.2 ns tPD for C Iol = 48 mA CMOS power levels: ... | OCR Scan |
4 pages, |
QS74FCT2X273T 74FCT273 74F273 74ABT273 QSFCT2X273T QSFCT2X273T abstract |
|
|||
| Abstract: QSFCT2X273T QSFCT2X273T, QSFCT2X2273T QSFCT2X2273T ffl 16-Bit Register with qs74fct2X27st m Asynchronous Reset QS74fct2x2273t Quality Semiconductor. Inc. FEATURES/BENEFITS • Function compatible to the 74F273 74F273 • 74FCT273 74FCT273 and 74ABT273 74ABT273 • CMOS power levels: ... | OCR Scan |
7 pages, |
74FCT273 74F273 74ABT273 QSFCT2X273T QSFCT2X2273T QSFCT2X273T abstract |
|
|||
| Abstract: 1 6 - B it R e g is t e r w it h Ã- Q u a l it y S e m ic o n d u c t o r , I n c . q s 7 4 f c t 2X273t A s y n c h ro n o u s R e s e t in Q V S O P TM FEATURES/BENEFITS · Function compatible to the 74F273 74F273, 74FCT273 74FCT273 and 74ABT273 74ABT273 · CMOS power levels: ... | OCR Scan |
4 pages, |
datasheet abstract |
|
|||
| Abstract: QSFCT2X273T QSFCT2X273T, QSFCT2X2273T QSFCT2X2273T TM ] Q u a l it y S e m i c o n d u c t o r , In c . 16-Bit Register with Asynchronous Reset QS74FCT2X273T QS74FCT2X273T qs74fct2X2273t FEATURES/BENEFITS · · · · · Function compatible to the 74F273 74F273 74FCT273 74FCT273 and 74ABT273 74ABT273 CMOS power levels: ... | OCR Scan |
7 pages, |
QSFCT2X273T QSFCT2X2273T QSFCT2X273T abstract |
|
|||
| Abstract: NT3980 NT3980 TFT LCD Source Driver Features n Output: 384 output channels n 8-bit resolution /256 gray scales n Dot inversion with polarity control n V1 ~ V10 for adjusting Gamma correction n Power for analog circuit: 7 ~ 10V n Output dynamic range: 0.1V ~ AVDD-0.1 n Power consumption of analog circuit: 6mA n Operating frequency: 70MHz(Vcc:3.0V~3.6V) 45MHz(Vcc:2.5V~3.0V) n Output deviation: ±2mv n Data inversion for reducing EMI n Cascade function with bi-direction shift control n CMO ... | Original |
13 pages, |
NT3980 R101 R102 R114 163 180 v4 130 NT398 V9 69 NT3980 abstract |
|
|||
| Abstract: P0430WQLC-T P0430WQLC-T Document No.: Tentative Product Specification Module name: P0430WQLC-T P0430WQLC-T Issue date: 2007/12/26 Version: 1.0 Customer Approved by Customer Approved by CMEL PD Division ENG Division QA Dept Note: 1. The information contained herein may be change without prior notice. It is therefore advisable to contact CHI MEI EL Corp. before designed your product based on this specification. 1 P0430WQLC-T P0430WQLC-T Document No.: Reversion History Version Date P ... | Original |
18 pages, |
diode d07 49 cmel 4.3 OLED driver IC P0430WQL CHI MEI C22P C22N S107 S160 Serial RGB 8bit CCIR601 24bit parallel RGB to 8bit cmel format rgb to hsync vsync P0430WQLC-T P0430WQLC-T P0430WQLC-T P0430WQLC-T abstract |
|
|||
| Abstract: P0430WQLB-T P0430WQLB-T Document No.: Tentative Product Specification Module name: P0430WQLB-T P0430WQLB-T Issue date: 2007/12/26 Version: 1.0 Customer Approved by Customer Approved by CMEL PD Division ENG Division QA Dept Note: 1. The information contained herein may be change without prior notice. It is therefore advisable to contact CHI MEI EL Corp. before designed your product based on this specification. 1 P0430WQLB-T P0430WQLB-T Document No.: Reversion History Version Date P ... | Original |
18 pages, |
24bit rgb input to ccir656 oled P0430WQL P0430WQLB S107 S160 C22P C22N cmel format OLED driver IC CHI MEI OLED waveforms rgb to hsync vsync cmel 4.3 P0430WQLB-T P0430WQLB-T P0430WQLB-T abstract |
|
|||