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Calculate Oscillator Jitter By Using Phase-Noise

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Abstract: Drakhlis, "Calculate Oscillator Jitter by using Phase-Noise Analysis Part 2," Microwaves and RF, February , 14, 2003, http://www.eedesign.com. 6. Boris Drakhlis, "Calculate Oscillator Jitter by using , MT-008 TUTORIAL Converting Oscillator Phase Noise to Time Jitter by Walt Kester INTRODUCTION , online to perform the integration by segments and calculate the rms jitter, thereby greatly simplifying , converting oscillator phase noise into time jitter. PHASE NOISE DEFINED First, a few definitions are in Analog Devices
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AD9445 AD9446 Boris Drakhlis ULN 2009 uln series ultra Low Noise ULN types Wenzel Associates 100MHz-SC
Abstract: . 6. References Drakhlis, Boris, "Calculate Oscillator Jitter By Using Phase-Noise Analysis," , . Rev. 0.1 3 AN279 By contrast, if we weight L(f) using the period jitter weighting function and , AN279 AN279 3. Basic Approach By definition, period jitter compares two similar instants in time , example. The estimation process may be simplified further by treating the period jitter weighting , jitter is dominated by high-frequency phase noise. Channel bandwidth plays a determining role in the Silicon Laboratories
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GR-499-CORE GR-1244-CORE
Abstract: Circuits, Vol. 34, No. 6, pp. 790-804. 2. Boris Drakhlis, "Calculate Oscillator Jitter By Using , point. The probability density as a function of the timing jitter t is calculated by setting vn = y = , various terms within Equation 4 by A yields: Equation 5 is a jitter distribution function similar to , slight modification, Equation 6 can also accommodate the jitter translation of other waveforms. By , bandwidth. Using numerical integration to integrate Equation 22, the resulting accumulated jitter with Maxim Integrated Products
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AN3631 APP3631 2n 3631 an363 100MH
Abstract: Oscillator Jitter By Using Phase-Noise Analysis," Microwaves & RF, Jan. 2001 pp. 82-90 and p. 157. 7 , , voltagecontrolled oscillator, low phase noise, low phase jitter, clock jitter, crystal oscillator, noise, SNR , 3 illustrates a sampling clock signal that contains jitter. Jitter generated by the clock is caused , Degrades ADC's Signal-to-Noise Ratio (SNR) Jitter generated by a clock source can cause the ADC's internal , can be calculated for a given amount of clock jitter: Figure 4. An SNR model obtained using the Maxim Integrated Products
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MAX104 MAX106 MAX2620 MB15E07 MAX105 MAX107 white noise Generator 1GHz VCO 10GHz APP800 1GHz PLL Generator VCO 10GHZ oscillator 120MH
Abstract: . Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy , , 1956, issued January 13, 1959. (describes flash and subranging conversion using tubes and transistors). , . Kiyomo, K. Ikeda, and H. Ichiki, "Analog-to-Digital Converter Using an Esaki Diode Stack," IRE , 3-bit flash ADC using a stack of tunnel diodes). 12. H. R. Schindler, "Using the Latest Analog Devices
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Analog-Digital Conversion Handbook Analog-DigitalConversionHandbook S4 diode 6cA MT-228 DIST/10 THD/10 HAR/20 MT10539
Abstract: noise in two ways. One way is to directly modulate the oscillator or VCO using a noise source. A VCO , KPHASEVn(t) = (t). You can calculate phase Page 3 of 8 noise by applying the Fourier transform to VOUT , : Phase Noise, PLL, Phase Locked Loop, VCO, Voltage Controlled Oscillator, Oscillator, Impairment, System , phaselocked loops can degrade the performance of a system. Phase noise in the oscillator of a wireless , telecommunications system causes time jitter in the signal chain. Although engineers usually try to minimize phase Maxim Integrated Products
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AN3822 APP3822 noise diode generator Zener Diode White noise noise source diode Phase-Modulator
Abstract: network processors. The classic design of using multiple 3rdovertone crystal oscillators followed by , System Environment Most clock oscillators give their jitter or phase-noise specification using an ideal , SV(f), one can instead calculate the DJ by measuring the spur in the phasenoise spectrum while , the PLL. The DJ can be estimated using the dual-Dirac model1 by measuring the peak distance between , caused by the convolution of the SJ PDF with the Gaussian distribution of the random jitter component Maxim Integrated Products
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HP Agilent 10MHz Reference DSO81304 fm linear 88-108mhz MAX3272 E5052 DSO81304A HFAN-04
Abstract: With Ultralow Noise Floor of â'"169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 fsRMS (Typ , inputs consist of primary, secondary, and crystal inputs, and manually selectable (through pins) using , CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small , 1 XTAL bypass (2) This mode is for XTAL input or overdrive of XTAL oscillator with LVCMOS , by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a Texas Instruments
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SCAS917C QFN-32 ISO/TS16949
Abstract: report Crystal Oscillator Performance of the CDCLVC1310 (SCAA119). NOTE If using the overdrive or , With Ultralow Noise Floor of â'"169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 fsRMS (Typ , inputs consist of primary, secondary, and crystal inputs, and manually selectable (through pins) using , CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small , ) IN_SEL0 0 1 XTAL bypass (2) This mode is for XTAL input or overdrive of XTAL oscillator with Texas Instruments
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SCAS917E
Abstract: Crystal Buffer With Ultralow Noise Floor of ­169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 , ) using the input MUX. The primary and secondary inputs can accept LVPECL, LVDS, HCSL, SSTL or LVCMOS , jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small 32-pin 5-mm × 5-mm QFN package , oscillator with LVCMOS input. For characteristics; see LVCMOS OUTPUT CHARACTERISTICS. This mode is only XTAL , described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate Texas Instruments
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SCAS917D
Abstract: report Crystal Oscillator Performance of the CDCLVC1310 (SCAA119). NOTE If using the overdrive or bypass , Crystal Buffer With Ultralow Noise Floor of ­169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 , ) using the input MUX. The primary and secondary inputs can accept LVPECL, LVDS, HCSL, SSTL or LVCMOS , jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small 32-pin 5-mm × 5-mm QFN package , overdrive of XTAL oscillator with LVCMOS input. For characteristics; see . This mode is only XTAL bypass Texas Instruments
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SCAA115
Abstract: report Crystal Oscillator Performance of the CDCLVC1310 (SCAA119). NOTE If using the overdrive or , With Ultralow Noise Floor of â'"169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 fsRMS (Typ , inputs consist of primary, secondary, and crystal inputs, and manually selectable (through pins) using , CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small , ) IN_SEL0 0 1 XTAL bypass (2) This mode is for XTAL input or overdrive of XTAL oscillator with Texas Instruments
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Abstract: With Ultralow Noise Floor of â'"169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 fsRMS (Typ , inputs consist of primary, secondary, and crystal inputs, and manually selectable (through pins) using , CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small , ) IN_SEL0 0 1 XTAL bypass (2) This mode is for XTAL input or overdrive of XTAL oscillator with , environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a Texas Instruments
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Abstract: report Crystal Oscillator Performance of the CDCLVC1310 (SCAA119). NOTE If using the overdrive or , With Ultralow Noise Floor of â'"169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 fsRMS (Typ , inputs consist of primary, secondary, and crystal inputs, and manually selectable (through pins) using , CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small , ) IN_SEL0 0 1 XTAL bypass (2) This mode is for XTAL input or overdrive of XTAL oscillator with Texas Instruments
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Abstract: clock (namely a low jitter clock) in order to limit the dynamic performance degradation caused by noise , contribution to jitter. Jitter is caused by noise but what can be interesting to understand in the phenomenon , uncertainty due to Clock Jitter The impact of the time jitter on the voltage errors is accentuated by the , 3-1. Example of High-speed Low Jitter Clock Generating System Clock Crystal Oscillator PLL , desired frequency. It works by comparing the VCO output frequency to a crystal oscillator. Since the Atmel
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MB15E07SL AT84A AT84D
Abstract: simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency , Measured using a Wenzel Oscillator as the input source. 5 ©2014 Integrated Device Technology, Inc , simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency , Measured using a Wenzel Oscillator as the input source. 6 ©2014 Integrated Device Technology, Inc , characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Integrated Device Technology
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IDT8P34S1102I
Abstract: simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency , Measured using a Wenzel Oscillator as the input source. 5 ©2014 Integrated Device Technology, Inc , simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency , Measured using a Wenzel Oscillator as the input source. 6 ©2014 Integrated Device Technology, Inc , characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Integrated Device Technology
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Abstract: fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects , Differential input accepts ECL/LVPECL, LVDS and CML levels Additive phase jitter, RMS @ 122.88MHz: 45fs , ) Part-to-Part Skew, NOTE 3, 4 odc Output Duty Cycle tjit Buffer Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section Test Conditions Minimum Typical Maximum Units 3 , voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs Integrated Device Technology
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ICS853S9252I
Abstract: . Most PLL clock devices use a VCO (Voltage Controlled Oscillator) for output clock generation. By using , MK2058-01 P R E L I M I N A RY I N F O R M AT I O N Communications Clock Jitter Attenuator Description Features The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter , 27MHz. A dual input mux is also provided. · Jitter attenuation for T1, E1, Frame Sync and other By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and Integrated Circuit Systems
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MK2058-01SI MK2058-01SITR ECHU1C104JB5 MAN05
Abstract: Ultralow Noise Floor of ­169 dBc/Hz Additive Phase Noise/Jitter Performance Is 25 fsRMS (Typ.) Operates , , secondary and crystal inputs and can be selected manually (through pins) using the input MUX. The primary , jitter performance is 25 fsRMS (typ). The CDCLVC1310 is packaged in a small 32-pin 5-mm × 5-mm QFN , Oscillator Input or XTAL Bypass mode Crystal Oscillator Output LVCMOS output 0 LVCMOS output 1 LVCMOS output , SEC_IN XTAL/overdrive (1) XTAL bypass (2) This mode can be used to overdrive the XTAL oscillator with Texas Instruments
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SCAS917B
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