NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| CYD09S72V | Cypress Semiconductor | FLEx72 18-Mb (256K x 72) Synchronous Dual-Port RAM |
26 pages, |
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| CYD09S72V-133BBC | Cypress Semiconductor | 128K x 72 (9 Mb) 3.3V synchronous dual-port SRAM. Speed 133 MHz. |
26 pages, |
Original | |
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| CYD09S72V-133BBC | Cypress Semiconductor | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
25 pages, |
Original | |
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| CYD09S72V-133BBI | Cypress Semiconductor | 128K x 72 (9 Mb) 3.3V synchronous dual-port SRAM. Speed 133 MHz. |
26 pages, |
Original | |
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| CYD09S72V-133BBI | Cypress Semiconductor | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
25 pages, |
Original | |
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| CYD09S72V-167BBC | Cypress Semiconductor | 128K x 72 (9 Mb) 3.3V synchronous dual-port SRAM. Speed 167 MHz. |
26 pages, |
Original | |
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| CYD09S72V-167BBC | Cypress Semiconductor | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
25 pages, |
Original | |
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| CYD09S72V18-167BBXC | Cypress Semiconductor | FullFlex Synchronous SDR Dual Port SRAM |
52 pages, |
Original | |
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| CYD09S72V18-167BBXI | Cypress Semiconductor | FullFlex Synchronous SDR Dual Port SRAM |
52 pages, |
Original | |
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| CYD09S72V18-200BBXC | Cypress Semiconductor | FullFlex Synchronous SDR Dual Port SRAM |
52 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: CYD09S72V Dual-Port SRAM 167 CYD09S72V-167BBC BB484 BB484 484-ball Grid Array Commercial 23mm x 23mm with 1.0mm pitch (FBGA) 133 CYD09S72V-133BBC BB484 BB484 484-ball Grid Array Commercial 23mm x , Cypress Device(27:12) C002h Defines Cypress DIE number for CYD18S72V CYD18S72V and CYD09S72V. C001h , CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V PRELIMINARY FLEx72TM 3.3V 64K/128K/256K 64K/128K/256K x 72 Synchronous , x 72) CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Max. Speed (MHz) 167 167 133 Max. Access ... | Original |
26 pages, |
CYD18S72V CYD09S72V CYD04S72V A15L A13L 64K/128K/256K CYD04S72V abstract |
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| Abstract: ) 3.3V Synchronous CYD09S72V Dual-Port SRAM 167 CYD09S72V-167BBC BB484 BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch (FBGA) 133 CYD09S72V-133BBC BB484 BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch (FBGA) CYD09S72V-133BBI BB484 BB484 484-ball Grid Array , CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V FLEx72TM 3.3V 64K/128K/256K 64K/128K/256K x 72 Synchronous Dual-Port RAM , ) 18-Mbit (256K x 72) CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Max. Speed (MHz) 167 167 133 ... | Original |
25 pages, |
CYD18S72V-133BBI CYD18S72V CYD09S72V CYD04S72V 64K/128K/256K CYD04S72V abstract |
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| Abstract: Dual-Port SRAM 133 CYD09S72V-133BBC BB484 BB484 484-ball Ball Grid Array Commercial 23 mm Ã- 23 mm with , CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V FLEx72TM 3.3 V 64 K/128 K/128 K/256 K/256 K Ã- 72 Synchronous Dual-Port RAM , (256K x 72) CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Max. Speed (MHz) 167 167 133 Max. , , 2010 [+] Feedback CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Logic Block Diagram[1] FTSELL PORTST[1:0]L , Mailboxes INTL INTR READYL LowSPDL Note 1. CYD04S72V CYD04S72V have 16 address bits, CYD09S72V have 17 ... | Original |
26 pages, |
CYD18S72V CYD09S72V CYD04S72V BE5L K/128 K/256 CYD04S72V abstract |
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| Abstract: SRAM 167 CYD09S72V-167BBC BB484 BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch (FBGA) 133 CYD09S72V-133BBC BB484 BB484 484-ball Grid Array Commercial 23 mm x 23 mm with 1.0-mm pitch (FBGA) CYD09S72V-133BBI BB484 BB484 484-ball Grid Array Industrial 23 mm x 23 mm with , CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V FLEx72TM 3.3V 64K/128K/256K 64K/128K/256K x 72 Synchronous Dual-Port RAM , ) 18-Mbit (256K x 72) CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Max. Speed (MHz) 167 167 133 ... | Original |
25 pages, |
CYD18S72V CYD09S72V CYD04S72V CYD18S72V-133BBI be5l 64K/128K/256K CYD04S72V abstract |
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| Abstract: CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V FLEx72TM 3.3 V 64 K/128 K/128 K/256 K/256 K Ã- 72 Synchronous Dual-Port RAM , ) CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Max. speed (MHz) 167 133 133 Max. access time-clock to , CYD09S72V CYD18S72V CYD18S72V Logic Block Diagram[1] FTSELL FTSELR CONFIG Block CONFIG Block PORTST[1:0 , READYL LowSPDL Note 1. CYD04S72V CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V CYD18S72V have 18 bits. Document Number : 38-06069 Rev. *M Page 2 of 30 CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V ... | Original |
30 pages, |
CYD18S72V CYD09S72V CYD04S72V be5l K/128 K/256 CYD04S72V abstract |
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| Abstract: CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V FLEx72TM 3.3 V 64 K/128 K/128 K/256 K/256 K Ã- 72 Synchronous Dual-Port RAM , ) CYD09S72V 133 4.4 350 484-ball FBGA 23 mm x 23 mm 18-Mbit (256K x 72) CYD18S72V CYD18S72V 133 5.0 410 484-ball FBGA 23 , CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Logic Block Diagram[1] FTSELL PORTST[1:0]L CONFIG Block CONFIG Block , address bits, CYD09S72V have 17 address bits and CYD18S72V CYD18S72V have 18 bits. Document Number : 38-06069 Rev. *L Page 2 of 30 [+] Feedback CYD04S72V CYD04S72V CYD09S72V CYD18S72V CYD18S72V Contents Pin Configuration ... | Original |
30 pages, |
CYD04S72V CYD09S72V CYD18S72V K/128 K/256 CYD04S72V abstract |
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| Abstract: FLEX72 FLEX72_BASE4.bsd BSDL file for one of the two (identical) half scan chains CYD09S72V_484FBGA 484FBGA.net Allegro , CY7C0833V CY7C0833V_144FBGA 144FBGA.net CY7C0833V CY7C0833V_bsdl.zip FLEX36 FLEX36_BASE4.bsd CYD04S72V CYD04S72V_484FBGA 484FBGA.net CYD09S72V_bsdl.zip Allegro , /CY7C0833V/CYD18S36V/ /CY7C0833V/CYD18S36V/ CYD04S72V/CYD09S72V/CYD18S72V) Introduction Cypress FLEx18/36/72 Dual-Port SRAMs (CYD09S18V/ CYD09S18V/ CYD09S36V/CYD18S36V/CYD04S72V/CYD09S72V/ CYD18S72V CYD18S72V) are compliant with the IEEE 1149.1 JTAG , FLEx72 4-MBit Dual-Ports (CYD09S18V/CYD09S36V/CY7C0833V/CYD04S72V/ CYD09S18V/CYD09S36V/CY7C0833V/CYD04S72V/ CYD09S72V) contain two halves. Each ... | Original |
11 pages, |
orcad pcb footprint design CYD18S72V CYD18S36V CYD09S72V CYD09S18V jtag bsdl cypress AN5027 CYD09S18V/CYD09S36V/CY7C0833V/CYD18S36V/ CYD04S72V/CYD09S72V/CYD18S72V CYD09S18V/ CYD09S36V/CYD18S36V/CYD04S72V/CYD09S72V/ CYD18S36V/CYD18S72V CYD09S18V/CYD09S36V/CY7C0833V/CYD04S72V/ AN5027 abstract |
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| Abstract: 16JT 72 (CYD18S72V18 CYD18S72V18) 9 Mbit: 128K x 72 (CYD09S72V18) 4 Mbit: 64K x 72 (CYD04S72V18 CYD04S72V18) The , The CYD18S72V18 CYD18S72V18, CYD09S36V18 CYD09S36V18, and CYD04S18V18 CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and , CYD18S72V18 CYD18S72V18, CYD09S72V18, and CYD04S72V18 CYD04S72V18. 7. Leave this Ball unconnected for CYD09S72V18 and CYD04S72V18 CYD04S72V18. ... | Original |
52 pages, |
CYD18S36V18 CYD09S36V18 be5l 484-ball datasheet abstract |
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| Abstract: 72 (CYD18S72V18 CYD18S72V18) 9 Mbit: 128K x 72 (CYD09S72V18) 4 Mbit: 64K x 72 (CYD04S72V18 CYD04S72V18) The , The CYD18S72V18 CYD18S72V18, CYD09S36V18 CYD09S36V18, and CYD04S18V18 CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and , CYD18S72V18 CYD18S72V18, CYD09S72V18, and CYD04S72V18 CYD04S72V18. 7. Leave this Ball unconnected for CYD09S72V18 and CYD04S72V18 CYD04S72V18. ... | Original |
52 pages, |
CYD18S36V18 CYD18S18V18 CYD09S36V18 BE5L datasheet abstract |
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| Abstract: 18-Mbit: 256K x 72 (CYD18S72V18 CYD18S72V18) - 9-Mbit: 128K x 72 (CYD09S72V18) - 4-Mbit: 64K x 72 (CYD04S72V18 CYD04S72V18) · , address bits. The CYD09S72V18 and the CYD04S36V18 CYD04S36V18 devices have 17 address bits. The CYD04S72V18 CYD04S72V18 has 16 , Leave this ball unconnected for CYD18S72V18 CYD18S72V18, CYD09S72V18 and CYD04S72V18 CYD04S72V18. 6. Leave this ball unconnected for CYD09S72V18 and CYD04S72V18 CYD04S72V18. 7. Leave this ball unconnected for CYD04S72V18 CYD04S72V18. Document # ... | Original |
51 pages, |
10-JTAG 10JTAG CYD04S18V18 CYD09S36V18 CYD18S36V18 CYD36S18V18-133BGI CYD36S36V18-133BGI CYD36S72V18-133BGI tca 780 str 350-430 BE5L TMS 1070 NL CYD36S72V18 CYD18S72V18 CYD36S72V18 abstract |
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