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Part : SLCS90-600-R Supplier : PEPPERL+FUCHS Manufacturer : Allied Electronics & Automation Stock : - Best Price : $875.7600 Price Each : $875.7600
Part : SLCS90-600-T Supplier : PEPPERL+FUCHS Manufacturer : Allied Electronics & Automation Stock : - Best Price : $716.5300 Price Each : $716.5300
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CS9060

Catalog Datasheet MFG & Type PDF Document Tags

U0401

Abstract: TCI diode PD0402 BCLK3 BREQO LA31 LA28 LHOLD LA29 LHOLDA LA30 BG~ ADS~ TT0 CS9060~ TS~ BB~ R/W , ~ READYI~ LLOCK~ 5 TEA~ BG~ AVEC~ TCI~ TBI~ LLOCK~ TA~ ADS~ BLAST~ CS9060~ READYI , ~ RST040~ TA~ TEA~ BG~ AVEC~ TCI~ TBI~ ADS~ BLAST~ CS9060~ READYI~ LHOLDA LLOCK~ 8 8
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MACH210 U0401 TCI diode 16v8c TIP 41 transistor 41 bb LA29 LOCK040 PD0401 U0402 I/O23 I/O22 I/O21

U0401

Abstract: TCI diode 1 LA[2.31] 2 3 4 5 6 7 8 LA[2.31] LA28 LA29 LA30 LA31 U0401 ADS~ TT0 CS9060~ TS~ BB~ R/W TT1 LOCK040~ SRRDY~ TIP~ A TS~ TIP~ R/W TT0 TT1 TS~ TIP~ R/W TT0 TT1 BR~ BB~ LOCK040~ BR~ BB~ LOCK040~ READYO~ SRRDY~ LHOLD BREQO READYO~ SRRDY~ LHOLD BREQO 2 3 4 5 6 7 8 9 10 11 BCLK3 BREQO LA31 LA28 LHOLD LA29 , LLOCK~ READYI~ TBI~ ADS~ BLAST~ CS9060~ READYI~ LHOLDA ADS~ BLAST~ CS9060~ READYI
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LA30 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26

MACH210A

Abstract: "output enables ads.OE = oe & (bg # bb); blast.OE = oe & (bg # bb); cs9060.OE = oe; readyi.OE = oe , la28.la31 !readyo !srrdy lhold !br !bb breqo !lock040pin 9; !oe "OUTPUTS _ads _blast !cs9060 , _ads istype 'reg,neg'; _blast istype 'reg,neg'; cs9060 istype 'com,neg'; readyi istype 'com,neg , ; "output equations cs9060 = tip & CFG; readyi = srrdy; ta = srrdy # readyo # retry # avinta # bkinta , ,tt0, readyo,srrdy,lock040] -> [lholda,bg, CTL, ta,tea,tbi,readyi, cs9060,llock]) [CK,L,L, X,X,X,X, X
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MACH210A PCI9060
Abstract: master !iordy !roe "OUTPUTS !csuart !cseprom _portrdy !cs9060 !cssram _q0 _port ca "or , ,neg'; cseprom istype 'reg,neg'; _portrdyistype 'reg,neg'; cs9060 istype 'com,neg'; cssram , # !(iordy & blast); cs9060 = CFG; cssram = SRAM; state_diagram PORTCA state IDLE: if reset , else IDLE; test_vectors ([pclk,roe,reset, ads,ADDR,wait,iordy,blast] -> [csuart,cseprom,cs9060 PLX Technology
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P20V8R E0000000 F0000000

u0304

Abstract: LA29 ~ READY CS9060~ WAITI~ LBE2~ LW/R LA27 XACK~ HOLDACK 2 3 4 5 6 7 8 9 10 11 LCLKB , XSIZ1 RDYI~ HOLDREQ READY WAITI~ CS9060~ XREQ~ XSIZ0 XSIZ1 RDYI~ HOLDREQ READY WAITI~ CS9060~ PR/W WBE0~ WBE1~ WBE2~ WBE3~ CARRY PR/W WBE0~ WBE1~ WBE2~ WBE3~ (A4) (A5
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PD0301 16V8-10 R0302 u0304 LA25 16v810 U0301 I/O25 I/O24 I/O20 I/O19

O-42

Abstract: MACH220 ~ EMPTY~ FIFOWEN~ DACK0~ CS9060~ VACT 28 29 30 31 32 33 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 , ~ AUDCS~ AUDRW CS9060~ DREQ0~ READY~ VIDCS~ VIDRD~ VIDWR~ AUDCS~ AUDRW CS9060~ DREQ0
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74FCT541AT MACH220 O-42 LA3C LA10 CLK25B I/O47 I/O46 I/O45 I/O44 I/O43

PD0404

Abstract: U0401 1 2 3 4 5 6 7 8 PCLK1B LA[2.31] A LA[2.31] LA3 LA28 LA29 LA30 LA31 RESET~ ADS~ BLAST~ WAIT~ READYO~ IORDY~ RESET~ ADS~ BLAST~ WAIT~ READYO~ PU0401 PD0401 1 2 3 4 5 6 7 8 9 10 11 14 23 13 U0401 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 22 21 20 19 18 17 16 15 CA PORT~ Q0~ CSSRAM~ CS9060~ PORTRDY~ CSEPROM~ CSUART~ CA PORT~ CSSRAM~ CS9060~ A
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U0403 16V8R PD0404 DIP10 pu0403 I11I12 20V8R PU0402 PU0403 PU0404 PU0405

STI3400

Abstract: STI4500 = oe; dreq0.OE = oe; regrd.OE = oe; regwr.OE = oe; cs9060.OE = oe; "clock assignments , !dreq0 _regrd _regwr !cs9060 pin 48; pin 33; pin 10; pin 13; pin 25; "ready to 9060 "DMA , istype 'reg'; ready dreq0 cs9060 istype 'com,neg'; istype 'com,neg'; istype 'com,neg'; fiforst , rdyo; dreq0 = !reset & (!alempty # (dreq0 & !(alempty & !empty & ads & dack0); cs9060 = PCISEL , ,cs9060]) [CK,X,L, X,X,X, X, X,X,X,X,L] -> [Z,Z, Z,Z,Z, Z,Z,Z,Z]; "tri-state [CK,H,L, X,X,X, X, X,X,X,X
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STI3400 STI4500 MACH220A

16V8-10

Abstract: semiconductor ad 5.9 125 126 127 128 129 130 131 132 133 135 136 LA[2.31] 19 18 17 CS9060~ RDYI , ~ READY CS9060~ WAITI~ LBE2~ LW/R LA27 XACK~ HOLDACK 2 3 4 5 6 7 8 9 10 11 LCLKB , XSIZ1 RDYI~ HOLDREQ READY WAITI~ CS9060~ XREQ~ XSIZ0 XSIZ1 RDYI~ HOLDREQ READY WAITI~ CS9060~ PR/W WBE0~ WBE1~ WBE2~ WBE3~ CARRY PR/W WBE0~ WBE1~ WBE2~ WBE3~ (A4) (A5
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74ACT74 R0801 U0801A semiconductor ad 5.9 MXA0 A10 J0601 LA17 PU0101 PU0102 PU0103 U0303B PU0104

la1 d22

Abstract: la2 d2 timer 128 129 130 131 132 133 135 136 C 19 18 17 CS9060~ READYI~ BTERM~ 147 146 , [2.31] LA28 LA29 LA30 LA31 U0401 ADS~ TT0 CS9060~ TS~ BB~ R/W TT1 LOCK040~ SRRDY~ TIP , 31 30 29 28 27 26 25 24 LLOCK~ READYI~ TBI~ ADS~ BLAST~ CS9060~ READYI~ LHOLDA ADS~ BLAST~ CS9060~ READYI~ LHOLDA LLOCK~ LLOCK~ A TCI~ READYO~ PD0401 RESET~ AVEC
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U0101 80960CA RN0804 la1 d22 la2 d2 timer rn0805 PCI9060 68040 L16 eeprom U0102 PCI9060/68040 PD0201 PU0201

OSCILLATOR

Abstract: MACH210 ADDR MUX MACH210 DRAM PCI9060ES 403GC CPU LD[31:0] D[31:0] LA[25:2] A[6:29] LA[31:26] LHOLD MACH210 HOLDREQ LHOLD A HOLDACK ADS~ CS1~ LW/R PR/W BLAST~ READY LBE[3:0] WBE[3:0] RDYO ~ XREQ~ RDYI~ XACK~ CS9060~ XSIZ[0:1] PCI BUS WAITI~ 50 MHz OSCILLATOR DIV/2 LCLK (25 MHz) PLX Technology
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OSCILLATOR transistor oscillator circuit 252a LD31 addr

403GC

Abstract: 9060ES enables holdreq.oe = oe; xreq.oe = oe; rdyi.oe = oe; waiti.oe = oe; cs9060.oe = oe; ready.oe = oe , Raaum 0x4a1a " CS9060 should be declared active low "This pal monitors direct slave cycles from the , to 9060 !cs9060 pin 5; "Chip select for 9060 internal registers la28.la31 pin 43,14,21,18 , wbe2 wbe3 cs9060 la26 la27 la28 la29 la30 la31 istype 'com,neg'; istype 'reg,neg'; istype , ; cs9060 = cs & !la25 & !la24; HILA = 0; holdreq = lhold # (DRAMCTL = S10); unalign = UNALIGN; inc2 =
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9060ES h9 ck PC/PCI9060ES

MXA0 A10

Abstract: 16V8 enables holdreq.oe = oe; xreq.oe = oe; rdyi.oe = oe; waiti.oe = oe; cs9060.oe = oe; ready.oe = oe , ~ XREQ~ RDYI~ XACK~ CS9060~ XSIZ[0:1] WAITI~ 50 MHz DIV/2 LCLK (25 MHz , running a 403GC cycle to the PCI9060ES with the 9060 chip select (CS9060~) asserted. The address offsets , running a 403GC cycle to the PCI9060ES with the 9060 chip select (CS9060~) asserted. The address offsets , BLAST~ READY LBE[3:0] WBE[3:0] RDYO ~ XREQ~ RDYI~ XACK~ CS9060~ XSIZ[0:1
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403GA 16V8 PCIbus LCLK-25

U0801A

Abstract: 16V8-10 enables holdreq.oe = oe; xreq.oe = oe; rdyi.oe = oe; waiti.oe = oe; cs9060.oe = oe; ready.oe = oe , ~ XREQ~ RDYI~ XACK~ CS9060~ XSIZ[0:1] WAITI~ 50 MHz DIV/2 LCLK (25 MHz , running a 403GC cycle to the PCI9060ES with the 9060 chip select (CS9060~) asserted. The address offsets , running a 403GC cycle to the PCI9060ES with the 9060 chip select (CS9060~) asserted. The address offsets , BLAST~ READY LBE[3:0] WBE[3:0] RDYO ~ XREQ~ RDYI~ XACK~ CS9060~ XSIZ[0:1
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LD31

Abstract: 0ns TITLE 50ns 100ns 150ns 200ns 250ns 300ns POWERPC , 1 WORD WRITE TO PCI9060 INTERNAL REGISTERS [PPCWR1.TD] (01/24/96) STATE LCLK-25 [4,15] [4,15] A[6:29] [3,11] [3,11] [3,12] [3,12] PR/W WBE[0.3] [4,16] [4,16] LD[31:0] WRITE DATA [2,13] [2,13] CS1~ [3,10] [3,10 CS9060~ [0,0] [0,0] LA[25:2] LA[31:26] 000000 [3,10] [3,10 LBE[3:0] [3,7] PCICTL STATE PIDLE [3,7] P0 [2,6] [3,7] P2 P1 [3,7
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LD31

Abstract: 0ns TITLE 50ns 100ns 150ns 200ns 250ns 300ns POWERPC , 1 WORD READ FROM PCI9060 INTERNAL REGISTERS [PPCRD1.TD] (01/24/96) STATE LCLK-25 [4,15] [4,15] A[6:29] [3,11] [3,11] [3,12] [3,12] [2,12] [2,12] PR/W WBE[0:3] CS1~ [3,10] [3,10 CS9060~ [0,0] [0,0] LA[25:2] LA[31:26] 000000 [3,10] [3,10] LBE[3.0] [2,6.5] PCICTL STATE PIDLE [2,6.5] P4 [2,6.5] [2,6.5] P6 P5 [2,6.5] P7 [2,6.5] PIDLE [2
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Y0803

Abstract: U0801B 121 122 125 126 127 128 129 130 131 132 133 135 136 LA[2.10] 19 18 17 3 CS9060 , PIXCLK LW/R FIFOLD~ EMPTY~ FIFOWEN~ DACK0~ CS9060~ VACT 28 29 30 31 32 33 I/O0 I/O1 , ~ VIDRD~ VIDWR~ AUDCS~ AUDRW CS9060~ DREQ0~ READY~ VIDCS~ VIDRD~ VIDWR~ AUDCS~ AUDRW CS9060
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U0801B Y0803 C0801 IC LM7805 N1 Y10 pin diagram of IC LM7805 20V8C

A 2169

Abstract: TLBI 603 LD[0:31] DH[0:31] LA[0:31] CS9060# A[0:31] MACH210 LHOLD# LHOLDA# LDSHOLD
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A 2169 TLBI 9060ES/603

403GC

Abstract: 9060ES enables holdreq.oe = oe; xreq.oe = oe; rdyi.oe = oe; waiti.oe = oe; cs9060.oe = oe; ready.oe = oe , Raaum 0x4a1a " CS9060 should be declared active low "This pal monitors direct slave cycles from the , to 9060 !cs9060 pin 5; "Chip select for 9060 internal registers la28.la31 pin 43,14,21,18 , wbe2 wbe3 cs9060 la26 la27 la28 la29 la30 la31 istype 'com,neg'; istype 'reg,neg'; istype , ; cs9060 = cs & !la25 & !la24; HILA = 0; holdreq = lhold # (DRAMCTL = S10); unalign = UNALIGN; inc2 =
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H 04 D 35 P16V8C

403GA

Abstract: PCI9060ES ~ CS9060~ XSIZ[0:1] WAITI~ 50 MHz DIV/2 LCLK (25 MHz) OSCILLATOR , running a 403GC cycle to the PCI9060ES with the 9060 chip select (CS9060~) asserted. The address offsets , running a 403GC cycle to the PCI9060ES with the 9060 chip select (CS9060~) asserted. The address offsets
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powerpc 403 BU108

596CA

Abstract: 16v8 book master !iordy !roe "OUTPUTS !csuart !cseprom _portrdy !cs9060 !cssram _q0 _port ca "or , ,neg'; cseprom istype 'reg,neg'; _portrdyistype 'reg,neg'; cs9060 istype 'com,neg'; cssram , # !(iordy & blast); cs9060 = CFG; cssram = SRAM; state_diagram PORTCA state IDLE: if reset , else IDLE; test_vectors ([pclk,roe,reset, ads,ADDR,wait,iordy,blast] -> [csuart,cseprom,cs9060 , master !iordy !roe "OUTPUTS !csuart !cseprom _portrdy !cs9060 !cssram _q0 _port ca "or
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BREQ960 596CA 16v8 book BREQ9060

MACH210A

Abstract: SR040 la28.la31 !readyo !srrdy lhold !br !bb breqo !lock040pin 9; !oe "OUTPUTS _ads _blast !cs9060 , _ads istype 'reg,neg'; _blast istype 'reg,neg'; cs9060 istype 'com,neg'; readyi istype 'com,neg , ; "output equations cs9060 = tip & CFG; readyi = srrdy; ta = srrdy # readyo # retry # avinta # bkinta , ,tt0, readyo,srrdy,lock040] -> [lholda,bg, CTL, ta,tea,tbi,readyi, cs9060,llock]) [CK,L,L, X,X,X,X, X , , ADDR,tt1,tt0, readyo,srrdy,lock040] -> [ARB, CTL, ta,tea,tbi,readyi, cs9060,llock]) [CK,L,H, L,L,L,L
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SR040 D24-31 D16-23 D8-15 D16-31 D0-15

h20000008

Abstract: 7705 reset master !iordy !roe "OUTPUTS !csuart !cseprom _portrdy !cs9060 !cssram _q0 _port ca "or , ,neg'; cseprom istype 'reg,neg'; _portrdyistype 'reg,neg'; cs9060 istype 'com,neg'; cssram , # !(iordy & blast); cs9060 = CFG; cssram = SRAM; state_diagram PORTCA state IDLE: if reset , else IDLE; test_vectors ([pclk,roe,reset, ads,ADDR,wait,iordy,blast] -> [csuart,cseprom,cs9060
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h20000008 7705 reset

L1239

Abstract: l0728 reset !fifold pin 21; "fifo load (program flags) !ready !dreq0 _regrd _regwr !cs9060 pin 48 , cs9060 istype 'com,neg'; istype 'com,neg'; istype 'com,neg'; fiforst fifold fifowen istype , & (!alempty # (dreq0 & !(alempty & !empty & ads & dack0); cs9060 = PCISEL; audrw = !lw_r , ,featoe] -> [pixoe,ldoe, fiforen,fifooe,fifowen, fiforst,fifold,dreq0,cs9060]) [CK,X,L, X,X,X, X, X,X,X , ,cs9060]) "Misc [CK,L,H, L,L,L, ^h000,L,L, H,H, L,L,L] -> [FIDLE, L,L,L, L,L,L, L,L]; [CK,L,H, L,L,L
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L1239 l0728 l0312 SGS L282 L0936 L11616 9060/MPEG

L0936

Abstract: l0728 !dreq0 _regrd _regwr !cs9060 pin 48; pin 33; pin 10; pin 13; pin 25; "ready to 9060 "DMA , istype 'reg'; ready dreq0 cs9060 istype 'com,neg'; istype 'com,neg'; istype 'com,neg'; fiforst , rdyo; dreq0 = !reset & (!alempty # (dreq0 & !(alempty & !empty & ads & dack0); cs9060 = PCISEL , ,cs9060]) [CK,X,L, X,X,X, X, X,X,X,X,L] -> [Z,Z, Z,Z,Z, Z,Z,Z,Z]; "tri-state [CK,H,L, X,X,X, X, X,X,X,X , , fifold,fifowen,fiforen, ready,cs9060]) "Misc [CK,L,H, L,L,L, ^h000,L,L, H,H, L,L,L] -> [FIDLE, L,L,L, L
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L0988 L9960 l0832 L4204 L9804 l0416 V0157 V0158 V0159 V0160 V0161 V0162

1N4148/2 pin connector sip

Abstract: ACT04 MOTOROLA master !iordy !roe "OUTPUTS !csuart !cseprom _portrdy !cs9060 !cssram _q0 _port ca "or , ,neg'; cseprom istype 'reg,neg'; _portrdyistype 'reg,neg'; cs9060 istype 'com,neg'; cssram , # !(iordy & blast); cs9060 = CFG; cssram = SRAM; state_diagram PORTCA state IDLE: if reset , else IDLE; test_vectors ([pclk,roe,reset, ads,ADDR,wait,iordy,blast] -> [csuart,cseprom,cs9060 , 129 130 131 132 133 135 136 C CS9060~ 19 18 17 PU0201 PU0202 147 146 169
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1N4148/2 pin connector sip ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 R0809 00000009-B PCLK1-33
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