500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
WM8351CGEB/V Cirrus Logic Consumer Circuit, CMOS, PBGA129 visit Digikey
WM8325GEFL/V Cirrus Logic Power Management Circuit, CMOS visit Digikey
WM8321GEFL/V Cirrus Logic Power Management Circuit, CMOS visit Digikey
WM8351CGEB/RV Cirrus Logic Consumer Circuit, CMOS, PBGA129 visit Digikey
WM8321GEFL/RV Cirrus Logic Power Management Circuit, CMOS visit Digikey
WM8325GEFL/RV Cirrus Logic Power Management Circuit, CMOS visit Digikey

CMOS+4049

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: / 7414 / 4009 / 4049 / 4069 7404 / 7406 / 7414 / 4009 / 4049 / 4069 7404 / 7405 / 7414 / 4009 / 4049 , / 4009 / 4049 / 4069 4012 4082 4025 4068 4071 7448 / 4056 / 4511 7447 / 4056 / 4511 7476 / 4027 , / 4049 / 4069 7400 / 7403 / 74132 / 4093 / 40107 7420 7474 / 74175 / 74273 / 40174 74161 / 74164 , 4047 4049 4050 4051 4052 4053 4056 4060 4063 4066 4067 4068 4069 4070 4071 4072 4073 , 4016 7447 / 7448 / 4511 7485 / 4585 7430 7404 / 7405 / 7406 / 7414 / 4009 / 4049 7486 / 74266 -
Original
74573 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432
Abstract: SPDT 40.49 out. 2 amp rating. Output: AC units — Triac; DC units — transistor. Low cost- 892-2013 120AC/CHDFA .6-60 sec. 120 VAC SPDT 40.49 compact size. 3 terminal configuration. No current leakage to load. Fixed flash DCR10 Series Delay On 120AF/FHDFA892-2014 1-100 min. 120 VAC SPDT 40.49 rates. Duty , SPDT 40.49 Temperature Range: 23°C to +60°C. Mounting: Single screw or optional 2 892-2016 12DC/CHDFA .6-60 sec. 12 VDC SPDT 40.49 Release TDR screw panel mount. 892-2017 12DF/FHDFA 1-100 min. 12 VDC SPDT Allied Electronics Catalog
Original
LR62586 Transistor D 2494 CI 4049 transistor on 4673 2 pin flasher relay 892-0142 892-2002 E96739 115ASPDTR1-120C 12DNOR1-120C 120AF10-120DFV 12DSPDTR1-120C
Abstract: referred to Vss pin voltage ORDERING NUMBERS: HCC 4049 UBD for dual in-line Ceramic package HCC 4049 UBF for dual in-line ceramic package, frit seal HCC 4049 UBK for ceramic flat package HCF 4049 UBE for dual in-line plastic package HCF 4049 UBF for dual in-line ceramic package, frit seal HCF 4049 UBM , MECHANICAL DATA (dimensions in mm) Dual in-line ceramic package for HCC 4049 UBD and HCC 4050 BD 736 as 7.62 t92w 12.!"« 9 si 4 Dual in-line ceramic package for HCC/HCF 4049 UBF and HCC/HCF -
OCR Scan
4049UB 4050B 4049 UBE 4049 4049 CMOS Inverter 4049UBE 4049 CMOS 4049 bf 4049UB/4050B
Abstract: voltage values are referred to Vss pin voltage ORDERING NUMBERS: HCC 4049 UBD for dual in-line ceramic package HCC 4049 UBF for dual in-line ceramic package, frit seal HCC 4049 UBK for ceramic flat package HCF 4049 UBE for dual in-line plastic package HCF 4049 UBF for dual in-line ceramic package, frit seal HCF 4049 UBM for plastic micropackage HCC 4050 BD for dual in-line ceramic package HCC 4050 BF , plastic micropackage 233 2/82 This Material Copyrighted By Its Respective Manufacturer HCC/HCF 4049 UB -
OCR Scan
CMOS 4049 4049 ubm 4050BE vc 4050 HCF 4049 UBE 4049 not
Abstract: M 54/M 74HC 4049/4050 CIRCUIT SCHEMATIC (Per Gate) HC4049 HC4050 CHIP CARRIER H C4049 > O O O , 74HC 4049/4050 PIN DESCRIPTION (H C 4 0 4 9 ) PIN No 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 13, 16 8 , MCBmmETFBWIlKB* 1075 M 54/M 74HC 4049/4050 RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vi Vo Top tr, tf , 4/6 " 7 # HOCRBaLBBirMSHOCS rz 7 SCS-IHOMSON 1076 M 54/M 74HC 4049/4050 AC , C 4IX 9) vOUT (H C 4 0 5 0 ) SCS-IHOMSON 5/6 1077 M 54/M 74HC 4049/4050 TEST -
OCR Scan
IC 4049 CMOS 4049 internal circuit operation of ic 4049 LC12480 iC 4049 14 pin 74hC4049 54/74HC 4049B/4050B 74HCXXXXC1R M54/74HC4049 M54/74HC4050 M54/75HC4049
Abstract: values are re fe rre d t o V s s p in volta g e O R D E R IN G NUM BERS: HCC 4049 UBD fo r dual in -lin e ceram ic package HCC 4049 UBF fo r dual in -lin e ceramic package, HCC 4049 UBK fo r ceramic fla t package HCF 4049 UBE fo r dual in -lin e plastic package HCF 4049 UBF fo r dual in -lin e ceramic package, HCF 4049 UBM fo r plastic micropackage HCC 4050 BD fo r dual in -lin e ceramic package , /82 HCC/HCF 4049 UB UCC/HCF 4050 B M ECHANICAL DATA (d imensions in mm) Dual in -lin e ceramic -
OCR Scan
4049U
Abstract: . E16.3 E16.3 M16.15 M16.15 Pinout CD74HC4049, CD74HC4050 (PDIP, SOIC) TOP VIEW 4049 VCC 1Y 1A 2Y , 10 4Y 9 4A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A CAUTION: These devices are sensitive to electrostatic , Number 1543.3 1 CD74HC4049, CD74HC4050 Functional Diagram 4050 4049 VCC 2 1Y 1Y 3 1A 4 2Y 2Y 5 2A 6 3Y 3Y 7 3A 8 GND 12 5Y 13 NC NC 14 6A 15 6Y 6Y 4049 NC 4050 1 16 11 5A 5Y 10 4Y 9 Harris Semiconductor
Original
4049 PC 4049 pin diagram CD74HC4049E CD74HC4050E CD74HC4049M CD74HC4050M ISO9000 1-800-4-HARRIS
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 54/74H C 4049 M C 54/74H C 4050 H ex B uffers/Logic-Level Down C onverters High-Performance Silicon-Gate CMOS T he M C 5 4 /7 4 H C 4 0 4 9 c o n s is ts , '¢ Chip Complexity: 36 FETs or 9 Equivalent Gates (4049) 24 FETs or 6 Equivalent Gates (4050) ORDERING , LS TTL H C 4049 DE VIC E ^ S o â'" OUT H C 4050 HC D E VIC E S TAN D A R D HC 4049 CMOS HC 4050 H C D E V IC E *Table 1. Supply Examples NOTE: To determine the noise -
OCR Scan
MC54/74HC4050 MC14049UB MC14050B 751B-05
Abstract: SOIC PKG. NO. E16.3 E16.3 M16.15 M16.15 Pinout CD74HC4049, C D74HC4050 (PDIP, SOIC) TOP VIEW 4049 VCC 1Y 4050 V ccE U 4050 16] NC 15] 6Y 1 ^ 6A 13] NC 4049 NC 6Y 6A NC 5Y 5A 4Y 4A 1A 2Y 2A 3Y 3A , 4050 4049 4049 4050 1Y 1Y 6Y 6Y 2Y 2Y NC 3Y 3Y 5Y Logic -
OCR Scan
HC 4050 N hct 4049 A104Y IS09000
Abstract: Hex Logic Level Down Converters T - X2.^/ DESCRIPTION The '4049 and '4 05 0 have a modified input , both positive and negative static voltages. In addition the '4049 and '4 05 0 can be used as simple buf , '4049 1A 2A 3A 4A ( 12 ) 5A ( 15 ) 6A · (3) hv (4) (6) ( 10 ) FUNCTION TABLE `4050 (3) (2 ) (4) (6 ) INPUT A H L OUTPUT Y '4049 L H '4050 H L (S) (7) (9) (111 (14) > > ( 10 -
OCR Scan
4049 logic gate 54/74LS KS74HCTLS KS54HCTLS HCTLS4049 HCTLS4050 KS74A
Abstract: CD74HC4049, C D74HC4050 (PDIP, SOIC) TOP VIEW 4049 4050 4050 16] NC 15] 6Y 14] 6A 13] NC 12] 5Y 5A 10] 4Y ^ ]4 A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A Vcc 1Y 1A 2Y 2A 3Y 3A GND vcc [T 1Y [7 1A 2Y [7 2A [7 3Y ^ , CD74HC4049, CD74HC4050 Functional Diagram 4050 4049 V CC 16 15 4049 NC 4050 1Y 1Y 1A -
OCR Scan
D74HC4049 CD54HC4049H CD54HC4050H D54HC4049W
Abstract: , TSSOP) TOP VIEW 4049 VCC 1Y 1A 2Y 2A 3Y 3A GND 4050 VCC 1 1Y 2 1A 3 2Y 4 2A 5 3Y 6 3A 7 GND 8 4050 16 NC 15 6Y 14 6A 13 NC 12 5Y 11 5A 10 4Y 9 4A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A CAUTION: These devices , © 2000,Texas Instruments Incorporated 1 CD54/74HC4049, CD54/74HC4050 Functional Diagram 4050 4049 VCC 2 1Y 1Y 3 1A 4 2Y 2Y 5 2A 6 3Y 3Y 7 3A 8 GND 12 5Y 13 NC NC 14 6A 15 6Y 6Y 4049 NC 4050 1 16 Texas Instruments
Original
SCHS205B CD74H C4050 CD54HC4049F3A CD54HC4050F3A CD74HC4050PW
Abstract: CD74HC4049PW 4049 ­55 to 125 CD74HC4049E CD54HC4049, CD54HC4050 (CERDIP) CD74HC4049, CD74HC4050 , 125 16 Ld TSSOP 4049 4050 VCC VCC 1 16 NC NC 1Y 1Y 2 15 6Y 6Y 1A , Incorporated 1 CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Functional Diagram 4050 4049 16 , 14 1A 2Y 4050 NC 1Y 1Y 4049 11 3Y 5A 7 5Y 10 3A 4Y 8 9 Texas Instruments
Original
IC 4049 DATASHEET ic 4049 pinout hct 4049 datasheet HC4050A 15-V TA 4049 SCHS205I
Abstract: information. Pinout CD74HC4049, CD74HC4050 (PDIP, SOIC, TSSOP) TOP VIEW 4049 4050 VCC VCC 1 16 NC 4050 NC 4049 1Y 1Y 2 15 6Y 6Y 1A 1A 3 14 6A 6A 2Y 2Y 4 , CD74HC4049, CD74HC4050 Functional Diagram 4050 4049 1 16 VCC 2 6Y 3 6A 4 13 2Y NC 5 NC 12 2A 5Y 6 3Y 6Y 14 1A 2Y 4050 15 1Y 1Y 4049 NC Texas Instruments
Original
SCHS205A
Abstract: CD74HC4049M96 ­55 to 125 16 Ld SOIC CD74HC4049NSR ­55 to 125 16 Ld SOP CD74HC4049PW 4049 , 4049 4050 VCC VCC 1 16 NC NC 1Y 1Y 2 15 6Y 6Y 1A 1A 3 14 6A 6A , , CD74HC4049, CD54HC4050, CD74HC4050 Functional Diagram 4050 4049 16 1 VCC 2 15 6Y 3 , 1Y 1Y 4049 11 3Y 5A 7 5Y 10 3A 4Y 8 9 4A GND Logic Diagrams Texas Instruments
Original
pinout diagram of 4049 4049 application note TEXAS INSTRUMENTS 4049 SCHS205H
Abstract: ) CD74HC4049, CD74HC4050 (PDIP, SOIC, SOP, TSSOP) TOP VIEW 4049 4050 VCC VCC 1 16 NC 4050 4049 NC 1Y 1Y 2 15 6Y 6Y 1A 1A 3 14 6A 6A 2Y 2Y 4 13 NC NC 2A , /74HC4050 Functional Diagram 4050 4049 16 1 VCC 2 15 6Y 3 6A 4 13 2Y NC 5 NC 12 2A 5Y 6 3Y 6Y 14 1A 2Y 4050 NC 1Y 1Y 4049 11 Texas Instruments
Original
1A314 TI 4050 SCHS205C CD74HC4050NSR
Abstract: , CD74HC4050 (PDIP, SOIC, SOP, TSSOP) TOP VIEW 4049 VCC 1Y 1A 2Y 2A 3Y 3A GND 4050 VCC 1 1Y 2 1A 3 2Y 4 2A 5 3Y 6 3A 7 GND 8 4050 16 NC 15 6Y 14 6A 13 NC 12 5Y 11 5A 10 4Y 9 4A 4049 NC 6Y 6A NC 5Y 5A 4Y 4A , Incorporated 1 CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Functional Diagram 4050 4049 VCC 1 2 16 15 4049 NC 6Y 4050 1Y 1Y 3 1A 4 13 14 6Y 6A 2Y 2Y 5 2A 6 12 NC , % of V CC at V CC = 5V Description The 'HC 4049 and 'HC 4050 are fabricated with high-speed Texas Instruments
Original
SN54/74HCT SN74HC4851/HC4852
Abstract: , CD54HC4050 (CERDIP) CD74HC4049, CD74HC4050 (PDIP, SOIC, TSSOP) TOP VIEW 4049 4050 VCC VCC 1 16 NC 4050 4049 NC 1Y 1Y 2 15 6Y 6Y 1A 1A 3 14 6A 6A 2Y 2Y 4 , CD54/74HC4049, CD54/74HC4050 Functional Diagram 4050 4049 16 1 VCC 2 15 6Y 3 , 1Y 1Y 4049 11 3Y 5A 7 5Y 10 3A 4Y 8 9 4A GND Logic Diagrams Texas Instruments
Original
CD54HC4049F 74HC4050 ic 4050
Abstract: OUTPUT BUFFER 6 VOLT REGULATOR CR 3 IN 4 4 5 4 OUF 002 U3 4049 TTL L O DA TA C O M P PL LETE - ) k - í OUTPUT BUFFER U3 4049 12 T TL H=>EN ABLE W R IT E START ENABLE DELAY U3 4049 IN TER N A L W R IT E ' CLO C K (1/2 RA TE OF IN P U T CLOCK) OUTPUT BUFFER CMOS P H A S E ENCODED W R I T E DATA IN' I IS P O S I T I V E T R A N S I T I O N REQUIRED SPECIFICATIONS . TM _ ^ pROPhitTARY uf E - _ JI1 TT T '.T T iä UNIT OF MEASURE TOLERANCES (E X C EP T A S N OTED) B r a -
OCR Scan
Abstract: Gates (4049) 24 FETs or 6 Equivalent Gates (4050) MC54/74HC4049 MC54/74HC4050 J SUFFIX CERAMIC CASE , HSCMOS Vd d * - High-Voltage CMOS to HSCMOS Vcc# O OUT w5 0 u>- STANDARD CMOS H C 4049 H C 4050 - ° HC DEVICE LSTTL OEVICE H C 4049 H C 4050 HC DEVICE NOTE: To determine the -
OCR Scan
74hc4049m MC14000-series MC14000- HC4049I HC4060 74HCT04
Showing first 20 results.