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Part : L-CLK12 Supplier : 3M Interconnect Solutions Manufacturer : Avnet Stock : - Best Price : - Price Each : -
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CLK12

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Jitter Performance - Period Jitter: 25 psec (Typ.) at CLK1-2 The AK8146A is a low power multi clock , IDD Conditions MIN Pin: CLK1-2,REFO TYP MAX V 0.8VDD IOH=-4mA Pin: CLK1-2 , Symbol Conditions MIN (1) Crystal Clock Frequency Pin: CLK1-2 Output Clock Duty Cycle , CLK1-2 Output Clock Fall Time Unit 24.0 Pin: XI 500mVp-p or more Duty:30%-70% @0.5 , TYP 50 60 % (2) 1.5 4.0 ns (2) 1.5 4.0 ns Pin: CLK1-2 ,REFO Pin Asahi Kasei Microdevices
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000MH MS0992-E-00

CRC-16 and verilog

Abstract: CLK48 should be sampled by the application on the rising edge of Clk12. This signal also qualifies HCIM_RdWr , internal to the Host Controller. APP_SAdr should meet setup time to Clk12. HCI Register Write Data Valid , signal asserted on the rising edge of Clk12. HCI Register Write Data: Data to be written into the Host , pointed to by the HCF_WrPtr[5:0] pins when HCF_WriteN is sampled asserted on the rising edge of Clk12. , PORT INTERFACE Clk12 Clk48 Test_PLLCLK Figure 2: Logic Symbol for USB 1.1 Host Controller 8
OKI Electric Industry
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Z0122 Z0100 CRC-16 and verilog CLK48

CLK12

Abstract: Period Jitter: 25 psec (Typ.) at CLK1-2 Low Current Consumption: 5.0mA (Typ.) at 3.3V Supply Voltage: 3.0 , Consumption Symbol VOH VOL IDD -20 to +85, 24MHz Crystal, unless otherwise noted Conditions Pin: CLK1-2,REFO IOH=-4mA Pin: CLK1-2,REFO IOL=+4mA No load Ta=25 5.0 MIN 0.8VDD 0.2VDD TYP MAX Unit V V mA AC , Conditions Pin: XI 500mVp-p or more Duty:30%-70% @0.5*(Input Swing) CLK1-2 Pin: CLK1-2 Pin: REFO MIN , trise tfall Pin: CLK1-2 ,REFO Pin: CLK1-2 ,REFO Pin: CLK1-2 (2) (1) AT cut, Fundamental mode
Asahi Kasei Microdevices
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CLK12

AK8128MV

Abstract: CLK2 ⡠⡠⡠出å›è² è· CLK1-2 長 : : : 3.0V â'" 3.6V 8 mA , /off : 15pF ä½ã'¸ãƒƒã'¿å‡ºå› Period Jitter CLK1-2 Long term Jitter CLK1-2 ï , Table 1: CLK1-2 Clock Output Frequency Selection Pin Clock Input Frequency (MHz) Clock Output , CLK1 GND Figure 1: Typical Connection Diagram C1-2 : 0.1μF ç¨'度 SW0 : CLK1-2 のå'¨æ³¢æ , '' SW1 : CLK1-2 のå'¨æ³¢æ•°è¨­å®šãƒãƒ¼ãƒãƒ«ã«å¿ã˜ã¦è¨­å®šã—てä¸'さã"ã
Asahi Kasei Microdevices
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AK8128MV 40625MH 2896MH MS1291-J-00

PC MOTHERBOARD CIRCUIT diagram

Abstract: PC MOTHERBOARD CIRCUIT diagram download free 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , BCLKn CLK24, CLK12 12 REF1 Low-level output current p L l l ­4 REF0 IOL 8 PCLKn
Texas Instruments
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CDC9841 PC MOTHERBOARD CIRCUIT diagram PC MOTHERBOARD CIRCUIT diagram download free free circuit diagram of motherboard ALL MOTHERBOARD CIRCUIT DIAGRAM SCAS458D 24-MH 12-MH 318-MH 31818-MH

AK8128ME

Abstract: CLK2 ⡠⡠⡠出å›è² è· CLK1-2 長 : : : 3.0V â'" 3.6V 8 mA , /off : 15pF ä½ã'¸ãƒƒã'¿å‡ºå› Period Jitter CLK1-2 Long term Jitter CLK1-2 ï , Table 1: CLK1-2 Clock Output Frequency Selection Pin Clock Input Frequency (MHz) Clock Output , CLK1 GND Figure 1: Typical Connection Diagram C1-2 : 0.1μF ç¨'度 SW0 : CLK1-2 のå'¨æ³¢æ , '' SW1 : CLK1-2 のå'¨æ³¢æ•°è¨­å®šãƒãƒ¼ãƒãƒ«ã«å¿ã˜ã¦è¨­å®šã—てä¸'さã"ã
Asahi Kasei Microdevices
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AK8128ME MS1293-J-00

AK8128ME

Abstract: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , : S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL , : CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072 11.2896 12.288 27.000 MAX Unit MHz MHz MHz , ). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency Selection
Asahi Kasei Microdevices
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MS1293-E-01

PC MOTHERBOARD CIRCUIT diagram

Abstract: CDC9841 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , , CLK12 12 REF1 Low-level output current ­4 REF0 IOL 8 PCLKn 6 BCLKn 4
Texas Instruments
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PC MOTHERBOARD CIRCUIT diagram

Abstract: ALL MOTHERBOARD CIRCUIT DIAGRAM 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , , CLK12 12 REF1 Low-level output current ­4 REF0 IOL 8 PCLKn 6 BCLKn 4
Texas Instruments
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Abstract: .) at CLK1-2 - Long Term Jitter (1000 cycle, 1σ): 40 psec (Typ.) at CLK1-2 Low Current Consumption , VDD Cpl Min 3.3 Max Unit 85 -20 3.0 Pin: CLK1-2 Typ °C 3.6 V 15 , Current consumption IDD Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25 , No , Term jitter (3) (2) Output Clock Duty Cycle 45 Pin: CLK1-2 50 55 % Output clock , (Pin7). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency Asahi Kasei Microdevices
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MS1293-E-00

AK8128mv

Abstract: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , , S1 Pin: S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25, No load S[0:1] = All Setting -1 -20 -20 -1 0.8VDD 0.2VDD 8.0 0.7VDD 0.45VDD , : CLK1(2) S[0:1] = "HL", "HH" 1000cycles Pin: CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072
Asahi Kasei Microdevices
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MS1291-E-00
Abstract: .) at CLK1-2 - Long Term Jitter (1000 cycle, 1σ): 40 psec (Typ.) at CLK1-2 Low Current Consumption , VDD Cpl Min 3.3 Max Unit 85 -40 3.0 Pin: CLK1-2 Typ °C 3.6 V 15 , Current consumption IDD Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25 , No , Term jitter (3) (2) Output Clock Duty Cycle 45 Pin: CLK1-2 50 55 % Output clock , (Pin7). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency Asahi Kasei Microdevices
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AK8128MV

Abstract: MS1291-E-01 Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , : S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL , : CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072 11.2896 12.288 27.000 MAX Unit MHz MHz MHz , ). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency Selection
Asahi Kasei Microdevices
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MS1291-E-01

AK8128

Abstract: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , , S1 Pin: S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25, No load S[0:1] = All Setting -1 -20 -20 -1 0.8VDD 0.2VDD 8.0 0.7VDD 0.45VDD , : CLK1(2) S[0:1] = "HL", "HH" 1000cycles Pin: CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072
Asahi Kasei Microdevices
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AK8128
Abstract: ) * * * * * * * Vc c [ X1[ X2[ GND[ 1 u 2 3 28 27 ] REFO ] REF1 4 26 ] V CC 25 ] CLK12 OE[ 5 , CLK24 Hi-Z 24 MHz 24 MHz 24 MHz T C LK /4 CLK12 Hi-Z 12M H z 1 2 MHz 12M H z T C LK /8 tT C L K is a , High-level output current PCLKn BCLKn CLK24, CLK12 REF0 REF1 Iq l Low-level output current PCLKn BCLKn CLK24, CLK12 T /\ NOTE 3: O perating free-air temperature Unused inputs m ust be held high or low to prevent , , CLK12 REFO REF1 PCLKn BCLKn CLK24, CLK12 2.5 2.5 2.5 2.5 2.5 l0 H = - 1 2 m A IO H = - 8 m A v OH VCC -
OCR Scan

circuit diagram of motherboard

Abstract: free circuit diagram of motherboard 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , , CLK12 12 REF1 Low-level output current ­4 REF0 IOL 8 PCLKn 6 BCLKn 4
Texas Instruments
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circuit diagram of motherboard PC MOTHERBOARD CIRCUIT diagram free CDC9841DW CDC9841DWR
Abstract: 20 19 18 17 16 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC BCLK4 BCLK5 GND BCLK1 BCLK0 , fixed-frequency outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the , CLK24 Hi-Z 24 MHz 24 MHz 24 MHz TCLK /4 CLK12 Hi-Z 12 MHz 12 MHz 12 MHz TCLK /8 H H H TCLK /2 TCLK , 2 27 REF1 24 ÷2 ÷2 ÷2 25 CLK24 CLK12 6 24-MHZ PLL 7 PCLK0 PCLK1 9 , High-level output current PCLKn BCLKn CLK24, CLK12 REF0 REF1 IOL Low-level output current PCLKn BCLKn CLK24 Texas Instruments
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CLK12

Abstract: ICS9158-03 input.) VDD=5V±10% or 3.3V±10%, TEMP=0-70°C FS2 FS1 FS0 CLK2A (MHz) CLK12(A-C) (MHZ , OE CLK2A CLK12(A-C) CLK12(A-D) 40MHz (Pin 6) 24MHz (Pin 7) REF (Pin 18) 1 , ANALOG GROUND 10 OE 11 CLK12B OUT 12 GND PW R Digital GROUND 13 CLK1C , R 17 CLK12A OUT CLK12A clock output 18 REF OUT 14.31818 M Hz clock output Digital GROUND IN IN OUTPUT ENABLE. Tristates all outputs when low. CLK12B clock output CPU
Integrated Circuit Systems
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ICS9158-03 ICS9158-03CW24 fs216
Abstract: Symbol VM VCC VIN fchop fCLK fPWM 1ch, 2ch, 3ch, 4ch, 5ch, 6ch CLK12, CLK34, CLK56 PWM5, PWM6 Conditions , on-resistance ID = -400mA VIN = 0 V (ST, CLK12, CLK34) VIN = 5 V (ST, CLK12, CLK34) ST, CLK12, CLK34 ST, CLK12 , temperature, Ta - °C 20 40 60 80 100 ILV00179 No.7944-4/24 LV8041FN PGND1 VREF7 CLK12 , VM56 OUT5B SEN5 OUT5A CLK12 51 MO12 CPH1 CPH2 CPL2 LIM7 VGH IN71 IN72 , SEN3 STB OUT1A OUT3B CLK12 OUT2A OUT4B OUT2B SEN1 TSD LVS TSD LVS VGH 5 Bridge SANYO Electric
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ENN7944
Abstract: 20 21 22 23 24 PIN NAM E CLK1A X2 X1 VDD GND 40 M Hz 24 M Hz CLK1B AGND OE CLK12B GND CLK1C CLK1D FS2 AVDD CLK12A REF GND VDD CLK12C CLK2A FS1 FS0 TYPE OUT OUT IN PW R PW R OUT OUT OUT PW R IN OUT PW R OUT , 32 32 50 50 66.67 60 CLK12(A-C) (MHZ) 16 32 16 32 25 50 33.33 60 CLK1(A-D) (MHz) 16 16 16 16 25 25 33.33 30 Peripheral Clocks OE 1 0 CLK2A Runs Tristate CLK12(A-C) Runs Tristate CLK12(A-D) Runs , output CLK1B clock output ANALOG GROUND OUTPUT ENABLE. Tristates all outputs when low. CLK12B clock Integrated Circuit Systems
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S13H

Abstract: .) at CLK1-2 - Long Term Jitter (1000 cycle, 1σ): 40 psec (Typ.) at CLK1-2 Low Current Consumption , VDD Cpl Min 3.3 Max Unit 85 -40 3.0 Pin: CLK1-2 Typ °C 3.6 V 15 , Current consumption IDD Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25 , No , Term jitter (3) (2) Output Clock Duty Cycle 45 Pin: CLK1-2 50 55 % Output clock , (Pin7). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency
Asahi Kasei Microdevices
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S13H AK8139A 200MH
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