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LTC2931HF#TRPBF Linear Technology LTC2931 - Configurable Six Supply Monitor with Adjustable Reset and Watchdog Timers; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2931IF#TRPBF Linear Technology LTC2931 - Configurable Six Supply Monitor with Adjustable Reset and Watchdog Timers; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2931IF#PBF Linear Technology LTC2931 - Configurable Six Supply Monitor with Adjustable Reset and Watchdog Timers; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2931CF#PBF Linear Technology LTC2931 - Configurable Six Supply Monitor with Adjustable Reset and Watchdog Timers; Package: TSSOP; Pins: 20; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2931CF#TRPBF Linear Technology LTC2931 - Configurable Six Supply Monitor with Adjustable Reset and Watchdog Timers; Package: TSSOP; Pins: 20; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2931HF#PBF Linear Technology LTC2931 - Configurable Six Supply Monitor with Adjustable Reset and Watchdog Timers; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy

CD4049 pin configuration not gate

Catalog Datasheet MFG & Type PDF Document Tags

SCR C106Y1

Abstract: soil moisture sensor circuit diagram k E> LOW BATTERY ALARM OSCILLATOR n PIN CONFIGURATION DuaMrvLine Package Ã' ground , Specified: TA = 25°C. V+= 15 V, flSET 8M ^ tprom Pin 7 to See Test Circuit_ Ope-ating Voltage Power , Supply Current, Alarm ON V+ = 9 V VquT = 0 V, Pin \2 Open 0 V < V|N < 15 V Input Bias Current {Pins 1 , Internal Reference Voltage (Measured at Pin II Ta = 70° C rA = o-c
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mm74hc

Abstract: CMOS TTL Logic Family Specifications Function devices only (listed in this section of the databook). These devices are direct pin, function and , (VCC = 5.0V), so TTL is not guaranteed to pull a valid CMOS logic "1" level. If the TTL circuit is , greater than 3V as a logic high, so in most instances TTL can drive MM74HC. To see why TTL does not pull up further, Figure 1 shows a typical standard TTL gate's output schematic. As the output pulls up , 5V supply, the TTL output cannot go much higher than about 3.5V. Figure 1 shows an LSTTL gate
Fairchild Semiconductor
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CD4000 CMOS TTL Logic Family Specifications FAIRCHILD MM74HC compared CMOS TTL Logic Family Specifications MM74HC fairchild MM74HC 16 pin MM74HC pin configuration MM74C

CD4049 PIN DIAGRAM

Abstract: CD40 shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark , include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed , Hex Buffer/ Converters) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate , . In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B , is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is
Texas Instruments
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CD4049 PIN DIAGRAM CD40 CD4069UB CD4049 pin configuration not gate SCHS046B CD405

cd4049ub

Abstract: CD4049 PIN DIAGRAM 's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b , tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" , Semiconductor, CD400 0, metal gate, CMOS Features The Harris CD4049UB and CD4050B are inverting and , logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin compatible with
Harris Semiconductor
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CD4049UBE CD4049 PIN DIAGRAM Circuit hb4-b CD4049 ic 16 pin diagram CD4049 PIN DIAGRAM Datasheet Circuit

CD4049

Abstract: SCHS046A manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of , tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" , / Converters) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS Features , applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can
Texas Instruments
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SCHS046A CD4049

40KHZ ULTRASONIC transducers

Abstract: 40KHz ultrasonic interface amplitude of the echo received by the system is so low that it is not detectable by the Comparator_A, the , located close to the power supply lines of the device. A 14-pin box header (J1) allows JTAG interface to , . LED1 is provided to indicate measurement cycles. Port pin P1.5 is configured to output the buffered , by a bridge configuration with hex inverter gates U4-CD4049. Reference [6] is the data sheet for this device. One inverter gate is used to provide a 180-degrees phase-shifted signal to one arm of the
Texas Instruments
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40KHZ ULTRASONIC transducers 40KHz ultrasonic interface ultrasonic transducer 40khz 9V 40khz ultrasonic receiver and transmitter ultrasonic distance circuit design 40KHz Ultrasonic Transducer SLAA136A MSP430 MSP430F413
Abstract: located within the shaded area shown. The m anufacturer's identification shall not be used as a pin one , .5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15m m (0.006 inch) per side. 4. Dimension "E" does not include interlead , C D 4 0 4 9 U B and C D 4 0 5 0 B are pin com p atib le w ith the C D 4 0 0 9 U B and C D 4 0 1 0 B , . 16 is not con ne cte d in te rn a lly on the C D 4 0 4 9 U B o r C D 4050B , therefore, con ne ction -
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4010B 1-800-4-HARR

SCHS046A

Abstract: CD4050BE ic 16 pin diagram 's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and , .5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead , applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Terminal No. 16 is not connected
Texas Instruments
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CD4050BE ic 16 pin diagram dtl ttl logic GUIDE SCEA004 SZZU001B SDYU001N SCET004 SCAU001A CD4050BDW

CD4049 ic 16 pin diagram

Abstract: CD4049 ic not gate 16 pin diagram located within the shaded area shown. The m anufacturer's identification shall not be used as a pin one , tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15m m (0.006 inch) per side. 4. Dimension "E" , applications. In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B , is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is of
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CD4049 ic not gate 16 pin diagram 16 pin CD4049 pin configuration ECD4050B CD401

CD4049 ic not gate 16 pin diagram

Abstract: CD4049UB within the shaded area shown. The m anufacturer's identification shall not be used as a pin one , tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15m m (0.006 inch) per side. 4. Dimension "E" , CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Terminal No. 16 is not connected internally
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CD4050BM IL-STD-1835

TS-6001

Abstract: TS6001 , protrusions or gate burns. Mode flash, protrusions or gate burns shall not exceed 0.127 mm per side Does not , the TS6001 is a series-mode voltage reference, its supply current is not affected by changes in the , and is available in a 3-pin SOT23 package. APPLICATIONS Battery-Operated Equipment Data , ) 3-Pin SOT23 (Derate at 4.0mW/°C above +70°C) . 320mW Operating Temperature Range , indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum
Touchstone Semiconductor
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TS6001B TS-6001 CD4049 HEX INVERTER MAX6025 TS6001A TS6001DS
Abstract: 0.21 Min Does not include mode flash, protrusions or gate burns. Mode flash, protrusions or gate , 500µA. Since the TS6001 is a series-mode voltage reference, its supply current is not affected by , +85°C temperature range and is available in a 3-pin SOT23 package. TYPICAL APPLICATION CIRCUIT , IN (VIN ≥ 6V) . 60s Continuous Power Dissipation (TA = +70°C) 3-Pin , other condition beyond those indicated in the operational sections of the specifications is not implied Silicon Laboratories
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Abstract: TS6001 PACKAGE OUTLINE DRAWING 3-Pin SOT23 Package Outline Drawing (N.B., Drawings are not to scale , gate burns. Mode flash, protrusions or gate burns shall not exceed 0.127 mm per side Does not , 2200pF Since the TS6001 is a series-mode voltage reference, its supply current is not affected by , +85° C C temperature range and is available in a 3-pin SOT23 package. TYPICAL APPLICATION , +70° C) 3-Pin SOT23 (Derate at 4.0mW/° above +70° . 320mW C C) Electrical and thermal Touchstone Semiconductor
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Abstract: LOGIC GATE (WITH ±5V OUTPUT SWING) TO PIN 8 OF LMH6732 Figure 62. Dynamic Control of Power , improve switching time, a speed up capacitor from the gate output to pin 8 is recommended. The value of , TTL GATE TO PIN 8 OF LMH6732 Figure 63. Controlling Power On State with TTL Logic (Open , specifications per the terms of the Texas Instruments standard warranty. Production processing does not , which the device is intended to be functional, but specific performance is not ensured. For ensured Texas Instruments
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SNOSA47B ISO/TS16949

A97A

Abstract: cd4049 die LOGIC GATE (WITH ±5V OUTPUT SWING) TO PIN 8 OF LMH6732 Figure 62. Dynamic Control of Power , improve switching time, a speed up capacitor from the gate output to pin 8 is recommended. The value of , TTL GATE TO PIN 8 OF LMH6732 Figure 63. Controlling Power On State with TTL Logic (Open , specifications per the terms of the Texas Instruments standard warranty. Production processing does not , which the device is intended to be functional, but specific performance is not ensured. For ensured
Texas Instruments
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A97A cd4049 die
Abstract: * RP TO PIN 8 OF LMH6732 CMOS LOGIC GATE (WITH ±5V OUTPUT SWING) Figure 62. Dynamic Control , minimizes feed-through. To improve switching time, a speed up capacitor from the gate output to pin 8 is , NUMBERS SHOWN FOR SOIC PACKAGE RP TO PIN 8 OF LMH6732 OPEN COLLECTOR TTL GATE Figure 63 , Instruments standard warranty. Production processing does not necessarily include testing of all parameters , , but specific performance is not ensured. For ensured specifications, see the Electrical Texas Instruments
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25VPP CLC505 CLC449

DAC8512 equivalent

Abstract: SSM-2018 DAC8512 TOP VIEW (Not to Scale) 7 6 5 PIN DESCRIPTIONS Pin 1 2 3 4 The DAC8512 is a complete , compatible with data in (SDI), clock (CLK) and load strobe (LD). There is also a chip-select pin for , guaranteed by design and not subject to production testing. 5 The settling time specification does not apply , methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult , Thermal Resistance JA 8-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 103°C/W 8-Lead SOIC
Analog Devices
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DAC8512EP DAC8512 equivalent SSM-2018 2677006301 DB3 ZENER diode 12-BIT C1734 DAC8512EZ DAC8512FP DAC8512FS
Abstract: RP is connected between pin 8 and the output of a CMOS gate powered from ±5V supplies, the gate can , time, a speed up capacitor from the gate output to pin 8 is recommended. The value of this capacitor , TO PIN 8 OF LMH6732 OPEN COLLECTOR TTL GATE Figure 63. Controlling Power On State with TTL , Instruments standard warranty. Production processing does not necessarily include testing of all parameters , be functional, but specific performance is not ensured. For ensured specifications, see the Texas Instruments
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analog device 8512

Abstract: DAC-8512 PIN CONFIGURATION SO-8 P-DIP-8 & Cerdip-8 â'" Wâ'" VDD E â'¢ 3 VOUT CS H CLK Å , chip-select pin for connecting multiple DACs. A CLR input sets the output to zero scale at power on or upon , guaranteed by design and not subject to production testing. 5The settling time specification does not apply , packaging is not guar­ anteed for standard product dice. Consult factory to negotiate specifications based , Resistance 0JA 8-Pin Cerdip Package (Z) .148°C/W 8-Pin Plastic
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analog device 8512 DAG-8512

74HCoo

Abstract: TRANSISTOR 2n2222 p1 TOP VIEW 6 CLR (Not to Scale) 5 LD DAC8512 TOP VIEW (Not to Scale) 7 6 5 PIN DESCRIPTIONS , pin for connecting multiple DACs. A CLR input sets the output to zero scale at power on or upon user , These parameters are guaranteed by design and not subject to production testing. 5 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices , variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
Analog Devices
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74HCoo TRANSISTOR 2n2222 p1 DAC8512G STAA 74hc161s OP90 equivalent
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