NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Package Diagrams Thin Ball Grid Array Packages 42-Ball Thin Ball Grid Array (6 x 5 x 1.2 mm) BB42 51-85139-*A 1 Package Diagrams 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 BB100 51-85107-*B 2 Package Diagrams 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A BB165A 51-85122-*B 3 Package Diagrams 165-Ball FBGA (13 x 15 x 1.62 mm) BB165B BB165B 51-49026-* 4 Package Diagrams 165-Ball FBGA (15 x 17 x 1.20 mm) BB165C 51-85165-* 5 Package Diagrams 172-Ball FBGA (15 x 15 ... | Original |
15 pages, |
BB484 BB100 165 BALL FBGA BB209 datasheet abstract |
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| Abstract: CY7C1444AV33 CY7C1444AV33 CY7C1445AV33 CY7C1445AV33 PRELIMINARY 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM Functional Description[1] Features · Supports bus operation up to 250 MHz · Available speed grades are 250, 200 and 167 MHz · Registered inputs and outputs for pipelined operation · Optimal for performance (Double-Cycle deselect) · Depth expansion without wait state · 3.3V 5% and +10% core power supply (VDD) · 2.5V / 3.3V I/O operation · Fast clock-to-output times - 2.6 ns (for 250-MHz d ... | Original |
24 pages, |
CY7C1445AV33 CY7C1444AV33 CY7C1444AV33 abstract |
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| Abstract: CY7C1484V25 CY7C1484V25 CY7C1485V25 CY7C1485V25 PRELIMINARY 72-Mbit (2M x 36/4M 36/4M x 18) Pipelined DCD Sync SRAM Functional Description[1] Features · Supports bus operation up to 250 MHz · Available speed grades are 250, 200, and 167 MHz · Registered inputs and outputs for pipelined operation · Optimal for performance (Double-Cycle deselect) · Depth expansion without wait state · 2.5V power supply (VDD) · 2.5V / 1.8V I/O operation · Fast clock-to-output times - 3.0 ns (for 250-MHz device) The CY7C ... | Original |
24 pages, |
CY7C1485V33 CY7C1485V25 CY7C1484V33 CY7C1484V25 36/4M CY7C1484V25 abstract |
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| Abstract: CY7C1484V33 CY7C1484V33 CY7C1485V33 CY7C1485V33 PRELIMINARY 72-Mbit (2M x 36/4M 36/4M x 18) Pipelined DCD Sync SRAM Functional Description[1] Features · Supports bus operation up to 250 MHz · Available speed grades are 250, 200, and 167 MHz · Registered inputs and outputs for pipelined operation · Optimal for performance (Double-Cycle deselect) · Depth expansion without wait state · 3.3V 5% and +10% core power supply (VDD) · 2.5V / 3.3V I/O operation · Fast clock-to-output times - 3.0 ns (for 250-MHz d ... | Original |
24 pages, |
CY7C1485V33 CY7C1484V33-250AXC CY7C1484V33 36/4M CY7C1484V33 abstract |
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| Abstract: CY7C1444AV25 CY7C1444AV25 CY7C1445AV25 CY7C1445AV25 PRELIMINARY 36-Mbit (1M x 36/2M 36/2M x 18) Pipelined DCD Sync SRAM Functional Description[1] Features · Supports bus operation up to 250 MHz · Available speed grades are 250, 200, and 167 MHz · Registered inputs and outputs for pipelined operation · Optimal for performance (Double-Cycle deselect) · Depth expansion without wait state · 2.5V core power supply (VDD) · 2.5V/1.8V I/O supply · Fast clock-to-output times - 2.6 ns (for 250-MHz device) The CY ... | Original |
25 pages, |
CY7C1445AV25 CY7C1444AV25 36/2M CY7C1444AV25 abstract |
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| Abstract: CY7C1470V33 CY7C1470V33 CY7C1472V33 CY7C1472V33 CY7C1474V33 CY7C1474V33 PRELIMINARY 72-Mbit (2M x 36/4M 36/4M x 18/1M 18/1M x 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description · Pin-compatible and functionally equivalent to ZBTTM · Supports 250-MHz bus operations with zero wait states - Available speed grades are 250, 200, and 167 MHz · Internally self-timed output buffer control to eliminate the need to use asynchronous OE · Fully registered (inputs and outputs) for pipelined operation · Byte ... | Original |
28 pages, |
CY7C1474V33 CY7C1472V33-250 CY7C1472V33-200 CY7C1472V33 CY7C1470V33-250 CY7C1470V33-200 CY7C1470V33-167 CY7C1470V33 36/4M 18/1M CY7C1470V33 abstract |
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| Abstract: CY7C1347F-200BGC CY7C1347F-200BGC BG119 BG119 CY7C1347F-200BZC CY7C1347F-200BZC BB165C CY7C1347F-200AI CY7C1347F-200AI CY7C1347F-200BGI CY7C1347F-200BGI 166 CY7C1347F-166AC CY7C1347F-166AC A101 BG119 BG119 A101 CY7C1347F-166BGC CY7C1347F-166BGC BG119 BG119 CY7C1347F-166BZC CY7C1347F-166BZC BB165C CY7C1347F-166AI CY7C1347F-166AI , CY7C1347F-133BZC CY7C1347F-133BZC BB165C CY7C1347F-133AI CY7C1347F-133AI CY7C1347F-133BGI CY7C1347F-133BGI A101 BG119 BG119 Package Type 100-Lead Thin Quad , ] Feedback CY7C1347F CY7C1347F Package Diagrams (continued) 165-Ball FBGA (15 x 17 x 1.20 mm) BB165C PIN 1 ... | Original |
19 pages, |
CY7C1347F-250BGC CY7C1347F-250AC CY7C1347F-225BGC CY7C1347F-225AC CY7C1347F-200AC CY7C1347F CY7C1347F abstract |
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| Abstract: BB165C CY7C1347F-200AI CY7C1347F-200AI CY7C1347F-200BGI CY7C1347F-200BGI 166 CY7C1347F-166AC CY7C1347F-166AC A101 BG119 BG119 A101 CY7C1347F-166BGC CY7C1347F-166BGC BG119 BG119 CY7C1347F-166BZC CY7C1347F-166BZC BB165C CY7C1347F-166AI CY7C1347F-166AI A101 CY7C1347F-166BGI CY7C1347F-166BGI 133 BG119 BG119 CY7C1347F-133AC CY7C1347F-133AC A101 CY7C1347F-133BGC CY7C1347F-133BGC BG119 BG119 CY7C1347F-133BZC CY7C1347F-133BZC BB165C , (continued) 165-ball FBGA (15 x 17 x 1.20 mm) BB165C 51-85165-* Intel and Pentium are registered ... | Original |
19 pages, |
CY7C1347F-166BGI CY7C1347F CY7C1347F abstract |
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| Abstract: CY7C1347F-200BZC CY7C1347F-200BZC BB165C CY7C1347F-200AI CY7C1347F-200AI CY7C1347F-200BGI CY7C1347F-200BGI 166 CY7C1347F-166AC CY7C1347F-166AC A101 BG119 BG119 A101 CY7C1347F-166BGC CY7C1347F-166BGC BG119 BG119 CY7C1347F-166BZC CY7C1347F-166BZC BB165C CY7C1347F-166AI CY7C1347F-166AI A101 CY7C1347F-166BGI CY7C1347F-166BGI 133 BG119 BG119 CY7C1347F-133AC CY7C1347F-133AC A101 CY7C1347F-133BGC CY7C1347F-133BGC BG119 BG119 CY7C1347F-133BZC CY7C1347F-133BZC BB165C , 1.20 mm) BB165C PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER 1 Ø0.25 M C A B 2 ... | Original |
19 pages, |
CY7C1347F-250BGC CY7C1347F-250AC CY7C1347F-225BGC CY7C1347F-225AC CY7C1347F-200AC CY7C1347F CY7C1347F abstract |
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| Abstract: CY7C1347F-200BZC CY7C1347F-200BZC BB165C CY7C1347F-200AI CY7C1347F-200AI CY7C1347F-200BGI CY7C1347F-200BGI 166 CY7C1347F-166AC CY7C1347F-166AC A101 BG119 BG119 A101 CY7C1347F-166BGC CY7C1347F-166BGC BG119 BG119 CY7C1347F-166BZC CY7C1347F-166BZC BB165C CY7C1347F-166AI CY7C1347F-166AI A101 CY7C1347F-166BGI CY7C1347F-166BGI 133 BG119 BG119 CY7C1347F-133AC CY7C1347F-133AC A101 CY7C1347F-133BGC CY7C1347F-133BGC BG119 BG119 CY7C1347F-133BZC CY7C1347F-133BZC BB165C , ) 165-Ball FBGA (15 x 17 x 1.20 mm) BB165C PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER 1 ... | Original |
19 pages, |
CY7C1347F-250BGC CY7C1347F-250AC CY7C1347F-225BGC CY7C1347F-225AC CY7C1347F-200AC CY7C1347F CY7C1347F abstract |
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| Abstract: CY7C1440AV33 CY7C1440AV33 CY7C1442AV33 CY7C1442AV33 CY7C1446AV33 CY7C1446AV33 PRELIMINARY 36-Mbit (1M x 36/2M 36/2M x 18/512K 18/512K x 72) Pipelined Sync SRAM Functional Description[1] Features · Supports bus operation up to 250 MHz · Available speed grades are 250, 200,167 MHz · Registered inputs and outputs for pipelined operation · 3.3V core power supply · 2.5V/3.3V I/O operation · Fast clock-to-output times - 2.6 ns (for 250-MHz device) - 3.2 ns (for 200-MHz device) - 3.4 ns (for 167-MHz device) · Provide high-perfor ... | Original |
27 pages, |
CY7C1446AV33 CY7C1442AV33 CY7C1440AV33 36/2M 18/512K CY7C1440AV33 abstract |
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| Abstract: CY7C1440AV25 CY7C1440AV25 CY7C1442AV25 CY7C1442AV25 CY7C1446AV25 CY7C1446AV25 PRELIMINARY 36-Mbit (1M x 36/2M 36/2M x 18/512K 18/512K x 72) Pipelined Sync SRAM Functional Description[1] Features · · · · · · · · · · · · · · · Supports bus operation up to 250 MHz Available speed grades are 250, 200,167 MHz Registered inputs and outputs for pipelined operation 2.5V core power supply 2.5V/1.8V I/O supply Fast clock-to-output times - 2.6 ns (for 250-MHz device) - 3.2 ns (for 200-MHz device) - 3.4 ns (for 167- ... | Original |
28 pages, |
CY7C1446AV25 CY7C1442AV25 CY7C1440AV25 36/2M 18/512K CY7C1440AV25 abstract |
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| Abstract: CY7C1481V33 CY7C1481V33 CY7C1483V33 CY7C1483V33 CY7C1487V33 CY7C1487V33 PRELIMINARY Logic Block Diagrams CY7C1481V33 CY7C1481V33 2M x 36 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP Q A[20:0] 21 GW 19 DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS D DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS Q D BWc BWb BWa CE1 CE2 CE3 2M X36 MEMORY ARRAY Q D 21 Q D BWE BW d 19 ADDRESS CE REGISTER D D ENABLE CE R ... | Original |
30 pages, |
CY7C1487V33 CY7C1483V33 CY7C1481V33 CY7C1481V33 abstract |
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