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TPS65901ZQWT Texas Instruments Integrated Power Management IC w/ 3 DC/DCs, 10 LDOs, Audio Codec, USB FS OTG Transceiver, Charger 143-BGA MICROSTAR JUNIOR -30 to 85 visit Texas Instruments
TSI721A1-16GIL Integrated Device Technology Inc FCBGA-143, Tray visit Integrated Device Technology Buy

Assembly Instructions TAI-143

Catalog Datasheet MFG & Type PDF Document Tags

K709

Abstract: TAI-143 ASSEMBLY INSTRUCTIONS AND TOOLS TOOL DIE OR CLOSURE OR LOCATOR SETTING TAI-117 CONTACT: CRIMP , mechanism for the easy identification of tools used for assembly with Trompeter connectors. Typically, all Trompeter engineering control drawings has the appropriate TAI (Trompeter Assembly Instruction) listed on sheet 1. In addition, the appropriate assembly instruction may be stamped on the bag in which the part , TAI-143 CONTACT: SHIELD ASSY: BODY ASSY: TAI-144 CONTACT: SHIELD ASSY: BODY ASSY: TAI
Trompeter Electronics
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K709 TAI-143 TROMPETER Assembly Instructions Assembly Instructions TAI-143 TAI-168 tai-d118 UPL2000 M22520/1-01 M22520/5-01 M22520/1-12 M22520/5- M22520/5-07

spc 8438

Abstract: DSP56600 Specific Combinations of Instructions .3 Predication , demonstrate achievable speed and size points achieved by combining hand-coded assembly and compiled C code , portions of an application to be coded in assembly (versus C) as well as portions to be optimized for , where the encoding of two instructions specified for parallel execution consumes exactly the same number of words as the two instructions would if they executed sequentially. Example 1. Instructions 1
Freescale Semiconductor
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AN1838 spc 8438 DSP56600 DSP16000 DSP56000 SC140 SC140/SC1400

spc 8438

Abstract: DSP16000 , as shown in Formula A-1 in Section A.1.3.3, "The Estimation Formula." A.1.4.3 Instructions That , assembly and compiled C code. The methods and results presented will be of use in making trade-off decisions and in selecting portions of an application to be coded in assembly (versus C) as well as , simple case, the encoding of two instructions, when specified for parallel execution, takes exactly the same number of words as the two instructions would if they were executed sequentially. See Example 1
Motorola
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AN1838/D

GSM starcore

Abstract: 9618E-9 Estimation Formula." A.1.4.3 Instructions That Map One to Three Most DSP56600 instructions that activate , reached by combining hand-coded assembly and compiled C code. The methods and results presented will be , assembly (versus C) as well as portions to be optimized for speed (rather than for size). Based on this , operations. In the simple case, the encoding of two instructions, when specified for parallel execution, takes exactly the same number of words as the two instructions would if they were executed sequentially
Motorola
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GSM starcore 9618E-9

9618E-9

Abstract: 320C62XX Address Registers R8­R15 .2 Specific Combinations of Instructions , by combining hand-coded assembly and compiled C code. The methods and results presented can be of use in making trade-off decisions and in selecting portions of an application to be coded in assembly , operations. Example 1 illustrates a simple case where the encoding of two instructions specified for parallel execution consumes exactly the same number of words as the two instructions would if they
Freescale Semiconductor
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MSC7116 320C62XX

trompeter 14949 coaxial

Abstract: TROMPETER Assembly Instructions AND WRENCH TIGHTEN HEX NUT TD 25 IN LB MAXIMUM INSTALLATION TURQUE ASSEMBLY INSTRUCTIONS BJ226GF , APPROVED CONNECTOR BOOY ASSEMBLY STEP 671 - -CRIMP SLEEVE MIL-SPEC CRIMPING SEALING SL E E V E , TYINAX. TRIAX. OJAORAX COMPONENTS · SYSTEMS B. C. STEP 3 MADE IN USA -CONNECTOR BOOY ASSEMBLY ASSE MB LY INSTRUCTIONS BJ226GF/UBJ246GF "FULL CRIMP" CONNECTORS WITH GROUND FILTERING CAPACITOR TO
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trompeter 14949 coaxial UBJ246 BJ246GF ms2252 trompeter 14949 capacitor tgl MS22520/ M22520/5-0I M22520/5 J225GF/UBJ225GF

AN1716

Abstract: HC12 instruction, the assembly code is quite efficient. Fewer instructions mean smaller programs and fewer memory , consideration in a microelectronic-controlled system, then assembly language and code size will continue to be , : www.freescale.com Freescale Semiconductor, Inc. Application Note How IIA Works Typical IIA mode assembly , brackets around the operands. Converting assembly code to use brackets instead of parentheses is a , JUMP tables appropriate for JSR and JMP instructions: my_table: fdb fdb fdb fdb end_my_table
Freescale Semiconductor
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AN1716 M68HC12 HC12 M68HC11 AN1716/D

MASM16

Abstract: DSA003656 keep instruction execution word-aligned, all CPU16 instructions are either two bytes, four bytes, or , instructions imposes several requirements on software writers. When defining the starting address of a code , 140 of the source code will allow proper assembly of the EXERC_7.ASM file: EVEN This forces the interrupt service routines to begin assembly on a wordaligned boundary. EB306 MOTOROLA 3 N O N - , the percentage of misaligned accesses, all instructions are forced to word boundaries. To add to the
Motorola
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M68HC16Z1EVB MC68HC16 MASM16 DSA003656 M68HC16Z1 EB306/D

ASSEMBLY INSTRUCTIONS Radiall

Abstract: R143018 ASSEMBLY INSTRUCTIONS W asher M01 B ack n u t G asket B ra id c la m p C e n te r C o , RAPIALL*! 26 ASSEMBLY INSTRUCTIONS V -g ro o v e gasket W asher | B raid c la m p C e n te r C o n , «A P IA L L 27 ASSEMBLY INSTRUCTIONS M03 50Q C O N NECTO RS TOOLING R AD IA LL crim p tool R , P . ALL 28 ASSEMBLY INSTRUCTIONS C ab le c la m p B ack n u t in s u la to r C e n te r C o n , . M ount assem bly into body. 13b a d i a l l 29 ASSEMBLY INSTRUCTIONS F e rru le In s u la
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ASSEMBLY INSTRUCTIONS Radiall R143018 Radiall 321 007 000 ASSEMBLY INSTRUCTIONS Radiall crimp 02 Radiall 161 256 000 RRU 32

EB306

Abstract: CPU16 family freescale help programmers and system designers keep instruction execution word-aligned, all CPU16 instructions , ADR0 = 0. Word-alignment of all instructions imposes several requirements on software writers. When , proper assembly of the EXERC_7.ASM file: EVEN This forces the interrupt service routines to begin assembly on a wordaligned boundary. EB306 MOTOROLA 3 For More Information On This Product, Go to , misaligned accesses, all instructions are forced to word boundaries. To add to the indivisibility of
Freescale Semiconductor
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CPU16 family freescale

M68000

Abstract: MCF5307 modifying 68K assembly code to the ColdFire architecture. Freescale Semiconductor, Inc. Based on , (IFP) The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the , eight-instruction FIFO buffer, the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the time stalled waiting for instructions. To maximize the performance of branch instructions, the Version 3 IFP implements a branch prediction mechanism. Backward branches are predicted to
Motorola
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MCF5307 M68000 PC-100 triggering scr with microprocessor AVR remote CONTROLLER seven channel MCF5307PB/D

Alu 181

Abstract: these files. The tool converts only assembly language instructions (either in .asm files or in inline , exactly one of these flags must appear: · -m: manual mode, converts assembly language instructions from , line-by-line and only the inline assembly language instructions are converted. Inline assembly language , assembly instructions in Byte Craft can also begin with the #asm directive and an open parenthesis and end , input data) as input and generates a new file, with all assembly language instructions converted from
Freescale Semiconductor
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Alu 181

PC-100

Abstract: M68000 facilitate modifying 68K assembly code to the ColdFire architecture. Based on the concept of , four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the operand execution , , the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the time stalled waiting for instructions. To maximize the performance of branch instructions, the , , set-associative cache provides pipelined, single-cycle access on cached instructions and operands. As with all
Motorola
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G522-0289-00

Abstract: DH31 ) addresses, integer data types of 8, 16, and 32 bits, and floating- As many as three instructions issued and , many as five instructions in execution implementations, the PowerPC architecture provides additional , issuing and retiring as many as three instructions per clock. - LSU completion appear Instructions can , - Thirty-two FPRs for single- or double-pre instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency · High instruction and data throughput and
Motorola
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G522-0289-00 PPC603 DH31 LOCTITE 223 PPC603 instruction set Nippon capacitors DH27

scr 102 100

Abstract: R143082 Assembly instructions .197 ( 5 ) / 5 0 S. scr. .236 ( 6 ) / 75 R 143 082 161 50Q R 143 085 161* 75Q M03 page 28 Right angle plugs CABLE GROUP PART NUMBER Impedance Assembly instructions .102 ( 2 .6 ) / 5 0 S scr. R 143 181 161» 50Q M10 page 34 CABLE GROUP PART NUMBER Impedance Assembly instructions · Manufactured upon request. .197 (5 )/5 0 S. scr. R 143 182 161 50Q M10 page 34 RADIALI , CRIMP TYPE FOR FLEXIBLE CABLE Straight plugs CABLE GROUP PART NUMBER Impedance Assembly instructions
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scr 102 100 R143082

56800E

Abstract: CG56800E Push and Pop Instructions Example 2 -2. Converting 56800 Assembly Code Using Push and Pop #1 , Instructions to 56800E Instructions . . . . . . . . . . . . . . . . . 2-1 LoadRx, StoreRx, and TestRx Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Push and Pop Instructions . . . . , Use Macros to Convert 56800 or 56800E Assembly Code . . . . . . . . . . . . . . . . . . . . Converting 56800 Assembly Code Using Push and Pop #1 . . . . . . . . . . . . . . . . . . . Converting 56800
Freescale Semiconductor
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CG56800E DSP56800 DSP56800E DSP56800ERM DSP56800FM

MMC2001

Abstract: motorola bubble memory controller Semiconductor, Inc. - - - - - - - - Assembly and disassembly of M·CORE instructions for , - 32-bit RISC architecture, 16-bit instructions - Low power, high performance · OnCETM Debug , instruction execution for most instructions. 2 M·CORE ARCHITECTURAL INFORMATION For More Information On , extension of byte and halfword load data. These instructions can execute in two clock cycles. Load and store multiple register instructions allow low overhead context save and restore operations; these instructions
Motorola
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MMC2001 motorola bubble memory controller 8 bit modified booth multipliers modified booth circuit diagram MMC2001PB/D

Nippon capacitors

Abstract: 617-2455 retiring as many as three instructions per clock. Instructions can execute out of order for increased , system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for PID7v-EC603e~based systems. Most integer instructions execute in one clock cycle. The PID7v-EC603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and
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617-2455 MPE603E7VEC/D EC603 PID6-EC603 MPC603

Nippon capacitors

Abstract: is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the PID7v-EC603e makes completion , execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for PID7v-EC603e­based systems. Most integer instructions execute in , set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory
Motorola
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motorola bubble memory controller

Abstract: MMC2001 following functional units: · M·CORE Integer Processor - 32-bit RISC architecture, 16-bit instructions , fashion, allowing single clock instruction execution for most instructions. 2 M·CORE ARCHITECTURAL , extension of byte and halfword load data. These instructions can execute in two clock cycles. Load and store multiple register instructions allow low overhead context save and restore operations; these instructions , PRODUCT INFORMATION 3 - - - - - - - - Assembly and disassembly of M·CORE
Motorola
Original
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