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DUALOUTPUT-ISOFLYBACK-REF Texas Instruments Dual Output Isolated Flyback Design: 5V @ 0.2A, 12V @ 2.1A w/2 addl out 3.3V @ 0.5A, 5V @ 0.5A visit Texas Instruments
SN74ALS870FN Texas Instruments 16X4 MULTI-PORT SRAM, PQCC28 visit Texas Instruments
SN74172N-10 Texas Instruments 8X2 MULTI-PORT SRAM, PDIP24 visit Texas Instruments
SN74172N Texas Instruments 8X2 MULTI-PORT SRAM, 50ns, PDIP24 visit Texas Instruments
SN74172J-00 Texas Instruments 8X2 MULTI-PORT SRAM, CDIP24 visit Texas Instruments
SN74172N-00 Texas Instruments 8X2 MULTI-PORT SRAM, PDIP24 visit Texas Instruments

ARM dual port SRAM compiler

Catalog Datasheet MFG & Type PDF Document Tags

LCD 18 pin

Abstract: alps 14 pin LCD monochrome connector low power systems for control of SRAM, Flash, and expansion I/O such as Dual Processor CPU with , time 5KB on-chip dual ported SRAM for frame buffer or program/data store Programmable Buzzer PC , HP/UX 9.0. Contains the following programs: · ARM® C Compiler (armcc) · ThumbTM C Compiler (tcc , Controller Piccolo 512Byte I-Cache Color/Mono LCDC 5KB SRAM 8KB Cache Mono LCDC Multi , instruction 512Byte Instruction cache Dual Memory Subsystem Dynamic Memory Control 16 bit wide SDRAM
LinkUp Systems
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NEC-V850

Abstract: DesignWare SPI Max Bits/ Bits Bits Words Word 2-port SRAM (1W/1R), asynchronous 32K 4 512K 256 MZ , Compiler The single-port clocked SRAM compiler creates speed-optimized RAM blocks based on user , Customer Design Center for complete details. Single-Port Clocked SRAM Compiler With Word-Write , and/or written on up to three strobes. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM , implementation with support for multiple test methodologies. The compiler options are: 1-port CRAM area
Texas Instruments
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verilog code for UART with BIST capability

Abstract: VHDL CODE FOR HDLC controller dc power and zero hold times. Table 5: Memories Summary Description 2-port SRAM (1W/1R , 3-port CRAM (2W/1R) 32 144K 4K 128 Single edge CAM compiler 512 128K 1K 128 , Copyright 2000 9 Memories Single-Port Clocked SRAM Compiler The single-port clocked SRAM , complete details. Single-Port Clocked SRAM Compiler With Word-Write, Bit-Write and Multistrobe In , strobes. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM compiler creates area- and
Texas Instruments
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ARM dual port SRAM compiler

Abstract: designware i2c 64K 128 Copyright 2001 Memories Single-Port Clocked SRAM Compiler The single-port clocked SRAM compiler creates speed-optimized RAM blocks based on user specifications. It creates data , for complete details. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM compiler creates , Corporation. DC Professional, DC Expert, DesignPower, DesignWare, Integrator, Power Compiler, PrimeTime, Synopsys, Test Compiler, Test Compiler Plus, and VSS are trademarks of Synopsys, Inc. DETECTOR, GOOD
Texas Instruments
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tv nei schematics

Abstract: ARM dual port SRAM compiler dual ported SRAM for frame buffer or " program/data store $" Programmable Buzzer " " #" PC Card , , separately available from ARM® and LinkUp Systems. The Multi-ICE makes use of a builtin JTAG port, which , 4.1.3 or HP/UX 9.0. Contains the following programs: $ ARM® C Compiler (armcc) $ ThumbTM C Compiler , /Mono LCDC 5KB SRAM 8KB Cache Mono LCD Multi ICE I/F Boot RAM ROM FLASH , . For low power systems, a static memory controller is provided for SRAM, Flash, and expansion I/O such
LinkUp Systems
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verilog code voltage regulator

Abstract: verilog code for 32 bit risc processor Description 2-port SRAM (1W/1R) Max Min Max Max Bits/ Bits Bits Words Word Functionality 32K 2K , 128 Single edge 3-port CRAM (2W/1R) 32 144K 4K 128 Single edge CAM compiler , Compiler The single-port clocked SRAM compiler creates speed-optimized RAM blocks based on user , Customer Design Center for complete details. Single-Port Clocked SRAM Compiler With Word-Write , and/or written on up to three strobes. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM
Texas Instruments
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ternary content addressable memory VHDL

Abstract: ARM dual port SRAM compiler /ARM926EJ/ARM1020E/ETM7/ ETM9 from ARM, TeakLite/TEAK from DSPG - Memories Low-power compiled SRAM , - SPSRAM with Redundancy - up to 1Mbits - Dual Port Synchronous static RAM - up to 128Kbits - , SRAM/ROM with best-density - 1.5V and 3.3V ADC,DAC and PLLs - ARM920T/ARM940T, TeakLite , is 20% less than that of STD150. Each element is provided as a compiler. For high-capacity memory solution in SOC design, the repairable memory containing redundancy scheme is also provided as a compiler
Samsung Electronics
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ternary content addressable memory VHDL ARM dual port SRAM compiler ARM1020E SMART ASIC bga Samsung ASIC 0.13um standard cell library STDL150

16x16x1.4

Abstract: ahb arbiter in mentor / Bits Bits Words Word Functionality Description 2-port SRAM (1W/1R) 32K 4 2K 64 , Memories Single-Port Clocked SRAM Compiler The single-port clocked SRAM compiler creates , Clocked SRAM Compiler With Word-Write, Bit-Write and Multistrobe In addition to the single-port clocked , . Multistrobe allows data to be read and/or written on up to three strobes. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM compiler creates area- and speed-optimized RAM based on user
Texas Instruments
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16x16x1.4 ahb arbiter in mentor

datasheet of BGA Staggered pins

Abstract: NEC-V850 (1W/1R), bit write 1-port CRAM, area optimized, bit write CAM compiler 2-port CRAM (1W/1R , Compiler The single-port clocked SRAM compiler creates speed-optimized RAM blocks based on user , Customer Design Center for complete details. Single-Port Clocked SRAM Compiler With Word-Write , and/or written on up to three strobes. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM , implementation with support for multiple test methodologies. The compiler options are: u 1-port CRAM area
Texas Instruments
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datasheet of BGA Staggered pins NEC-V850 VHDL CODE FOR HDLC controller clock tree balancing vhdl code for 4 channel dma controller 2 port register file

verilog code for 32 bit risc processor

Abstract: vhdl code for usart 3-port CRAM (2W/1R) 144K 1 4K 128 Single edge CAM compiler 128K 2K 1024 , SRAM Compiler The single-port clocked SRAM compiler creates speed-optimized RAM blocks based on user , Customer Design Center for complete details. Single-Port Clocked SRAM Compiler With Word-Write , and/or written on up to three strobes. Dual-Port Clocked SRAM Compiler The dual-port clocked SRAM , implementation with support for multiple test methodologies. The compiler options are: u 1-port CRAM area
Texas Instruments
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verilog code for 32 bit risc processor vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI GS30TR
Abstract: VF6xx - ARM Cortex-A5 (500 MHz) + Cortex-M4 (167 MHz) Dual SVGA LCD, Camera Interface with Video ADC , VF6xx [Heterogeneous Dual Core] Cortex A5 up to 500 MHz Cortex M4 up to 167 MHz Up to 1.5MB SRAM 364 , '¢ 1.5 MB SRAM (ECC support on 512KB) â'¢ NAND flash controller with 32-bit ECC â'¢ Dual Quad SPI , HMI â'¢ Dual TFT LCD up to SVGA resolution Memory â'¢ 32KB I and D L1 Cache â'¢ 1.5MB SRAM with , â'" 500 MHz ARM Cortex-A5 (628 DMIPS) and optional 166 MHz Cortex-M4 (208 DMIPS) On-chip SRAM Freescale Semiconductor
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MPC5606S 24MB/ MPC5645S 64MB/ 160MB/ LK043T1DG02

ARM9TDMI

Abstract: SMART ASIC bga /926EJ /1020E from ARM, TeakLite/TEAK from DSPG - Memories High-density compiled SRAM and repairable , with Bit-Write - up to 256Kbits - SPSRAM with Redundancy - up to 1Mbits - Dual Port Synchronous , , GPIO, SSI, Color LCD controller smart CARD I/F Memory Compiler · Fully compiled high-speed SRAM , Compiled High-density SRAM - 1.2V and 3.3V ADC,DAC and PLLs - ARM920T/ARM940T, TeakLite/TeakHigh-density , elements for high-speed. Each element is provided as a compiler. For highcapacity memory solution in SOC
Samsung Electronics
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STDH150 ARM9TDMI DSPG samsung hdd Samsung S ARM teaklite ARM920T

ARM1020E

Abstract: samsung hdd ASIC Macros Memory Compiler Analog Cores · Fully compiled high-density SRAM · Single-port(1RW, 1R , 1Mbits - Dual Port Synchronous static RAM - up to 128Kbits - DPSRAM with Bit-Write - up to 128Kbits , Compiled High-density SRAM - 1.8V and 3.3V ADC,DAC and PLLs - ARM920T/ARM940T, TeakLite/TeakHigh-density , provided as a compiler. For highcapacity memory solution in SOC design, the repairable memory containing redundancy scheme is provided as a compiler. Samsung ASIC Variety of IPs are provided in STD150 family
Samsung Electronics
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Samsung Soc processor 4468 8 pin ARM920t datasheet UART 16C450 ARM SRAM compiler samsung lvds

ARM dual port SRAM compiler

Abstract: DSPG ASIC Macros Memory Compiler Analog Cores · Fully compiled high-density SRAM · Single-port(1RW, 1R , 1Mbits - Dual Port Synchronous static RAM - up to 128Kbits - DPSRAM with Bit-Write - up to 128Kbits , Compiled High-density SRAM - 1.8V and 3.3V ADC,DAC and PLLs - ARM920T/ARM940T, TeakLite/TeakHigh-density , provided as a compiler. For highcapacity memory solution in SOC design, the repairable memory containing redundancy scheme is provided as a compiler. Samsung ASIC Variety of IPs are provided in STD150 family
Samsung Electronics
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usb dspg jtag Standard Cell 0.13um System-On-Chip ASIC 0.13Um ST 0.18Um Standard cell ST adc vhdl

8052 instruction set

Abstract: 8052 microcontroller on-chip with both blocks mapped into a single linear array. ARM code can run directly from SRAM at 45 MHz , 3-phase PWM, PLA, and 62 kbytes Flash/EE, plus 8 kbytes SRAM · 8052 MicroConverter® series with , -bit bus for instructions and data, integrate a JTAG test port for debug access, and operate at 45 MHz maximum. In addition to the 32-bit ARM instruction set, the core supports an instruction set that is , integrate an industry-standard MCU core, the 8052, with Flash memory, precision analog I/O, and dual 24
Analog Devices
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8052 instruction set 8052 microcontroller ADuC7000 8052 Tutorial arm7 tdmi 5 8052 microcontroller philips C7000 F-92182 BR04809-6-3/04

Philips LPC2138 reference manual

Abstract: IAR UART example code LPC2138 microcontroller with 512 KByte program Flash and 32 KByte SRAM, or Philips ARM7TDMI LPC2132 microcontroller with 64 KByte program Flash and 16 KByte SRAM · All LPC213x I/O pins are available on connectors , form factor for easy integration - Dual 2x16 pins I/O connectors - Four layer PCB (FR , User's Guide 2.3.5 Page 14 LEDs The port pins of the LPC213x microcontrollers have a 4 mA , . The preloaded test program (described in Section 3.1 ) outputs a running-zero on all the port pins
Embedded Artists
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Philips LPC2138 reference manual IAR UART example code LPC2138 ARM LPC2138 embedded C language UM10120 uart lpc214x ARM LPC2124 embedded C language LPC213 EA2-USG-0504 SE-214 DDI0029G DDI0100E

IAR WE SCANF CODE EXAMPLES

Abstract: LPC21ISP with 128 Kbyte program Flash and 64 Kbyte SRAM · All LPC2106 I/O pins are available on , 's Guide Page 7 Besides the LPC2106 microcontroller from Philips, the board contains a dual voltage , . Figure 8 ­ Example SPI Interface 2.3.5 LEDs The port pins of the LPC2106 microcontrollers have a , 13 on the port pins (P0.4 ­ P0.31), in order to create a running-one pattern on the LEDs. A , the one found in Figure 9, can be used to attach LEDs to port pins P0.4 ­ P0.31. Pins P0.0 ­ P0.1 are
Embedded Artists
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LPC2000 IAR WE SCANF CODE EXAMPLES LPC21ISP manual lpc2119 DIL40 can controller in lpc2129 DDI0029G, ARM7TDMI Technical Reference Manual RS232 EA2-USG-0501

AF11 Transistors

Abstract: D740 shared (PARM) between mAgic and the ARM processor. It is a dual port memory 512 words by 40- bit for , Features · Dual Core System Integrating an ARM7TDMI ARM Thumb Processor Core and a mAgic DSP for , 1149.1 JTAG Boundary Scan on all Active Pins Efficient ARM - DSP Interface Based on 1K x 40-bit Dual , Program Memory, the Data Memory, the Data Buffer, and the dual ported memory shared with the ARM , words by 128-bit single port memory. When mAgic is in System Mode the ARM can modify the content of the
Atmel
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AF11 Transistors D740 ARM pin configuration AT572D740 ATMEL 740 ARMA FUNCTION SIGNAL GENERATOR 7001AS

VHDL CODE FOR PID CONTROLLERS

Abstract: ARM JTAG Programmer Schematics Memory Setting the SRAM Speed and Width Setting the EPROM/Flash Speed and Width Parallel Port/LED mode , macrocell is programmed in serial through the Test Access Port (TAP) controller on the ARM, via the JTAG , channels. It is easy to port to different hardware. It requires control over the ARM's exception vectors , if no other communications port is available. Only requires the JTAG interface to the ARM , connection Connect your host computer to the Serial A port on the ARM Development Board using a 9-pin RS232
ARM
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VHDL CODE FOR PID CONTROLLERS ARM JTAG Programmer Schematics serial programmer schematic diagram for arm 7tdmi APS 226 PSU vhdl code for rs232 receiver using fpga application HBI-0011B VG-468

ARM dual port SRAM compiler

Abstract: synopsys dc ultra - SPSRAM with Redundancy - up to 1M bits - Dual Port Synchronous static RAM - up to 256K bits - , drive and 3.3/5V tolerant I/O - Compilable SRAM for two different application - 1.8V and 3.3V ADC,DAC , compiler. For high-capacity memory solution in SOC design, the repairable Samsung ASIC memory containing redundancy scheme is provided as a compiler. Variety of IPs are provided in STD130 family including - Processor Cores : ARM7T/ARM9T/940T/920T from ARM, Teaklite/TEAK from DSPG - Memories
Samsung Electronics
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synopsys dc ultra rm2510 16C450 16C550 ARM940T IEEE1284
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