Datasheet Search Results			1 - 4 of about 4 for APEX20KE
	APEX 20KE	Altera Corporation	New APEX 20KE Device Ordering Codes	79.87 Kb,  2 Pages.
	APEX 20KE	Altera Corporation	APEX 20KE PCI Development Board Data Sheet	427.62 Kb,  40 Pages.
	APEX 20KE	Altera Corporation	SB 55: APEX 20KE PCI Starter & Development Kit	762.02 Kb,  3 Pages.
	APEX20KE	Altera Corporation	PIB 29: LVDS Comparision: APEX 20KE vs. Virtex-E Devices	285.96 Kb,  24 Pages.

Fulltext Datasheet Results		1 - 50 of about 71 for APEX20KE
	First line: 10/100Mbps Ethernet Core with Avalon Interface Product Brief Version November 2003 Ethernet available different speeds (10/100/1000 10000Mbps) provides connectivity meet wide range needs from desktop switches. MorethanIP solutions provide solution each Ethernet application with library configurable Abstract: .. APEX20KE -2 4200 54080 50 MHz. STRATIX -7 4100 54080 130 MHz. CYCLONE -8 4100 54080 130MHz 130MHz . 10/100Mbps 100Mbps Ethernet MAC Core. with Avalon Interface. Product Brief. Version 3.3 - November 2003. 6. 6 10/100Mbps 100Mbps ..  Tags: rx data path interface in vhdl  frame by vhdl  Ethernet-MAC  ethernet phy  avalon vhdl  APEX20KE  altera rgmii specification   datasheet abstract..	67.39 Kb	8 Pages	Original
	First line: DPRAM Configurable Controller 1.01 stand-alone controller Controller Area Network (CAN) widely used automotive industrial applications. conforms Bosch 2.0B specification (2.0B Active). Core simple interface (8/16/32 configurable data width) with little endian adressing scheme. Hardware message filte Abstract: .. APEX20KE -1 1956 + 2 ESB 83 MHz. APEX20K APEX20K -1 1956 + 2 ESB 66 MHz. ACEX1K -1 1956 + 2 ESB 66 MHz. FLEX10KE FLEX10KE -1 1956 + 2 ESB 66 MHz. 8-bit CPU Core performance in ALTERA ® devices. Device. Speed grade Logic Cells Fmax ..  Tags: DPRAM FLEX10KE  APEX20KE  A1600   datasheet abstract..	109.38 Kb	3 Pages	Original
	First line: Mbps Dual-Speed Ethernet (Media Access Controller) Alcatel PE-MACMIITM module Mbps Ethernet Media Access Controller (MAC) designed with several features including wide support Physical layer devices dual Mbps Mbps operating speeds. This core technology originally shipped 1995, currently shipping sil Abstract: .. Device Family APEX20K APEX20K APEX20KE. Device Used EP20K400FC672-1 EP20K400FC672-1 EP20K400EFC672-1 EP20K400EFC672-1 . Logic Cell Usage1. 1807 1805. EAB/ESB Usage. 0 0. Fmax2 52 61. Core I/O Count3. 223 223. Included with MACMII Core Documentation ..  Tags: Ethernet-MAC  A1600   datasheet abstract..	19.23 Kb	1 Pages	Original
	First line: Mbps Dual-Speed Ethernet (Media Access Controller) Alcatel PE-MACMIITM module Mbps Ethernet Media Access Controller (MAC) designed with several features including wide support Physical layer devices dual Mbps Mbps operating speeds. This core technology originally shipped 1995, currently shipping sil Abstract: .. Device Family APEX20K APEX20K APEX20KE. Device Used EP20K400FC672-1 EP20K400FC672-1 EP20K400EFC672-1 EP20K400EFC672-1 . Logic Cell Usage1. 1787 1784. EAB/ESB Usage. 0 0. Fmax2 25+ 25+ Core I/O Count3. 223 223. Included with MACMII Core Documentation ..  Tags: Ethernet-MAC  A1600   datasheet abstract..	18.88 Kb	1 Pages	Original
	First line: Interfacing QDRTM with Altera APEX20KE QDRTM: Introduction evolution newer systems increased demands speed performance. result this, faster processors have emerged that have increased demands memory performance. Newer memory architectures with higher through-put have been designed that support curre Abstract: .. Interfacing the QDRTM with Altera APEX20KE. Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600 March 12, 2001. QDRTM: An Introduction The evolution of ..  Tags:   APEX20KE	93.11 Kb	7 Pages	Original
	First line: Interfacing QDRTM with Altera APEX20KE QDRTM: Introduction evolution newer systems increased demands speed performance. result this, faster processors have emerged that have increased demands memory performance. Newer memory architectures with higher through-put have been designed that support curre Abstract: .. Interfacing the QDRTM with Altera APEX20KE. Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600 March 12, 2001. QDRTM: An Introduction The evolution of ..  Tags: APEX20KE   APEX20KE	87.61 Kb	7 Pages	Original
	First line: ACEX1K 10/100/1000Mbps Ethernet Core Reference Guide Version July 2002 Ethernet available different speeds (10/100/1000 10000Mbps) provides connectivity meet wide range needs from desktop switches. MorethanIP solutions provides solution each Ethernet application with library configurable (Medium Acc Abstract: .. Source code option for Altera CPLDs ACEX1K, APEX20KE, APEX-II or STRATIX or ASIC implementations. ALTR. Encrypted netlist for Altera CPLDs ACEX1K, APEX20KE, APEX-II or STRATIX . 5. 10/100 ..  Tags: ACEX1K Ethernet-MAC  ethernet phy  altera rgmii specification  1gbps serdes   datasheet abstract..	147.54 Kb	6 Pages	Original
	First line: 10/100/1000Mbps Ethernet with Protocol Acceleration MAC-NET Core with Avalon Interface Product Brief Version February 2004 Ethernet available different speeds (10/100/1000 10000Mbps) provides connectivity meet wide range needs from desktop switches. MorethanIP solutions provide solution each Etherne Abstract: .. Source code option for Altera CPLDs APEX20KE, CYCLONE, APEX-II, STRATIX or STRATIX GX or ASIC implementations. ALTR. Encrypted netlist for Altera CPLDs APEX20KE, APEX-II, CYCLONE, STRATIX ..  Tags: Ethernet-MAC  ethernet mac chip  ethernet mac  avalon vhdl   datasheet abstract..	74.5 Kb	9 Pages	Original
	First line: Compliant with IEEE 1284- 2000 parallel interface protocol standard ECP_Slave Extended Capabilities Parallel Port Slave Megafunction Abstract: .. Apex20KE EP20K100-2 EP20K100-2 . 501 92 71. Apex20KC Apex20KC EP20K200-8 EP20K200-8 . 503 92 90. ApexII EP2A-8. 504 92 110. Cyclone ..  Tags:   datasheet abstract..	536.13 Kb	2 Pages	Original
	First line: DFPSQRT Floating Point Pipelined Square Root Unit 2.90 DFPSQRT uses pipelined mathematics algorithm compute square root function. input number format according IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT operation pipelined levels. Input data every clock cycle. first resu Abstract: .. APEX20KE -1 970 53 MHz. APEX20KC APEX20KC -7 970 62 MHz. APEX-II -7 970 83 MHz. MERCURY -5 975 99 MHz. STRATIX -5 725 96 MHz. CYCLONE -6 725 94 MHz. STRATIX-II -3 890 131 MHz. CYCLONE-II -6 730 99 MHz. Core performance in ..  Tags: A1600   datasheet abstract..	106.8 Kb	3 Pages	Original
	First line: DFP2INT Floating Point Integer Pipelined Converter 2.20 DFP2INT pipelined floating point integer converter. input output numbers format according IEEE-754 standard. DFP2INT supports single precision real numbers double word integers Bytes). Convert operation pipelined levels. Input data every clock Abstract: .. APEX20KE -1 295 67 MHz. APEX20KC APEX20KC -7 295 88 MHz. APEX-II -7 295 114 MHz. MERCURY -5 270 208 MHz. STRATIX -5 245 184 MHz. CYCLONE -6 245 165 MHz. STRATIX-II -3 185 214 MHz. CYCLONE-II -6 265 133 MHz. Core performance ..  Tags:   datasheet abstract..	98.81 Kb	3 Pages	Original
	First line: DFPDIV Floating Point Pipelined Divider Unit 2.15 DFPDIV uses pipelined mathematics algorithm divide arguments. input numbers format according IEEE754 standard. DFPDIV supports single precision real number. Divide operation pipelined levels. Input data every clock cycle. first result appears after c Abstract: .. APEX20KE -1 2720 40 MHz. APEX20KC APEX20KC -7 2720 42 MHz. APEX-II -7 2720 50 MHz. MERCURY -5 2780 65 MHz. STRATIX -5 2270 88 MHz. CYCLONE -6 2270 86 MHz. STRATIX-II -3 2040 104 MHz. Core performance in ALTERA ® devices ..  Tags: ieee floating point vhdl   IEEE754	98.69 Kb	3 Pages	Original
	First line: DFPMUL Floating Point Pipelined Multiplier Unit 2.70 DFPMUL uses pipelined mathematics algorithm multiply arguments. input numbers format according IEEE754 standard. DFPMUL supports single precision real number. Multiply operation pipelined levels. Input data every clock cycle. first result appears Abstract: .. APEX20KE -1 1210 50 MHz. APEX20KC APEX20KC -7 1210 51 MHz. APEX-II -7 1210 67 MHz. MERCURY -5 1290 77 MHz. STRATIX -5 440+8M1 93 MHz. CYCLONE -6 1170 72 MHz. STRATIX-II -3 410+8M1 134 MHz. CYCLONE-II -6 480+8M1 117 MHz ..  Tags: ieee floating point vhdl  digital clock vhdl code  A1600   IEEE754	99.17 Kb	3 Pages	Original
	First line: DINT2FP Integer Floating Point Pipelined Converter 2.32 DINT2FP pipelined integer floating point converter. input output numbers format according IEEE-754 standard. DINT2FP supports double word integers Bytes) single precision real numbers. Convert operation pipelined levels. Input data every clock Abstract: .. APEX20KE -1 470 73 MHz. APEX20KC APEX20KC -7 470 87 MHz. APEX-II -7 470 103 MHz. MERCURY -5 570 157 MHz. STRATIX -5 400 150 MHz. CYCLONE -6 385 156 MHz. STRATIX-II -3 330 234 MHz. CYCLONE-II -6 410 149 MHz. Core performance ..  Tags: A1600   datasheet abstract..	94.28 Kb	2 Pages	Original
	First line: DFPADD Floating Point Pipelined Adder Unit 2.50 DFPADD uses pipelined mathematics algorithm compute arguments. input numbers format according IEEE-754 standard. DFPADD supports single precision real number. operation pipelined levels. Input data every clock cycle. first result appears after clock pe Abstract: .. APEX20KE -1 955 52 MHz. APEX20KC APEX20KC -7 955 68 MHz. APEX-II -7 955 88 MHz. MERCURY -5 975 117 MHz. STRATIX -5 845 107 MHz. CYCLONE -6 845 104 MHz. STRATIX-II -3 690 153 MHz. CYCLONE-II -6 845 105 MHz. Core performance ..  Tags: ieee floating point vhdl   IEEE754	98.86 Kb	3 Pages	Original
	First line: DI2CSB Interface Slave Base version 1.15 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CSB provides interface between passive target device e.g. memory, display, pressure sensors etc. bus. works slave receiver tra Abstract: .. APEX20KE -1 95 130 MHz. APEX20K APEX20K -1 95 94 MHz. ACEX1K -1 95 99 MHz. FLEX10KE FLEX10KE -1 95 95 MHz. MAX 7000AE 7000AE -4 50 107 MHz. MAX 3000A 3000A -4 50 107 MHz. MAX II -3 75 154 MHz. Core performance in ALTERA ® devices. The main features ..  Tags: vhdl source code for i2c memory (read and write)  vhdl code for i2c  verilog code for transmission line   DI2CSB	105.74 Kb	4 Pages	Original
	First line: DI2CS Interface Slave 3.02 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CS core provides interface between microprocessor /microcontroller bus. works slave transmitter slave receiver depending working mode determ Abstract: .. APEX20KE -1 170 120 MHz. APEX20K APEX20K -1 170 90 MHz. ACEX1K -1 170 107 MHz. FLEX10KE FLEX10KE -1 170 107 MHz. MAX 7000AE 7000AE -5 83 96 MHz. MAX 3000A 3000A -5 83 104 MHz. Control Register – Contains five control bits used for performing ..  Tags: verilog code for transmission line   DI2CS	109.27 Kb	4 Pages	Original
	First line: D8259 Programmable Interrupt Controller 1.04 D8259 soft Core Programmable Interrupt Controller. fully compatible with 82C59A device. D8259 Core manages 8-vectored priority interrupts processor. Programming cascade allows vectored interrupts. More than vectored interrupts accomplished programming Pol Abstract: .. APEX20KE -1 407 93 MHz. APEX20K APEX20K -1V 407 72 MHz. ACEX1K -1 413 78 MHz. FLEX10KE FLEX10KE -1 413 76 MHz. Core performance in ALTERA ® devices. All trademarks mentioned in this document are trademarks of their respective ..  Tags: processor 8088  MCS-80/85  MCS-80  interrupt controller vhdl code download  d8259  D8254  applications of 8259  82C59A  8259 Programmable Interrupt Controller  8259   MCS-80 85	105.42 Kb	4 Pages	Original
	First line: Voice encryption AES chips Simplex Encryption/Decryption Cores CS5265/75 Abstract: .. Table 3: CS5265 CS5265 / CS5275 CS5275 Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHz DATA RATE MBITS/Sec CS5265AA CS5265AA 1666 ..  Tags: AES chips Voice encryption Northern Design (Electronics)  cs3500  asic   CS5265 75	196.04 Kb	6 Pages	Original
	First line: High Performance OCB-AES Simplex Encryption/Decryption Cores CS5331-32 Abstract: .. Table 5: CS5331-32 CS5331-32 Family Programmable Logic Core Using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHz DATA RATE MBITS/Sec a. a. Sustained ..  Tags: Voice encryption  pin diagram decoder 4511  hardware AES controller  cs5332  cs3500  ARK MOTION  Amphion Semiconductor  AES chips   CS5331-32	193.53 Kb	7 Pages	Original
	First line: CS5321-CS5322 AES chips CS5321-22 High Performance OCB-AES Encryption Cores CS5321-22 Abstract: .. Table 5: CS5321-CS5322 CS5321-CS5322 Programmable Logic Cores Using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CLOCK SPEED MHz DATA RATE MBITS/Sec CS5321AA CS5321AA 3322 8 46 136. CS5322AA CS5322AA 3605 ..  Tags: CS5321-22 CS5321-CS5322 hardware AES controller  ARK MOTION  Amphion Semiconductor  AES chips   CS5321-22	186.62 Kb	6 Pages	Original
	First line: DI2CM Interface Master 3.02 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CM core provides interface between microprocessor microcontroller bus. work master transmitter master receiver depending working mode deter Abstract: .. APEX20KE -1 290 160 MHz. APEX20K APEX20K -1 290 120 MHz. ACEX1K -1 290 130 MHz. FLEX10KE FLEX10KE -1 290 140 MHz. MAX 7000AE 7000AE -5 149 64 MHz. MAX 3000A 3000A -7 149 47 MHz. Core performance in ALTERA ® devices. All trademarks mentioned ..  Tags: DI2CM   DI2CM	142.79 Kb	6 Pages	Original
	First line: DI2CMS Interface Master/Slave 1.01 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CMS core provides interface between microprocessor microcontroller bus. work master slave transmitter/receiver depending working mod Abstract: .. APEX20KE -1 394 120 MHz. APEX20K APEX20K -1 394 90 MHz. ACEX1K -1 411 107 MHz. FLEX10KE FLEX10KE -1 411 107 MHz. MAX 2 -3 291 187 MHz. MAX 7000AE 7000AE -5 198 67 MHz. MAX 3000A 3000A -7 198 49 MHz. Core performance in ALTERA ® devices. DI2CMS ..  Tags:   DI2CMS	116.97 Kb	6 Pages	Original
	First line: vhdl code for accumulator D68000 16/32-bit Microprocessor 1.15 D68000 soft core binary-compatible with industry standard 68000 32-bit microcontroller. D68000 16-bit data 24-bit address data bus. code compatible with MC68008 upward code compatible with MC68010 virtual extensions MC68020 32-bit implem Abstract: .. APEX20KE -1 6332 32 MHz. APEX20KC APEX20KC -7 6332 37 MHz. APEX-II -7 6657 40 MHz. MERCURY -5 7086 45 MHz. STRATIX -5 6862 49 MHz. CYCLONE -6 6604 44 MHz. Core performance in ALTERA ® devices. C O N T A C T S For any modification ..  Tags: vhdl code for accumulator mc68010  MC68008  D68000*   MC68008 MC68010 MC68020	107.75 Kb	4 Pages	Original
	First line: DFPMU Floating Point Coprocessor 2.05 DFPMU Floating Point Coprocessor, designed assist performing floating point mathematic computations. DFPMU directly replaces software functions, equivalent, very fast hardware operations, which significantly accelerate system performance. doesn't require program Abstract: .. APEX20KE -1 5150 50 MHz. APEX20KC APEX20KC -7 5150 58 MHz. APEX-II -7 5150 73 MHz. CYCLONE -6 4650 90 MHz. CYCLONE-II -6 4520 96 MHz. STRATIX -5 4460 108 MHz. STRATIX-II -3 3300 168 MHz. Core performance in ALTERA ® devices ..  Tags: vhdl code for cordic  CORDIC   DP8051	110.47 Kb	5 Pages	Original
	First line: DSPIS DSPIS Serial Peripheral Interface -Slave 1.01 DSPIS fully configurable slave device, designated operate with passive devices like memories, drivers etc. DSPIS allows user configure polarity phase serial clock signal SCK. serial clock line (SCK) synchronizes shifting sampling information indepe Abstract: .. APEX20KE -1 82 202 MHz. APEX20K APEX20K -1 82 140 MHz. ACEX1K -1 87 196 MHz. FLEX10KE FLEX10KE -1 87 204 MHz. MAX2 -3 79 257 MHz. MAX3K -5 57 114 MHz. MAX7K -5 57 114 MHz. Core performance in ALTERA ® devices. T r a n s f e r F o r m a t s. Software ..  Tags: DSPIS APEX20KE   datasheet abstract..	113.63 Kb	5 Pages	Original
	First line: DPRAM Media Access Controller 2.07 hardware implementation media access control protocol defined IEEE standard. cooperation with external device enables network functionality design. capable transmitting receiving Ethernet frames from network. Half full duplex modes supported, well Mbit/s speed. cor Abstract: .. APEX20KE -1 1622 + 4 kB RAM 108 / 99 / 111. APEX20K APEX20K -1 1622 + 4 kB RAM 86 / 87 / 88. Core performance in ALTERA ® devices. All trademarks mentioned in this document are trademarks of their respective owners ..  Tags: DPRAM   CRC-32	106.89 Kb	4 Pages	Original
	First line: DI2CM Interface Master 3.08 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CM core provides interface between microprocessor microcontroller bus. work master transmitter master receiver depending working mode deter Abstract: .. APEX20KE -1 268 160 MHz. APEX20K APEX20K -1 268 122 MHz. ACEX1K -1 287 135 MHz. FLEX10KE FLEX10KE -1 287 140 MHz. MAX 2 -3 241 187 MHz. MAX 7000AE 7000AE -5 137 67 MHz. MAX 3000A 3000A -7 137 49 MHz. Core performance in ALTERA ® devices. The main ..  Tags: DI2CM   DI2CM	114.55 Kb	5 Pages	Original
	First line: DFPAU Floating Point Arithmetic Coprocessor 2.05 DFPAU Floating Point Arithmetic Coprocessor, designed assist performing floating point arithmetic computations. DFPAU directly replaces software functions, equivalent, very fast hardware operations, which significantly accelerate system performance. d Abstract: .. APEX20KE -1 2640 48 MHz. APEX20KC APEX20KC -7 2640 57 MHz. APEX-II -7 2640 70 MHz. CYCLONE -6 2410 91 MHz. CYCLONE-II -6 2280 96 MHz. STRATIX -5 2210 115 MHz. STRATIX-II -3 1680 169 MHz. Core performance in ALTERA ® devices ..  Tags:   DP8051	109.92 Kb	5 Pages	Original
	First line: Ethernet-MAC ic BCM5221 MIC29302BU BCM5221KPT mj-179p CM71-10401-1E FAMILY EVALUATION BOARD MB91401 Abstract: .. Device : APEX20KE EP20K1000EFC33-1X EP20K1000EFC33-1X PKG Type : 1020 pin Fine Line BGA Power supply voltage : I/O +3.3 V, Core +1.8 V. TDI TMS TDO. TCK. JTAG Pin header. Serial Configuration Mode. TDI TMS. TDO. TCK J3. J2 ..  Tags: mj-179p BCM5221KPT MIC29302BU BCM5221 Ethernet-MAC ic   MB91401	174.57 Kb	28 Pages	Original
	First line: High Performance Decryption Cores CS5250-80 Abstract: .. Table 4: CS5250-80 CS5250-80 Family of Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHZ DATA RATE MBITS/Sec CS5250AA CS5250AA ..  Tags:   CS5250-80	514.63 Kb	8 Pages	Original
	First line: High Performance Encryption Cores CS5210-40 Abstract: .. Table 4: CS5210-40 CS5210-40 Family of Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHz DATA RATE MBITS/Sec CS5210AA CS5210AA ..  Tags: cs6100  CS5210-40   CS5210-40	509.81 Kb	8 Pages	Original
	First line: DES/3DES Encryption/Decryption Cores CS5010-40 Abstract: .. Table 4: CS5010-40 CS5010-40 DES/3DES Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE CYCLES PER OPERATION. TIMING CONSTRAINT MHz DES DATA RATE MBITS/SEC. 3DES DATA RATE ..  Tags: DES Encryption  CS5040   CS5010-40	529.44 Kb	8 Pages	Original
	First line: D16450 Configurable UART 2.07 D16450 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C450. D16450 performs serial-to-parallel conversion data characters received from peripheral device MODEM, parallel-to-serial conversion data characters received from CPU. rea Abstract: .. APEX20KE -1 340 122 MHz. APEX20K APEX20K -1 340 83 MHz. ACEX1K -1 363 99 MHz. FLEX10KE FLEX10KE -1 363 98 MHz. Core performance in ALTERA ® devices. D 1 6 X 5 0 U A R T S F A M I L Y O V E R V I E W. The family of DCD D16X50 D16X50 UART IP Cores combine ..  Tags: vhdl code for 8 bit ODD parity generator  verilog code for uart communication  datasheet of 16450 UART  D16754  APEX20KE  a VHDL description for an 8-bit even/odd parity c   TL16C450	129.84 Kb	6 Pages	Original
	First line: DSPI Serial Peripheral Interface Master/Slave 2.07 fully configurable master/slave device, which allows user configure polarity phase serial clock signal SCK. allows microcontroller communicate with serial peripheral devices. also capable interprocessor communications multi-master system. serial clo Abstract: .. APEX20KE -1 196 169 MHz. APEX20K APEX20K -1 196 135 MHz. ACEX1K -1 205 156 MHz. FLEX10KE FLEX10KE -1 205 156 MHz. MAX2 -3 181 209 MHz. MAX3K -5 119 96 MHz. MAX7K -5 119 96 MHz. Core performance in ALTERA ® devices. All trademarks ..  Tags: DSPI A1600   SS7O SS0O	90.2 Kb	6 Pages	Original
	First line: DSPI_FIFO Serial Peripheral Interface Master/Slave with FIFO 1.07 DSPI_FIFO fully configurable master/slave device, which allows user configure polarity phase serial clock signal SCK. DSPI_FIFO allows microcontroller communicate with serial peripheral devices. also capable interprocessor communicati Abstract: .. APEX20KE -1 369 115 MHz. APEX20K APEX20K -1 369 94 MHz. ACEX1K -1 369 103 MHz. FLEX10KE FLEX10KE -1 369 103 MHz. Core performance in ALTERA ® devices. T r a n s f e r F o r m a t s. Software can select any of four combinations of serial ..  Tags: A1600   SS7O SS0O	91.93 Kb	6 Pages	Original
	First line: phase shift oscillator transistor P2P testbench of a transmitter in verilog Using APEX APEX 20KE PLLs Quartus Software Abstract: .. The altclklock behavioral model can be used to simulate both the APEX20K APEX20K PLL and the APEX20KE PLL by generating a clock signal based upon a reference clock. The APEX 20K and APEX 20KE 20KE behavioral ..  Tags: testbench of a transmitter in verilog transistor P2P phase shift oscillator   datasheet abstract..	585.13 Kb	20 Pages	Original
	First line: Using APEX APEX 20KE PLLs Quartus Software Abstract: .. The altclklock behavioral model can be used to simulate both the APEX20K APEX20K PLL and the APEX20KE PLL by generating a clock signal based upon a reference clock. The APEX 20K and APEX 20KE 20KE behavioral ..  Tags:   datasheet abstract..	507.6 Kb	20 Pages	Original
	First line: SHA-256 CS5311 CS5312* Standard Hash Algorithm (SHA-1 SHA-2) Cores CS5310/11/12 Abstract: .. Table 7: CS5311 CS5311 Programmable Logic Core Using Altera APEX20KE-1. PRODUCT ID. LOGIC USED LEs MEMORY USED. ESB CYCLES PER OPERATION. TIMING. CONSTRAINT MHz SUSTAINED DATA THROUGHPUT Gbps ..  Tags: CS5311 SHA-256 CS5312*  CS5265*  CS5210   CS5310 11 12	207.15 Kb	12 Pages	Original
	First line: wavelet 128x128 Discrete Wavelet Transform CS6210 Abstract: .. CS6210AA CS6210AA Altera Apex20KE 47 7381 LEs 24 ESBs Now. CS6210XE CS6210XE Xilinx VirtexE-8 55 3784. SLICES 24 BRAMs Now. CS6210 CS6210 Discrete Wavelet Transform. TM. Virtual Components for the Converging World. CORPORATE ..  Tags: wavelet 128x128   CS6210	320.54 Kb	11 Pages	Original
	First line: Mentor Graphics ModelSim Support QII53001-7.1.0 Altera® software subscription includes license ModelSim-Altera software UNIX platform. ModelSim-Altera software used perform functional register transfer level (RTL), post-synthesis, gate-level timing simulations either Verilog VHDL designs that ta Abstract: .. apex20ke Precompiled library for APEX 20KC 20KC , APEX 20KE 20KE , and ExcaliburTM device designs. mercury Precompiled library for MercuryTM device designs. flex10ke flex10ke Precompiled library for FLEX ® ..  Tags: intel atom  Gate level simulation without timing  flex6000 figure  Date Code Formats Altera  cycloneIII  altera Date Code Formats  alt2gxb   QII53001-7	826.28 Kb	54 Pages	Original
	First line: Scripting with Quartus Software Application Note Abstract: .. where: <family name> = APEX20K APEX20K , APEX20KE <device name> = any valid device in the specified family. Add Pinout. To add a pin assignment, use the following Tcl command. cmp add_assignment <chip_name ..  Tags:   datasheet abstract..	207.68 Kb	16 Pages	Original
	First line: DRPIC1655X High Performance Configurable 8-bit RISC Microcontroller 2.15 DRPIC1655X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast (typically onchip) dual ported memory. core been designed with special concern about power consumption. DRPIC1655X soft core so Abstract: .. APEX20KE -1 1131 70 MHz. APEX20K APEX20K -1 1131 41 MHz. ACEX1K -1 1150 64 MHz. FLEX10KE FLEX10KE -1 1150 59 MHz. Core performance in ALTERA ® devices. Area utilized by the each unit of DRPIC1655X DRPIC1655X core in vendor specific ..  Tags: vhdl code for usart  PIC16C55X  PIC16C554   PIC16C554 PIC16C558	139.88 Kb	8 Pages	Original
	First line: DF6811CPU 8-bit FAST Microcontrollers Family 2.17 Document contains brief description DF6811CPU core functionality. DF6811CPU advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6811CPU soft core binarycompatible with industry standard 68HC11 8-bit microcontroller achieve Abstract: .. APEX20KE -1 1809 42 MHz. ACEX1K -1 1785 34 MHz. FLEX10KE FLEX10KE -1 1785 32 MHz. Core performance in ALTERA ® devices. I M P R O V E M E N T For user the most important is application speed improvement. The most commonly ..  Tags: arithmetic instruction for microcontroller 68HC11   DF6811CPU	145.17 Kb	7 Pages	Original
	First line: DF6808 8-bit FAST Microcontrollers Family 1.04 Document contains brief description DF6808 core functionality. DF6808 advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6808 soft core binary-compatible with industry standard 68HC08 8-bit microcontroller achieve performance Abstract: .. APEX20KE -1 2531 41 MHz. ACEX1K -1 2536 36 MHz. FLEX10KE FLEX10KE -1 2536 36 MHz. Core performance in ALTERA ® devices. Area utilized by the each unit of DF6808 DF6808 core in vendor specific technologies is summarized ..  Tags: verilog code for uart communication   DF6808 DF6808	158.61 Kb	9 Pages	Original
	First line: DFPIC1655X High Performance Configurable 8-bit RISC Microcontroller 2.02 DFPIC1655X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast memory (typically on-chip). core been designed with special concern about power consumption. DFPIC1655X software compatible wit Abstract: .. APEX20KE -1 739 56 MHz. APEX20K APEX20K -1 739 50 MHz. ACEX1K -1 804 39 MHz. FLEX10KE FLEX10KE -1 804 38 MHz. Core performance in ALTERA ® devices. I M P R O V E M E N T Most instruction of DFPIC1655X DFPIC1655X is exe-cuted within 2 CLK cycles ..  Tags: vhdl code for usart  vhdl code for spi controller implementation on fp  verilog HDL program to generate PWM  PIC16C55X  PIC16C554  free vhdl code download for usart   PIC16C554 PIC16C558	133.92 Kb	7 Pages	Original
	First line: verilog code for TCON DP8051CPU Pipelined High Performance 8-bit Microcontroller 4.02 DP8051CPU ultra high performance, speed optimized soft core singlechip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. core been designed with special concern a Abstract: .. APEX20KE -1 68 MHz. APEX20KC APEX20KC -7 79 MHz. APEX-II -7 74 MHz. MERCURY -5 101 MHz. CYCLONE -6 93 MHz. CYCLONE-II -6 95 MHz. STRATIX -5 89 MHz. STRATIX-II -3 160 MHz. Core performance in ALTERA ® devices. For a user ..  Tags: verilog code for TCON verilog code for uart communication  function of internal data memory microcontroller   DP8051CPU DP8051CPU	169.93 Kb	10 Pages	Original
	First line: D16750 Configurable UART with FIFO 2.08 D16750 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C750. D16750 allows serial transmission modes: UART mode FIFO mode. FIFO mode internal FIFOs activated allowing bytes (plus bits error data byte RCVR FIFO) stored bo Abstract: .. APEX20KE -1 5111 96 MHz. APEX20K APEX20K -1 5111 87 MHz. ACEX1K -1 5431 93 MHz. FLEX10KE FLEX10KE -1 5431 94 MHz. 1 - FIFOs implemented in EAB’s – 1216 Bits Core performance in ALTERA ® devices. All trademarks mentioned in ..  Tags: verilog code for uart communication  D16750   TL16C750	135.41 Kb	7 Pages	Original
	First line: D16550 Configurable UART with FIFO 2.08 D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C550A. D16550 allows serial transmission modes: UART mode FIFO mode. FIFO mode internal FIFOs activated allowing bytes (plus bits error data byte RCVR FIFO) stored b Abstract: .. APEX20KE -1 4791 123 MHz. APEX20K APEX20K -1V 4791 94 MHz. ACEX1K -1 5001 104 MHz. FLEX10KE FLEX10KE -1 5001 102 MHz. 1 - FIFOs implemented in EAB’s – 304 Bits Core performance in ALTERA ® devices. All trademarks mentioned ..  Tags: verilog code for uart communication  TL16C550A   TL16C550A	134.85 Kb	7 Pages	Original
	First line: DRPIC166X High Performance Configurable 8-bit RISC Microcontroller 2.15 DRPIC166X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast (typically onchip) dual ported memory. core been designed with special concern about power consumption. DRPIC166X soft core softw Abstract: .. APEX20KE -1 1695 54 MHz. APEX20K APEX20K -1 1695 50 MHz. ACEX1K -1 1695 52 MHz. FLEX10KE FLEX10KE -1 1695 54 MHz. Core performance in ALTERA ® devices. Area utilized by the each unit of DRPIC166X DRPIC166X core in vendor specific technologies ..  Tags: vhdl code for usart  verilog HDL program to generate PWM  free vhdl code download for usart   PIC16C6X	142.42 Kb	8 Pages	Original
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