APEX20KE datasheet and Application Note, Data Sheet, Circuit, PDF, Pinout

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APEX20KE Datasheet, Circuit, PDF, & Application Note Results

Datasheet Search Results			1 - 4 of about 4 for APEX20KE
	APEX 20KE	Altera Corporation	New APEX 20KE Device Ordering Codes	79.87 Kb, 2 Pages.	Buy Now!

	APEX 20KE	Altera Corporation	APEX 20KE PCI Development Board Data Sheet	427.62 Kb, 40 Pages.	Buy Now!

	APEX 20KE	Altera Corporation	SB 55: APEX 20KE PCI Starter & Development Kit	762.02 Kb, 3 Pages.	Buy Now!

	APEX20KE	Altera Corporation	PIB 29: LVDS Comparision: APEX 20KE vs. Virtex-E Devices	285.96 Kb, 24 Pages.	Buy Now!

Contextual Datasheet Results		1 - 50 of about 62 for APEX20KE
	First line: DCAN Configurable Controller OVERVIEW DCAN stand-alone controller Controller Area Network CAN widely Abstract: .. APEX20KE -1 1956 + 2 ESB 83 MHz. APEX20K -1 1956 + 2 ESB 66 MHz. ACEX1K -1 1956 + 2 ESB 66 MHz. FLEX10KE -1 1956 + 2 ESB 66 MHz. 8-bit CPU Core performance in ALTERA® devices. Device. Speed grade Logic Cells Fmax .. datasheet abstract..	109.38 Kb	3 Pages

	First line: Mbps Dual-Speed Ethernet Media Access Controller Alcatel PE-MACMII module Mbps Ethernet Media Abstract: .. Device Family APEX20K APEX20KE. Device Used EP20K400FC672-1 EP20K400EFC672-1. Logic Cell Usage1. 1787 1784. EAB/ESB Usage. 0 0. Fmax2 25+ 25+ Core I/O Count3. 223 223. Included with MACMII Core Documentation .. datasheet abstract..	18.88 Kb	1 Pages

	First line: Mbps Dual-Speed Ethernet Media Access Controller Alcatel PE-MACMII module Mbps Ethernet Media Abstract: .. Device Family APEX20K APEX20KE. Device Used EP20K400FC672-1 EP20K400EFC672-1. Logic Cell Usage1. 1807 1805. EAB/ESB Usage. 0 0. Fmax2 52 61. Core I/O Count3. 223 223. Included with MACMII Core Documentation .. datasheet abstract..	19.23 Kb	1 Pages

	First line: Interfacing QDR with Altera APEX20KE QDRTM Introduction evolution newer systems increased demands Abstract: .. Interfacing the QDRTM with Altera APEX20KE. Cypress Semiconductor Corporation • 3901 North First Street San Jose CA 95134 408-943-2600 March 12, 2001. QDRTM: An Introduction The evolution of .. datasheet abstract..	87.61 Kb	7 Pages

	First line: DINT2FP Integer Floating Point Pipelined Converter OVERVIEW DINT2FP pipelined integer floating point Abstract: .. APEX20KE -1 470 73 MHz. APEX20KC -7 470 87 MHz. APEX-II -7 470 103 MHz. MERCURY -5 570 157 MHz. STRATIX -5 400 150 MHz. CYCLONE -6 385 156 MHz. STRATIX-II -3 330 234 MHz. CYCLONE-II -6 410 149 MHz. Core performance .. datasheet abstract..	94.28 Kb	2 Pages

	First line: DFPSQRT Floating Point Pipelined Square Root Unit OVERVIEW DFPSQRT uses pipelined mathematics Abstract: .. APEX20KE -1 970 53 MHz. APEX20KC -7 970 62 MHz. APEX-II -7 970 83 MHz. MERCURY -5 975 99 MHz. STRATIX -5 725 96 MHz. CYCLONE -6 725 94 MHz. STRATIX-II -3 890 131 MHz. CYCLONE-II -6 730 99 MHz. Core performance in .. datasheet abstract..	106.8 Kb	3 Pages

	First line: DFPMUL Floating Point Pipelined Multiplier Unit OVERVIEW DFPMUL uses pipelined mathematics algorithm Abstract: .. APEX20KE -1 1210 50 MHz. APEX20KC -7 1210 51 MHz. APEX-II -7 1210 67 MHz. MERCURY -5 1290 77 MHz. STRATIX -5 440+8M1 93 MHz. CYCLONE -6 1170 72 MHz. STRATIX-II -3 410+8M1 134 MHz. CYCLONE-II -6 480+8M1 117 MHz .. datasheet abstract..	99.17 Kb	3 Pages

	First line: DFPDIV Floating Point Pipelined Divider Unit OVERVIEW DFPDIV uses pipelined mathematics algorithm Abstract: .. APEX20KE -1 2720 40 MHz. APEX20KC -7 2720 42 MHz. APEX-II -7 2720 50 MHz. MERCURY -5 2780 65 MHz. STRATIX -5 2270 88 MHz. CYCLONE -6 2270 86 MHz. STRATIX-II -3 2040 104 MHz. Core performance in ALTERA® devices .. datasheet abstract..	98.69 Kb	3 Pages

	First line: DFPADD Floating Point Pipelined Adder Unit OVERVIEW DFPADD uses pipelined mathematics algorithm Abstract: .. APEX20KE -1 955 52 MHz. APEX20KC -7 955 68 MHz. APEX-II -7 955 88 MHz. MERCURY -5 975 117 MHz. STRATIX -5 845 107 MHz. CYCLONE -6 845 104 MHz. STRATIX-II -3 690 153 MHz. CYCLONE-II -6 845 105 MHz. Core performance .. datasheet abstract..	98.86 Kb	3 Pages

	First line: DFP2INT Floating Point Integer Pipelined Converter OVERVIEW DFP2INT pipelined floating point integer Abstract: .. APEX20KE -1 295 67 MHz. APEX20KC -7 295 88 MHz. APEX-II -7 295 114 MHz. MERCURY -5 270 208 MHz. STRATIX -5 245 184 MHz. CYCLONE -6 245 165 MHz. STRATIX-II -3 185 214 MHz. CYCLONE-II -6 265 133 MHz. Core performance .. datasheet abstract..	98.81 Kb	3 Pages

	First line: DI2CSB Interface Slave Base version OVERVIEW two-wire bi-directional serial that provides simple Abstract: .. APEX20KE -1 95 130 MHz. APEX20K -1 95 94 MHz. ACEX1K -1 95 99 MHz. FLEX10KE -1 95 95 MHz. MAX 7000AE -4 50 107 MHz. MAX 3000A -4 50 107 MHz. MAX II -3 75 154 MHz. Core performance in ALTERA® devices. The main features .. datasheet abstract..	105.74 Kb	4 Pages

	First line: DI2CS Interface Slave OVERVIEW two-wire bi-directional serial that provides simple efficient method Abstract: .. APEX20KE -1 170 120 MHz. APEX20K -1 170 90 MHz. ACEX1K -1 170 107 MHz. FLEX10KE -1 170 107 MHz. MAX 7000AE -5 83 96 MHz. MAX 3000A -5 83 104 MHz. Control Register – Contains five control bits used for performing .. datasheet abstract..	109.27 Kb	4 Pages

	First line: D8259 Programmable Interrupt Controller OVERVIEW D8259 soft Core Programmable Interrupt Controller. fully Abstract: .. APEX20KE -1 407 93 MHz. APEX20K -1V 407 72 MHz. ACEX1K -1 413 78 MHz. FLEX10KE -1 413 76 MHz. Core performance in ALTERA® devices. All trademarks mentioned in this document are trademarks of their respective .. datasheet abstract..	105.42 Kb	4 Pages

	First line: DSPIS Serial Peripheral Interface Slave OVERVIEW DSPIS fully configurable slave device designated Abstract: .. APEX20KE -1 82 202 MHz. APEX20K -1 82 140 MHz. ACEX1K -1 87 196 MHz. FLEX10KE -1 87 204 MHz. MAX2 -3 79 257 MHz. MAX3K -5 57 114 MHz. MAX7K -5 57 114 MHz. Core performance in ALTERA® devices. T r a n s f e r F o r m a t s. Software .. datasheet abstract..	113.63 Kb	5 Pages

	First line: DMAC Media Access Controller OVERVIEW DMAC hardware implementation media access control protocol Abstract: .. APEX20KE -1 1622 + 4 kB RAM 108 / 99 / 111. APEX20K -1 1622 + 4 kB RAM 86 / 87 / 88. Core performance in ALTERA® devices. All trademarks mentioned in this document are trademarks of their respective owners .. datasheet abstract..	106.89 Kb	4 Pages

	First line: DI2CMS Interface Master / Slave OVERVIEW two-wire bi-directional serial that provides simple efficient method Abstract: .. APEX20KE -1 394 120 MHz. APEX20K -1 394 90 MHz. ACEX1K -1 411 107 MHz. FLEX10KE -1 411 107 MHz. MAX 2 -3 291 187 MHz. MAX 7000AE -5 198 67 MHz. MAX 3000A -7 198 49 MHz. Core performance in ALTERA® devices. DI2CMS .. datasheet abstract..	116.97 Kb	6 Pages

	First line: DI2CM Interface Master OVERVIEW two-wire bi-directional serial that provides simple efficient method Abstract: .. APEX20KE -1 268 160 MHz. APEX20K -1 268 122 MHz. ACEX1K -1 287 135 MHz. FLEX10KE -1 287 140 MHz. MAX 2 -3 241 187 MHz. MAX 7000AE -5 137 67 MHz. MAX 3000A -7 137 49 MHz. Core performance in ALTERA® devices. The main .. datasheet abstract..	114.55 Kb	5 Pages

	First line: DFPMU Floating Point Coprocessor OVERVIEW DFPMU Floating Point Coprocessor designed assist performing Abstract: .. APEX20KE -1 5150 50 MHz. APEX20KC -7 5150 58 MHz. APEX-II -7 5150 73 MHz. CYCLONE -6 4650 90 MHz. CYCLONE-II -6 4520 96 MHz. STRATIX -5 4460 108 MHz. STRATIX-II -3 3300 168 MHz. Core performance in ALTERA® devices .. datasheet abstract..	110.47 Kb	5 Pages

	First line: DFPAU Floating Point Arithmetic Coprocessor OVERVIEW DFPAU Floating Point Arithmetic Coprocessor designed Abstract: .. APEX20KE -1 2640 48 MHz. APEX20KC -7 2640 57 MHz. APEX-II -7 2640 70 MHz. CYCLONE -6 2410 91 MHz. CYCLONE-II -6 2280 96 MHz. STRATIX -5 2210 115 MHz. STRATIX-II -3 1680 169 MHz. Core performance in ALTERA® devices .. datasheet abstract..	109.92 Kb	5 Pages

	First line: D68000 16 / 32-bit Microprocessor OVERVIEW D68000 soft core binary-compatible with industry standard 32-bit Abstract: .. APEX20KE -1 6332 32 MHz. APEX20KC -7 6332 37 MHz. APEX-II -7 6657 40 MHz. MERCURY -5 7086 45 MHz. STRATIX -5 6862 49 MHz. CYCLONE -6 6604 44 MHz. Core performance in ALTERA® devices. C O N T A C T S For any modification .. datasheet abstract..	107.75 Kb	4 Pages

	First line: DI2CM Interface Master OVERVIEW two-wire bi-directional serial that provides simple efficient method Abstract: .. APEX20KE -1 290 160 MHz. APEX20K -1 290 120 MHz. ACEX1K -1 290 130 MHz. FLEX10KE -1 290 140 MHz. MAX 7000AE -5 149 64 MHz. MAX 3000A -7 149 47 MHz. Core performance in ALTERA® devices. All trademarks mentioned .. datasheet abstract..	142.79 Kb	6 Pages

	First line: Simplex Encryption / Decryption Cores Virtual Components Converging World CS5265 / 75 CS5265 CS5275 Simplex encryption / decryption1 Abstract: .. Table 3: CS5265 / CS5275 Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHz DATA RATE MBITS/Sec CS5265AA 1666 .. datasheet abstract..	196.04 Kb	6 Pages

	First line: High Performance OCB-AES Simplex Encryption / Decryption Cores CS5331-32 Virtual Components Converging World CS5331 Abstract: .. Table 5: CS5331-32 Family Programmable Logic Core Using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHz DATA RATE MBITS/Sec a. a. Sustained .. datasheet abstract..	193.53 Kb	7 Pages

	First line: High Performance OCB-AES Encryption Cores CS5321-22 Virtual Components Converging World CS5321 CS5322 Abstract: .. Table 5: CS5321-CS5322 Programmable Logic Cores Using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CLOCK SPEED MHz DATA RATE MBITS/Sec CS5321AA 3322 8 46 136. CS5322AA 3605 .. datasheet abstract..	186.62 Kb	6 Pages

	First line: DSPIFIFO Serial Peripheral Interface Master / Slave with FIFO OVERVIEW DSPIFIFO fully configurable master / slave Abstract: .. APEX20KE -1 369 115 MHz. APEX20K -1 369 94 MHz. ACEX1K -1 369 103 MHz. FLEX10KE -1 369 103 MHz. Core performance in ALTERA® devices. T r a n s f e r F o r m a t s. Software can select any of four combinations of serial .. datasheet abstract..	91.93 Kb	6 Pages

	First line: DSPI Serial Peripheral Interface Master / Slave OVERVIEW DSPI fully configurable master / slave device which Abstract: .. APEX20KE -1 196 169 MHz. APEX20K -1 196 135 MHz. ACEX1K -1 205 156 MHz. FLEX10KE -1 205 156 MHz. MAX2 -3 181 209 MHz. MAX3K -5 119 96 MHz. MAX7K -5 119 96 MHz. Core performance in ALTERA® devices. All trademarks .. datasheet abstract..	90.2 Kb	6 Pages

	First line: D16450 Configurable UART OVERVIEW D16450 soft Core Universal Asynchronous Receiver / Transmitter UART functionally Abstract: .. APEX20KE -1 340 122 MHz. APEX20K -1 340 83 MHz. ACEX1K -1 363 99 MHz. FLEX10KE -1 363 98 MHz. Core performance in ALTERA® devices. D 1 6 X 5 0 U A R T S F A M I L Y O V E R V I E W. The family of DCD D16X50 UART IP Cores combine .. datasheet abstract..	129.84 Kb	6 Pages

	First line: High Performance Decryption Cores CS5250-80 Virtual Components Converging World CS5250-80 series decryption Abstract: .. Table 4: CS5250-80 Family of Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHZ DATA RATE MBITS/Sec CS5250AA .. datasheet abstract..	514.63 Kb	8 Pages

	First line: High Performance Encryption Cores CS5210-40 Virtual Components Converging World CS5210-40 series encryption Abstract: .. Table 4: CS5210-40 Family of Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE MEMORY USED ESB CYCLES PER OPERATION. CLOCK SPEED MHz DATA RATE MBITS/Sec CS5210AA .. datasheet abstract..	509.81 Kb	8 Pages

	First line: DES / 3DES Encryption / Decryption Cores CS5010-40 Virtual Components Converging World CS5010-CS5040 DES / 3DES Encryption / Decryption cores Abstract: .. Table 4: CS5010-40 DES/3DES Programmable Logic Cores using Altera APEX20KE-1. PRODUCT ID LOGIC USED LE CYCLES PER OPERATION. TIMING CONSTRAINT MHz DES DATA RATE MBITS/SEC. 3DES DATA RATE .. datasheet abstract..	529.44 Kb	8 Pages

	First line: White Paper Using APEX APEX 20KE PLLs Quartus Software Introduction APEX devices Abstract: .. The altclklock behavioral model can be used to simulate both the APEX20K PLL and the APEX20KE PLL by generating a clock signal based upon a reference clock. The APEX 20K and APEX 20KE behavioral .. datasheet abstract..	507.6 Kb	20 Pages

	First line: White Paper Using APEX APEX 20KE PLLs Quartus Software Introduction APEX devices Abstract: .. The altclklock behavioral model can be used to simulate both the APEX20K PLL and the APEX20KE PLL by generating a clock signal based upon a reference clock. The APEX 20K and APEX 20KE behavioral .. datasheet abstract..	585.13 Kb	20 Pages

	First line: DRPIC1655X High Performance Configurable 8-bit RISC Microcontroller OVERVIEW DRPIC1655X low-cost high performance Abstract: .. APEX20KE -1 1131 70 MHz. APEX20K -1 1131 41 MHz. ACEX1K -1 1150 64 MHz. FLEX10KE -1 1150 59 MHz. Core performance in ALTERA® devices. Area utilized by the each unit of DRPIC1655X core in vendor specific .. datasheet abstract..	139.88 Kb	8 Pages

	First line: DRPIC166X High Performance Configurable 8-bit RISC Microcontroller OVERVIEW DRPIC166X low-cost high performance Abstract: .. APEX20KE -1 1695 54 MHz. APEX20K -1 1695 50 MHz. ACEX1K -1 1695 52 MHz. FLEX10KE -1 1695 54 MHz. Core performance in ALTERA® devices. Area utilized by the each unit of DRPIC166X core in vendor specific technologies .. datasheet abstract..	142.42 Kb	8 Pages

	First line: DP8051CPU Pipelined High Performance 8-bit Microcontroller OVERVIEW DP8051CPU ultra high performance speed Abstract: .. APEX20KE -1 68 MHz. APEX20KC -7 79 MHz. APEX-II -7 74 MHz. MERCURY -5 101 MHz. CYCLONE -6 93 MHz. CYCLONE-II -6 95 MHz. STRATIX -5 89 MHz. STRATIX-II -3 160 MHz. Core performance in ALTERA® devices. For a user .. datasheet abstract..	169.93 Kb	10 Pages

	First line: DFPIC1655X High Performance Configurable 8-bit RISC Microcontroller OVERVIEW DFPIC1655X low-cost high performance Abstract: .. APEX20KE -1 739 56 MHz. APEX20K -1 739 50 MHz. ACEX1K -1 804 39 MHz. FLEX10KE -1 804 38 MHz. Core performance in ALTERA® devices. I M P R O V E M E N T Most instruction of DFPIC1655X is exe-cuted within 2 CLK cycles .. datasheet abstract..	133.92 Kb	7 Pages

	First line: DFPIC165X High Performance 8-bit RISC Microcontroller OVERVIEW DFPIC165X low-cost high performance 8-bit Abstract: .. APEX20KE -1 635 56 MHz. APEX20K -1 635 45 MHz. ACEX1K -1 648 50 MHz. FLEX10KE -1 648 48 MHz. CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack, 256 B RAM, 4k of Program memory. Core performance .. datasheet abstract..*	128.96 Kb	6 Pages

	First line: DF6811CPU 8-bit FAST Microcontrollers Family OVERVIEW Document contains brief description DF6811CPU core Abstract: .. APEX20KE -1 1809 42 MHz. ACEX1K -1 1785 34 MHz. FLEX10KE -1 1785 32 MHz. Core performance in ALTERA® devices. I M P R O V E M E N T For user the most important is application speed improvement. The most commonly .. datasheet abstract..	145.17 Kb	7 Pages

	First line: DF6808 8-bit FAST Microcontrollers Family OVERVIEW Document contains brief description DF6808 core Abstract: .. APEX20KE -1 2531 41 MHz. ACEX1K -1 2536 36 MHz. FLEX10KE -1 2536 36 MHz. Core performance in ALTERA® devices. Area utilized by the each unit of DF6808 core in vendor specific technologies is summarized .. datasheet abstract..	158.61 Kb	9 Pages

	First line: DF6805 8-bit FAST Microcontrollers Family OVERVIEW Document contains brief description DF6805 core Abstract: .. APEX20KE -1 1698 47 MHz. ACEX1K -1 1739 41 MHz. FLEX10KE -1 1739 41 MHz. Core performance in ALTERA® devices. Area utilized by the each unit of DF6805 core in vendor specific technologies is summarized .. datasheet abstract..	154.04 Kb	8 Pages

	First line: D16750 Configurable UART with FIFO OVERVIEW D16750 soft Core Universal Asynchronous Receiver / Transmitter Abstract: .. APEX20KE -1 5111 96 MHz. APEX20K -1 5111 87 MHz. ACEX1K -1 5431 93 MHz. FLEX10KE -1 5431 94 MHz. 1 - FIFOs implemented in EAB’s – 1216 Bits Core performance in ALTERA® devices. All trademarks mentioned in .. datasheet abstract..	135.41 Kb	7 Pages

	First line: D16550 Configurable UART with FIFO OVERVIEW D16550 soft Core Universal Asynchronous Receiver / Transmitter Abstract: .. APEX20KE -1 4791 123 MHz. APEX20K -1V 4791 94 MHz. ACEX1K -1 5001 104 MHz. FLEX10KE -1 5001 102 MHz. 1 - FIFOs implemented in EAB’s – 304 Bits Core performance in ALTERA® devices. All trademarks mentioned .. datasheet abstract..	134.85 Kb	7 Pages

	First line: Discrete Wavelet Transform CS6210 Virtual Components Converging World CS6210 Forward Discrete Wavelet Abstract: .. CS6210AA Altera Apex20KE 47 7381 LEs 24 ESBs Now. CS6210XE Xilinx VirtexE-8 55 3784. SLICES 24 BRAMs Now. CS6210 Discrete Wavelet Transform. TM. Virtual Components for the Converging World. CORPORATE .. datasheet abstract..	320.54 Kb	11 Pages

	First line: Scripting with Quartus Software Application Note November ver. Introduction Developing running tool Abstract: .. where: <family name> = APEX20K, APEX20KE <device name> = any valid device in the specified family. Add Pinout. To add a pin assignment, use the following Tcl command. cmp add_assignment <chip_name .. datasheet abstract..	207.68 Kb	16 Pages

	First line: Mentor Graphics ModelSim Support QII53001-7.1.0 Introduction Altera software subscription includes license ModelSim-Altera Abstract: .. apex20ke Precompiled library for APEX 20KC, APEX 20KE, and ExcaliburTM device designs. mercury Precompiled library for MercuryTM device designs. flex10ke Precompiled library for FLEX® .. datasheet abstract..	826.28 Kb	54 Pages

	First line: D16550 Configurable UART with FIFO OVERVIEW D16550 soft Core Universal Asynchronous Receiver / Transmitter Abstract: .. APEX20KE -1 5071 103 MHz. APEX20K -1 5071 103 MHz. ACEX1K -1 5091 88 MHz. FLEX10KE -1 5091 81 MHz. 1 - FIFOs implemented in EAB’s – 304 Bits Core performance in ALTERA® devices. D 1 6 X 5 0 U A R T S F A M I L Y O V E R V .. datasheet abstract..	96.65 Kb	6 Pages

	First line: Standard Hash Algorithm SHA-1 SHA-2 Cores CS5310 / 11 / 12 Virtual Components Converging World CS5310 / 11 / 12 Abstract: .. Table 7: CS5311 Programmable Logic Core Using Altera APEX20KE-1. PRODUCT ID. LOGIC USED LEs MEMORY USED. ESB CYCLES PER OPERATION. TIMING. CONSTRAINT MHz SUSTAINED DATA THROUGHPUT Gbps .. datasheet abstract..	207.15 Kb	12 Pages

	First line: Application Note MSAN-188 Implementing GTLP Drivers Mb / s Backplanes Contents Introduction Background Information Abstract: .. APEX20KE, APEX20KC. 1.8V. CPLD Cypress Delta39K 3.3V. CL CL CL. RT CL. λ. Application Note MSAN-188 .. datasheet abstract..	122.82 Kb	11 Pages

	First line: DP80390CPU Pipelined High Performance 8-bit Microcontroller OVERVIEW DP80390CPU ultra high performance speed Abstract: .. APEX20KE -1 63 MHz. APEX20KC -7 76 MHz. APEX-II -7 74 MHz. MERCURY -5 101 MHz. CYCLONE -6 93 MHz. CYCLONE-II -6 95 MHz. STRATIX -5 98 MHz. STRATIX-II -3 160 MHz. Core performance in ALTERA® devices. For a user .. datasheet abstract..	169.49 Kb	10 Pages

	First line: DP80390 Pipelined High Performance 8-bit Microcontroller OVERVIEW DP80390 ultra high performance speed Abstract: .. APEX20KE -1 66 MHz. APEX20KC -7 78 MHz. APEX-II -7 76 MHz. MERCURY -5 100 MHz. CYCLONE -6 91 MHz. CYCLONE-II -6 93 MHz. STRATIX -5 90 MHz. STRATIX-II -3 160 MHz. Core performance in ALTERA® devices. For a user .. datasheet abstract..	174.73 Kb	10 Pages

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