500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
HI3-674AJN-5 Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 visit Intersil
HI5812JIB Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 visit Intersil
HI5812JIP Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24 visit Intersil
HI3-674AKN-5 Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 visit Intersil
HI5812KIB Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 visit Intersil
HI3-574AJN-5 Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 visit Intersil

ADC EISC

Catalog Datasheet MFG & Type PDF Document Tags

SE1608

Abstract: 16 bit risc processor SE1608 High-Performance 16bit Embedded MCU Core IP, FPGA Processor Product Information 16-bit Simple EISC Description SE1608 is a small, high-performance, low power embedded 16 bit MCU processor based on adc' proprietary s EISC (Extendable Instruction Set Computer) architecture. EISC possesses advantages over existing CISC and RISC architectures. EISC' fixed length instruction set maximizes cost/performance efficiency and at the same time s offers flexibility and power through the Extendable Register
Xian Swip
Original
16 bit risc processor 16-bit alu cisc architecture eisc ADC EISC computer architecture 360MIP

ae32000c

Abstract: super harvard architecture block diagram Multimedia Processor 32bit EISC Microcontroller Description GMX-1000 is the new adchips' multimedia , PWM 0.1 (Timer 4.5) / PPM Watch Dog Timer Key Scan Timer 0, 1,2,3 ADC Controller Pin Mux 12 S , We build a new millenium technology. GMX-1000 Preliminary Information Features â'¢ 32bit EISC(AE32000C) Processor Core - Based On EISC Instruction Set Architecture - High Performance Integer , '¢ IDE Controller for HDD Interface High-Performance Multimedia Processor 32bit EISC Microcontroller â
-
OCR Scan
MPU-401 super harvard architecture block diagram drum machine sound ic VOICE RECORDer on USB flash memory drum sound ic crt controller

Transistor 638 MOTOROLA

Abstract: 2N6056 MOTOROLA applications. · High DC Current Gain - hpE = 3000 (Typ) @ Iq = 4.0 Adc · Collector-Emitter Sustaining Voltage - @ 100 mA · Low Collector-Emitter Saturation Voltage - VcE(sat) = 2 0 Vdc {Max) @ lc = 4.0 Adc = 3.0 Vdc (Max) @ Iq = 8.0 Adc · Monolithic Construction with Built-In Base-Em itter Shunt Resistors M , WATTS Max 80 80 5.0 8.0 16 120 100 0.571 - 6 5 t o +200 Unit Vdc Vdc Vdc Adc mAdc Watts W/°C °C , Voltage (1) (IC = 100m Adc, Ib = 0) Collector Cutoff Current (V q e = 40 Vdc, Ib = 0) Collector Cutoff
-
OCR Scan
Transistor 638 MOTOROLA 2N6056 MOTOROLA DIODE 851 MOTOROLA REF2667 2N6056/D 2N6056

CBF 423

Abstract: SGI Reality Coprocessor FEATURES 1.1 General Description ADC's VISA2000 32bit SEISC microcontroller is designed to provide a , background. SE3208 is the family in EISC series and is optimized for Embedded Application and the , sticker and etc. 1.2 Features Built in 32bit CPU - High Performance EISC Core SE3208 - 2Kbyte
Advanced Digital Chips
Original
KA2198 JRC2246 CBF 423 SGI Reality Coprocessor R3404 1x32-Bit MC44144
Abstract: DA2 DA1 DAO $17 SCI STATUS $18 SCI DATA $19 CONFIG REG $1A EISC REG RESERVED STPEN , is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4 -
OCR Scan
MC68HC05C0 M68HC05

JRC 45600

Abstract: 45600 JRC Approval BBC ABB IXY ABP A BS ACP ACC ALI ACR ACS ACT ACU M /C ADP ADA ADT ADL ADV ADC
-
OCR Scan
JRC 45600 45600 JRC YD 803 SGS TDA 7277 krp power source sps 6360 TDA 5072 ZOP020 ZOP021 ZOP023 ZOP022 ZOP024 ZOP025

001B

Abstract: 001C - - - $17 SCI STATUS $18 SCI DATA $19 CONFIG REG $1A EISC REG RESERVED Figure 2-2 , is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4
Motorola
Original
68HC05C0 001B 001C HC05 HC05C0GRS/D

eisc

Abstract: 68HC05C0 $17 SCI STATUS $18 SCI DATA $19 CONFIG REG $1A EISC REG RESERVED Figure 2-2: I/O Registers for , Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between
Freescale Semiconductor
Original
ddr2 A14-A8
Abstract: '" â'" $17 SCI STATUS $18 SCI DATA $19 CONFIG REG $1A EISC REG RESERVED Figure 2-2: I/O , Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between Freescale Semiconductor
Original