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Part : RK27112A0A16 Supplier : ALPS Manufacturer : Avnet Stock : - Best Price : $7.29 Price Each : $7.89
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A0-A16

Catalog Datasheet MFG & Type PDF Document Tags

ADA16

Abstract: A0-A16 A0-A16 NOE DQO-7 129kx8 NWE/NCS/CE A0-A16 NOE DQO-7 12BXXÍ NWE/NCS/CE A0-A16 NOE NW6/NCS/CE A0-A16 NOE NWE/NCS/CE AD-A16 NOE NWE/NCS/CE A0-A16 NOE C T IS PINOUT CONFIGURATION ch«ck B«*(x16) A0-A16
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OCR Scan
ADA16 HC83241 DATAO-31 DOS-15 DQ16-23 DQ24-31

M12j

Abstract: M10I   SEL0 â  5EÏ â  CE2 â'¢ sen CE0 ÃE â  W â  A0-A16 â  =6 M14 M12j M10I 8 M8 I -1/016-1/023 -1/00-1/07 CE7 â'¢ SE10 â  ÃE5 â  CE3 â'¢ SEL1 CET ÃE â  W â  A0-A16 â  =0 M15! M13; M1t| M9 ? S -I/024-I/031 -1/08-1/015 CES -SEL1 - en â'¢ CEà SEL0 ere se â  *E â  A0-A16 â , â'¢ WE â  A0-A16 â  =0 M7 I M5 I M3 Ml -1/024-1/031 -1/08-1/015 Commercial only. PIN NAMES A0-A16 Address Inputs I/00-I/031 Data Input/Output CÃ'Ã"-CÃ'7 Low Chip Enables â  SEL0, SEL1
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OCR Scan
M12j M10I DPS512X32AV3 T-V4-23-/V 1024K 2048K 1/01S 30A044-11

1df26

Abstract: Y153 I/O No. 16 CPU D0-D15 I/O A0-A16 I 17 /CS I 3.3 V /OE , V1 - V2 - 3.3 V D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, GMODE, PL0, PL1 , µ PD16661A DIR PL0,1,2 TEST A0A16 Address input control Address management , circuit) A0A16 RAM µ PD16661A 8 VGA 480×640 2 (Arbiter) RAM RAM 3RAM 160×240×2 , RDY RAM RAM CPU RDY CPU 1 A0A16,/UBE /CS /OE,/WE Hi-z Hi-z RDY
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1df26 Y153 1DE28 1DF28 D1666 MARK Y153 PD16666A VGA640 PD16661 PD16661AN-XXX PD16661AN-051 S11498JJ3V1DS00

0802A LCD

Abstract: 0802C ) 1998,1999 µ PD16664 1. CMODE0, CMODE1 DIR PL0,PL1 TEST A0-A16 Address input control , D0-D15 I/O A0-A16 I 17 /CS I VCC2 /OE I /WE I /UBE , V0 - V1 - V2 - VCC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE , circuit A0A16 RAM LSI 4 416×320 1FF00H1FF1EH 25 4 (2) Arbiter RAM RAM (3) RAM , PD16664 12. CPU 12.1 RDY RAM RAM CPU RDY CPU (1) A0A16,/UBE /CS /OE,/WE
NEC
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0802A LCD 0802C 07F28 0A128 0814E 09F28 PD16667 PD16664N- PD16664N-001 S13780JJ2V0DS00 C10983J C11531J

Y153

Abstract: 0009E I/O No. 16 CPU D0-D15 I/O A0-A16 I 17 /CS I 3.3 V /OE , V1 - V2 - 3.3 V D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, GMODE, PL0, PL1 , µ PD16661A DIR PL0,1,2 TEST A0A16 Address input control Address management , circuit) A0A16 RAM µ PD16661A 8 VGA 480×640 2 (Arbiter) RAM RAM 3RAM 160×240×2 , RDY RAM RAM CPU RDY CPU 1 A0A16,/UBE /CS /OE,/WE Hi-z Hi-z RDY
NEC
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0009E MARK Y8 Y160 0F128 1df9 Y1-Y160
Abstract: NWE/NCS/CE NWE.'JiCSiCE AC-A1S NOE A0-A16 DOC-7 123/03 HW E'SCS.'CE AC-A1S NOE AC-A16 NOE A0-A16 NOE A0-A16 NOE A0-A16 NOE _E IE z c NOE 66 Pin Grid Array (PGA -
OCR Scan
GGD1D17 TA0-31

YPPD

Abstract: PPD16662 "L" = 16 /REFRH 3.3 V I /OE I/O /CS 3.3 V D0D15 A0A16 CPUIF I/O , 5.0 V /xxx 3.3 V D0D15, A0A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2 , TEST A0A16 BMODE D0D15 RAM 240×160×2 , 240 PULSE /FRM STB /DOUT L1 L2 Y1 Y2 Y3 Y240 3 PPD16662 1 A0A16 RAM , PPD16662 CPU 1RDY RAM RAM CPU RDY CPU A0A16, /UBE /CS /OE, /WE RDY Hi-Z
NEC
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PPD16667 PPD16662N YPPD Y240 11000B Y118 S12738JJ3V0DS00 Y1Y240

0802A LCD

Abstract: y204 µ PD16664 1. CMODE0, CMODE1 DIR PL0,PL1 TEST A0-A16 Address input control Address , A0-A16 I 17 /CS I VCC2 /OE I /WE I /UBE I RDY O , - VCC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET , S13780JJ2V0DS00 3 µ PD16664 3. (1) Address management circuit A0A16 RAM LSI 4 416×320 , (1) A0A16,/UBE /CS /OE,/WE Hi-Z Hi-Z RDY (2) RDY RDY 3 µ PD16664 LSI
NEC
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y204 07F2A 09F2C 07F58 09F24 09E28
Abstract: 14 A8 CE A1 IN 11 13 16 GND 17 D3 IN/OUT 22 A0-A16 D0-D7 CE OE PGM 24 , INPUT MBM27C1001-20(2/2) READ MODE(VDD = +5V,VPP = +5V) OE CE PGM A0-A16 D0-D7 0 0 1 A IN D , DISABLE PROGRAM MODE(VDD = +6V,VPP = +12.5V) MODE OE CE PGM A0-A16 1 0 0 A IN 1-BYTE 0 1 A -
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A2-A16

AT17128

Abstract: AD 4153 use only one, D0. A0-A16 A0-A16 are address output signals, used by modes 1, 2 and 5, to drive , control signals as well as the A0-A16 output signals, ERR output, and CSOUT signal. Data is loaded into , Configuration Pins Used CON, CS, M0, M1, M2, CCLK Dual-Function Pins Used D0-D7, A0-A16 Optional , Used CON, CS, M0, M1, M2, CCLK Dual-Function Pins Used D0-D7, A0-A16 Mode 2 (Figure 7 , MODE 2 M1 M2 M0 CCLK A0-A16 D0-D7 CS CON Figure 6. Mode 1 Configuration AT60xx MODE 1 M0
Atmel
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AT17128 AD 4153 ad 8077 Vector Controls AT171 AT17XXX AT6000

0A07A

Abstract: Y240 D0-D15 I/O 16 A0-A16 I 17 /CS I 3.3 V /OE I /WE I /UBE , , A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5 V STB , management circuit) A0-A16 RAM PD16663 4 480×320 1FFF80H-1FFFEH 49 16 2 (Arbiter) RAM , . CPU 7.1 RDY RAM RAM CPU RDY CPU 7.1.1 A0-A16,/UBE /CS /OE,/WE Hi-z Hi-z , PL0, PL1 LSI No. DIR 1 OSC1, OSC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF
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0A07A PD16663N-XXX PD16663N-051 S13392JJ1V0DS00

DPS512X32BV3

Abstract: CE4 WE0 OE A0-A16 C M14 5 M6 M12 1 S 1/00-1/07 1/016-1/023 CE5 WEI DE A0-A16 C M15 J M7 J £ M13 i S I/0S-I/015 1/024-1/031 CE0 WE0 OE A0-A16 - 1/016-1/023 - 1/00-1/07 CEI WE1 DE A0-A16 M3
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OCR Scan
DPS512X32BV3 AO-A16 I/031 30A044-12

HD74ACT138FP

Abstract: HM628128 Power supply VSS Ground 3 HM66205L Series Block Diagram A0­A16 A0 A1 A2 E1 E2 E3 A17 A18 CS VCC 01 02 03 04 05 06 07 08 Decoder *2 I/O1­I/O8 WE OE A0­A16 CS1 *1 CS2 I/O 1­8 RAM WE No.1 OE A0­A16 CS1 CS2 *1 I/O 1­8 RAM WE No.3 OE VCC VSS A0­A16 CS1 *1 CS2 I/O 1­8 RAM WE No.2 OE A0­A16 CS1 CS2 *1 I/O 1­8 RAM WE No.4 OE Notes
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HD74ACT138FP HM628128 CSA-012 HM628128BLT HM66205L-85B HM66205L-10B HM66205L-12B

HM66205L-85

Abstract: HM66205L-10 -­ 1 HM66205L Series HM66205L Series Block Diagram A0­A16 A17 A18 CS VCC I/O1­I/O8 WE OE A0 A1 A2 E1 E2 E3 01 02 03 04 05 06 07 08 Decoder *2 VSS A0­A16 CS1 *1 CS2 I/O 1­8 RAM WE No.2 OE A0­A16 CS1 CS2 *1 I/O 1­8 RAM WE No.3 OE VCC A0­A16 CS1 *1 CS2 I/O 1­8 RAM WE No.1 OE A0­A16 CS1 CS2 *1 I/O 1­8 RAM WE No.4 OE
Hitachi Semiconductor
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HM66205L-85 HM66205L-10 Decoder 5 to 32 cmos of 40 or 45 series HM66205L10 HM66205L-12 HM628128LT

M28F101

Abstract: PDIP32 A0-A16 W DQ0-DQ7 M28F101 Supply Voltage VSS VPP Output Enable W VCC Chip , . Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A16 DQ0-DQ7 X 2 Write X 90h 00000h 20h 00001h 07h X 20h Read X Data Output A0-A16 Data Input 00h Electronic Signature Read Write Write DQ0-DQ7 Write 1 A0-A16 , Program/ 2 2 Write A0-A16 0A0h Write X 40h Program Program Verify 2 Write
STMicroelectronics
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PLCC32 PDIP32 TSOP32 AI00666B

Dense-Pac Microsystems

Abstract: ) â'¢ 66-Pin PGA "VERSA-STACK" Package FUNCTIONAL BLOCK DIAGRAM ÃE2 SEL0 CE0 ÃE WF A0-A16 CE1 1/016-I/023 0E A0-A16 M1 -1/08â'" 1/015 Commercial only. PIN NAMES A0-A16 Address Inputs I
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OCR Scan
Dense-Pac Microsystems DPS128X24AV3 I/00-I/023 30A044-31 D00G445 T-46-23-14

TSOP32

Abstract: M68Z128 compatible. Table 1. Signal Names A0-A16 Address Inputs DQ0-DQ7 Data Inputs / Outputs E1 Chip Enable 1 E2 Write Enable VCC A0-A16 DQ0-DQ7 W M68Z128 Supply Voltage VSS , for any given device. Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 , VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV , Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH
STMicroelectronics
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AI00647

00005H

Abstract: 09fe D0-D15 I/O 16 A0-A16 I 17 /CS I 3.3 V /OE I /WE I /UBE , , A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5 V STB , management circuit) A0-A16 RAM PD16663 4 480×320 1FFF80H-1FFFEH 49 16 2 (Arbiter) RAM , . CPU 7.1 RDY RAM RAM CPU RDY CPU 7.1.1 A0-A16,/UBE /CS /OE,/WE Hi-z Hi-z , PL0, PL1 LSI No. DIR 1 OSC1, OSC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF
NEC
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00005H 09fe

M68Z128

Abstract: TSOP32 x 20mm) Figure 1. Logic Diagram VCC 17 8 A0-A16 DQ0-DQ7 W A0-A16 Address , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms tAVAV A0-A16 VALID tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , Figure 8. Write Enable Controlled, Write AC Waveforms tAVAV A0-A16 VALID tAVWH tWHAX tAVE1L , A0-A16 VALID tAVE1H tAVE1L tE1HAX tE1LE1H E1 tAVE2L tAVE2H tE2HE2L tE2LAX E2
STMicroelectronics
Original
Abstract: available in the standard 450mil-wide TSOP type 1 package. Figure 1. Logic Diagram VCC 17 A0-A16 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC Address Inputs Data Input , . Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 tAVQV VALID tAXQX DQ0-DQ7 DATA , Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV A0-A16 tAVQV tE1LQV E1 tE1LQX tE2HQV , , Write AC Waveforms tAVAV A0-A16 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA STMicroelectronics
Original
M68Z128W AI01878B
Abstract: I/O No. 16 CPU D0-D15 I/O A0-A16 I 17 /CS I 3.3 V /OE , V1 - V2 - 3.3 V D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, GMODE, PL0, PL1 , µ PD16661A DIR PL0,1,2 TEST A0A16 Address input control Address management , circuit) A0A16 RAM µ PD16661A 8 VGA 480×640 2 (Arbiter) RAM RAM 3RAM 160×240×2 , RDY RAM RAM CPU RDY CPU 1 A0A16,/UBE /CS /OE,/WE Hi-z Hi-z RDY Smart Modular Technologies
Original
SM372QFSFN3UGUU

fet p80

Abstract: fet p60 Diagram VCC VPP 17 8 A0-A16 Table 1. Signal Names A0-A16 Address Inputs DQ0-DQ7 , A0-A16 DQ0-DQ7 X 2 Write X 90h 00000h 20h 00001h 07h X 20h Read X Data Output A0-A16 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A16 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A16 A0h Write X 40h
Toshiba
Original
TMP91PW18A TMP91PW18AF TMP91CW18A fet p80 fet p60 80 sio TLCS-900/L1 000000H 001000H

M28F101

Abstract: PDIP32 Diagram VCC VPP 17 8 A0-A16 Table 1. Signal Names A0-A16 Address Inputs DQ0-DQ7 , Operation A0-A16 DQ0-DQ7 X 2 Write X 90h 00000h 20h 00001h 07h X 20h Read X Data Output A0-A16 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A16 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A16 A0h Write X 40h
STMicroelectronics
Original

M28F101

Abstract: PDIP32 Diagram VCC VPP 17 8 A0-A16 Table 1. Signal Names A0-A16 Data Inputs / Outputs E , 07h Table 5. Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A16 , Output A0-A16 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A16 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A16 A0h Write X 40h Program Program
STMicroelectronics
Original

M28F101

Abstract: PDIP32 µ PD16664 1. CMODE0, CMODE1 DIR PL0,PL1 TEST A0-A16 Address input control Address , A0-A16 I 17 /CS I VCC2 /OE I /WE I /UBE I RDY O , - VCC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET , S13780JJ2V0DS00 3 µ PD16664 3. (1) Address management circuit A0A16 RAM LSI 4 416×320 , (1) A0A16,/UBE /CS /OE,/WE Hi-Z Hi-Z RDY (2) RDY RDY 3 µ PD16664 LSI
STMicroelectronics
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SRAM 10ns

M28F101

Abstract: PDIP32 A0-A16 Data Inputs / Outputs E Chip Enable G Ground NC A0-A16 DQ0-DQ7 Supply , housing containing the battery. M48Z128, M48Z128Y Figure 3. Block Diagram VCC A0-A16 POWER , DQ0-DQ7 E E1CON E E2CON E3CON E4CON A0-A16 A RST B W BL VSS VSS AI03625 , . CL = 5pF. Figure 7. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 VALID tAVQV , Mode AC Waveforms tAVAV A0-A16 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV
STMicroelectronics
Original

M48Z128

Abstract: M48Z128Y D0-D15 I/O 16 A0-A16 I 17 /CS I 3.3 V /OE I /WE I /UBE , , A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5 V STB , management circuit) A0-A16 RAM PD16663 4 480×320 1FFF80H-1FFFEH 49 16 2 (Arbiter) RAM , . CPU 7.1 RDY RAM RAM CPU RDY CPU 7.1.1 A0-A16,/UBE /CS /OE,/WE Hi-z Hi-z , PL0, PL1 LSI No. DIR 1 OSC1, OSC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF
STMicroelectronics
Original
SOH28 PMDIP32 28-PIN 32-LEAD AI01194

A-6628

Abstract: a6628 D0-D15 I/O 16 A0-A16 I 17 /CS I 3.3 V /OE I /WE I /UBE , , A0-A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5 V STB , management circuit) A0-A16 RAM PD16663 4 480×320 1FFF80H-1FFFEH 49 16 2 (Arbiter) RAM , . CPU 7.1 RDY RAM RAM CPU RDY CPU 7.1.1 A0-A16,/UBE /CS /OE,/WE Hi-z Hi-z , PL0, PL1 LSI No. DIR 1 OSC1, OSC2 D0-D15, A0-A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF
OKI Electric Industry
Original
MSM548128BL A-6628 a6628 DIP32 J2L0043-17-Y1 072-W MSM548128BL512 81MSRAMCMOS RAM256KSRAM

M28F101

Abstract: PDIP32 compatible. Table 1. Signal Names A0-A16 Address Inputs DQ0-DQ7 Data Inputs / Outputs E1 Chip Enable 1 E2 Write Enable VCC A0-A16 DQ0-DQ7 W M68Z128 Supply Voltage VSS , for any given device. Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 , VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV , Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH
STMicroelectronics
Original
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