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GCP841A_0I6R_USB_S Controller (150043558) GE Critical Power Global Power System Galaxy Pulsar Edge Controller visit GE Critical Power
SN74AS841ADWR Texas Instruments 10-Bit Bus-Interface D-Type Latches With 3-State Outputs 24-SOIC 0 to 70 visit Texas Instruments
SN74ABT841ADBR Texas Instruments 10-Bit Bus-Interface D-Type Latches With 3-State Outputs 24-SSOP -40 to 85 visit Texas Instruments
SN74LVC841ADW Texas Instruments 10-Bit Bus-Interface D-Type Latch With 3-State Outputs 24-SOIC -40 to 85 visit Texas Instruments
SN74LVC841APWR Texas Instruments 10-Bit Bus-Interface D-Type Latch With 3-State Outputs 24-TSSOP -40 to 85 visit Texas Instruments

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841A

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: -(l)shows pin assignment of the TMP90C840AN/841AN. VREF Z AGND Z (ANO) P50 IZ (AN1) P51 IZ (AN2) P52 , 2.1-(2) shows pin assigunment of the TMP90Ç840AF/841AF. (TxD /RTS/SCLK) P32 (TxD) P33 (CTS) P34 1 , TOSHIBA TMP90C840A/841A CMOS 8-BIT MICROCONTROLLERS TMP90C840AN/TMP90C841 AN TM P90C840AF/TM , as the TMP90C840A but without the ROM. The TMP90C840AN/841AN is a 64-pin shrink DIP product. (SDIP64-P-750) The TMP90C840AF/841AF is a 64-pin flat package product. (QFP64-P-1420A) The characteristics -
OCR Scan
90C841 TMP90C841AN tmp90c841af 90c84 90c840a Cu-90 TMP90C840A/841A P90C841AF TMP90C841A TMP90C840AN/841AN TMP90C840AF/841AF 90C840A
Abstract: TMP90C840AN/841AN. VREF C AGND C (ANO) P50 IZ (AN1) P51 C (AN2) P52 C (AN3) P53 C (AN4) P54 C (AN 5 , ) shows pin assigunment of the TMP90C840AF/841AF. g g1 S ' co" vo in ? ? ST c ? P 1 o û g , : InitializestheTMP90C840A/841A. (Built-in pull-up resister) X1/X2 2 Input/ Output Vcc 1 Power supply ( + , TOSHIBA (UC/UP) LjME » m ^724^ G025715 fc. * 7 0 5 3 13 TMP90C840A/841A T O S H , as the TMP90C840A but without the ROM. The TMP90C840AN/841AN is a 64-pin shrink DIP product -
OCR Scan
TMP90C840AN/TMP90C841AN TMP90C840AF/TMP90C841AF 0D2S72 MCU90-14
Abstract: assigunment of the TMP90C840AF/841AF. ce 5'£'P(dK?m S'Po cc a. a. Juj â'" _ -~ a . , Ground (OV) Reset: Initializes the TMP90C840A/841A. (Built-in pull-up resister) Pins for quartz , TOSHIBA TM P90C840A/841A CMOS 8-BIT MICROCONTROLLERS TMP90C840AN/TMP90C841AN TM P90C840AF , /A16â'"A19 TOSHIBA 2. TMP90C840A/841A PIN ASSIGNMENT AND FUNCTIONS The assignment of input , 2.2 TM P90C840A/841A Pin Names and Functions The names of input/output pins and their -
OCR Scan
P90C840A/841A TMP90C840AN/841 TMP90C840AF/841 90C041 90C141 MCU90-139
Abstract: DESCRIPTION The 74LVC(H)841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced , Semiconductors Objective specification 10-bit transparent latch with 5-volt tolerant 74LVC 841A inputs , 10-bit transparent latch with 5-volt tolerant 74LVC 841A inputs/outputs; 3 , high impedance OFF-state NC = no change DC CHARACTERISTICS FOR 74LVC(H)841A For the DC characteristics , 74LVC(H)841A GND = 0 V; t, = t, < 2.5 ns; CL = 50 pF_ T .m t (°C) SYMBOL PARAMETER MIN. 40 to +85 -
OCR Scan
LVCH2B41A 74LVC841A 74LVCH841A
Abstract: TOSHIBA TMP90C840A/841A Port 4 Register 7 P4 (FFC8H) 6 5 4 3 2 P43 P42 0 bit Symbol 0 Read/Write 0 P41 P40 0 0 P41C P40C 0 0 R /W Resetting Value Port 4 Control Register 7 6 5 4 3 2 P43C bit Symbol P4CR (FFC9H , MAS TOSHIBA 3.5.6 TMP90C840A/841A Port 5 (P 5 0 -P 5 5 ) Port 5 is a 6-bit input port P5 ,   ^0^724^ 002^001 311 â  TOSHIBA TM P90C840A/841A 3.5.7 Port 6 (P60-P63) Port 6 is a 4 -
OCR Scan
P60--P63 P67CR
Abstract: 821 (Note 2) 824A (Note 2) 841A (Note 2) 842A (Note 2 ) 843A (Note 2) TABLE 4. CROSS OF EQUIVALENT , 651 652 821A 822A 823A 824A 841A 842A 843A 844A SN74ALSXXXN-1 SN74ALSXXXDW SN74ALSXXXDW-1 861A , 564 574 646 651 652 821A (Note 1) 823A (Note 1) 841A (Note 1) TABLE 5. CROSS OF EQUIVALENT Tl , Crossover Types: BCT 29821 29822 29823 29824 FCT 821A 822A 823A 824A BCT 29841 29842 29843 29844 FCT 841A -
OCR Scan
BiCMOS BCT Family Am29XXX HARRIS 244 FCT als 245 824A CD54FCT CD54FCT244E CD54FCT245E CCD54FCT CD74FCT SN74ALSXXXN
Abstract: ¬ O Q E fl'lû ? 343 TMP90C840A/841A TOSHIBA 3.4.4 STOP Mode Figure 3.4 (4) is a , TMP90C840A/841A TOSHIBA It is necessary to leave INTO at â'1â' until the second bus cycle of the , '" â'" â'" â'" â'" â'" â'" â'" â'" o o TMP90C840A/841A TOSHIBA 3.5 , function as RD and WR pins, respectively. MCU90-34 10C 1?B4C Q026V11 674 1 TM P90C840A/841A , (Data Read) Figure3.5(1) PortO MCU90-35 â I GDSflTTE 7 0 0 TMP90C840A/841A TOSHIBA -
OCR Scan
TMP90C840A/841 MCU90-30 MCU90-40
Abstract: TMP90C840AN/841AN is a 64-pin shrink DIP product. (SDIP64-P-750) The TMP90C840AF/841AP is a 64-pin flat , /841AN. VREF IZ AGND IZ (ANO) P50 IZ (AN1) P51 IZ (AN2) P52 IZ (AN3) P53 C (AN4) P 5 4 IZ (AN5 , /841 A Figure 2.1-(2) shows pin assigunm ent of the TMP90C840AF/841AF. ï. 8 £ Ã'I ü I ^ ^ , mode) MCU90-1 TDTTEMT GDañ^Sfi 5 4 2 TOSHIBA TMP90C840A/841A NMI ' P80/INT0 â , TMP90C840A Block Diagram MCU90-2 T O T T S MT D D S fl'iS T TOSHIBA 2. TM P90C840A/841A PIN -
OCR Scan
P90C840A/841 P90C840AN/TM P90C841AN TMP90C840AF/841AP
Abstract: )841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL , (H)841A is an 10-bit transparent latch featuring separate D-type inputs for each latch and 3 , . 2. The condition is V, = GND to Vcc, ORDERING INFORMATION TYPE NUMBER 74LVC(H)841AD 74LVC(H)841 ADB 74LVC(H)841APW PINNING PIN 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 SYMBOL OE D0 to D9 NAME AND FUNCTION output , NC = no change DC CHARACTERISTICS FOR 74LVC(H)841A For the DC characteristics see chapter "LVC(H)-A -
OCR Scan
LVCH2841A
Abstract: *504 fc>34 1 TOSHIBA TMP90C840A/841A 3.4.1 RUN Mode Figure 3.4 (2) shows the timing for , -28 ti [ H 7 2 4 cl 0 0 2 0 ^ 5 570 TOSHIBA TMP90C840A/841A 3.4.2 IDLE 1 Mode Figure 3.4 -
OCR Scan
MCU90-27 TGT724C MCU90-28 MCU90-29
Abstract: TOSHIBA TMP90C840A/841A 3.5.5 P o rt4(P 40~ P 4 3) Port 4 is a 4-bit port P4 intended only for the output. All bits of the output latch are initialized to â'0â' by resetting, and â'0â' is generated to the port. In addition to the output port function, it works as an address bus (A16~A19). The selection of the address bus function is made by the control register P4CR. The output port or address bus , -42 c10cî 7 2 ll'î 0 0 2 û clcH Qb5 TOSHIBA TMP90C840A/841A Port 4 Register 7 P4 (FFC8H -
OCR Scan
CU90-42 MCU90-43 D02TDGD
Abstract: (UC/UP) 1 > â  3MÃ" TM P90C840A/841A 002573b of Interrupt Controller 200689 TOSHIBA TOSHIBA Figure 3.3 (8) Block Diagram WTOSS I çp y Interrupt Controller TOSHIBA (UC/UP) b4E D â  TCHTSHI ÃD5S737 EfiM TOSHIBA TM P90C840A/841A The interrupt enable flags provided for all interrupt request channels are assigned to the memory address FFE6H or FFE7H. Setting any of these flags to â'1â' enables an interrupt of the respective channel. These -
OCR Scan
MCU90-24
Abstract: TOSHIBA (UC/UP) t.4E D H TDR7S4R 0D2S72fl 271 â  T0S3 T O SH IB A TM P90C840A/841A The overhead for the entire process from accepting an interrupt to jum ping to an interrupt processing program is 20 states. C General-Purpose Interrupt Processing (SP - 1 ) « -P C H (SP - , TM P90C840A/841A Table 3.3(1) lists the possible interrupt sources. T ab le3 .3(l) Interrupt , /UP) ^ 0 ^ 7 2 4 ^ DQ25731 flbb TOSHIBA TM P90C840A/841A FFOOH+V + O : Number of -
OCR Scan
0000H MCU90-17
Abstract: -40 ROTTEMI 00E6Ti7 ETE TOSHIBA TMP90C840A/841A Port 3 Register 7 P3 (FFC6H) bit Symbol Read , MCU90-41 â  ^ 7 2 4 ^ O G S im fl TOSHIBA TMP90C840A/841A 3.5.5 P o rt4 (P 4 0 ~ P 4 -
OCR Scan
MCU90-42
Abstract: 841A«841B H i Semiconductor gg National 74FCT841A«74FCT841B 10-Bit Transparent Latch with , Description Data Inputs TRI-STATE Outputs Output Enable Latch Enable 7-94 841A-841B Functional , and should not be used to estimate progagation delays. o9 TL/F/10681 -5 7 7-95 841A*841B , Input Toggling 50% Duty Cycle 0.5 2.0 mA IV < V \ o < 7-96 z z s»s < 841A , 500Î1 7-97 841A*841B AC Electrical Characteristics: Symbol Parameter Test Conditions See -
OCR Scan
FCT841A/B FCT373A 74FCT841A/B TL/F/10681-2 TL/F/10681-3 74FCTB
Abstract: 2 TJ IO o n CD 0 1 * TOSHIBA TMP90C840A/841A The interrupt enable flags , -23 TOTVSMR 0 D 2 f i clflG TTi TOSHIBA TM P90C840A/841A Attention should be paid to the -
OCR Scan
Abstract: TOSHIBA TM P90C840A/841A FFOOH + V + 0 : N um ber o f transfer FFOOH + V + 1 : Destination address (Lower) FFOOH + V + 2 : Destination address (Upper) FFOOH+V + 3 : Source address (Lower) FFOOH + V + 4 : Source address (Upper) F F 00H + V + 5 : I * ] - 256 0 -6 4 K 0 -6 4 K I (Transfer m ode) J _ L I 0 0 1 1 = Fix current , 2 0 1 7 4 715 TOSHIBA TMP90C840A/841A Table 3.3 (2) Addresses U pdated by M icro D M A -
OCR Scan
FF06H 0FF00H 0FF73H 0070H CU90-19
Abstract: TOSHIBA TMP90C840A/841A Table 3.3 (1) lists the possible interrupt sources. Table3.3(1) Interrupt Sources Priority order Type 1 2 3 Non maskable 4 5 6 7 7 8 9 10 11 12 13 14 Maskable Vector value â'¢r8 In te rru p t sourece SWI instruction NMI (Inp u t from NMI pin) INTWD (watchdog) Vector value Start address o f general purpose in te rru p t , P90C840A/841A FFOOH + V + 0 : Num ber o f transfer FFOOH + V + 1 : Destination address (Lower -
OCR Scan
0010H 0018H 0020H 0028H 0030H 0038H
Abstract: b4E D TOSHIBA (UC/UP) ^724^ DQ2S731 flbb TO SH IB A TM P90C840A/841A FFOOH+V + O : Number of transfer FFOOH+V+1 : Destination address (Lower) FF00H +V + 2 : Destination address (Upper) FF00H + V + 3 : Source address (Lower) FFOOH + V + 4 : Source address (Upper) ] 1 - 256 0 -6 4 K 0 -6 4 K (Transfer mode) FFOQH + V + 5 : 0 0 1 1 (Note) x , SH IB A TM P90C840A/841A Table 3.3 (2) Addresses Updated by Micro DMA Processing Transfer -
OCR Scan
0FF70H 0FF71H 0FF75H MCU90-18 DG2S733 MCU90-19
Abstract: = -55°C to 125°C, Vcc = 5.0V ±10% Cload = 50pF, Rload = 500il unless otherwise noted. 841A , 125°C, Vcc = 5.0V ±10% Cload = 50pF, Rload = 500il unless otherwise noted. 841A 841B 841C -
OCR Scan
74FCT841 74FCT841T 2841B 2841A QS54/74FCT841T QS54/74FCT2841T MIL-STD-883 2841T
Abstract: /841A in every block. The following is a description of TMP90C840A which can also be applied to , Service CopyRight 2003 TOSHIBA TMP90C840A/841A Wheà the halt status is released by a reset, the status -
OCR Scan
irfb 640 TMP90C840AN TMP90C840 DGMOS mt 6n6 stp 1016 TMP90C840AN/TM P90C841 90C841A 91P640 91PM40 MCU90-140
Abstract: mode) MCU90-1 TDTTEMT GDañ^Sfi 5 4 2 TOSHIBA TMP90C840A/841A NMI ' P80/INT0 â , TMP90C840A Block Diagram MCU90-2 T O T T S MT D D S fl'iS T TOSHIBA 2. TM P90C840A/841A PIN , ) MCU90-4 TÃTTSMT QOEûlbl G37 TOSHIBA 2.2 TM P90C840A/841A Pin Names and Functions The nam , 200689 MCU90-5 ^ 7241 OOSfl'ïbS T73 TOSHIBA TMP90C840A/841A Table 2.2 Pin Names and , pin in th e TM P90C840A using internal ROM, and w ith GND pin in th e TM P90C 841A w ith no internal MERITEK
Original
0603x4 2D 1002 RTA02-2D RTA03-2D RTA02-4D RTA02-4C RTA03-4D RTA03
Abstract: TOSHIBA (UC/UP) t.4E D H TDR7S4R 0D2S72fl 271 â  T0S3 T O SH IB A TM P90C840A/841A The overhead for the entire process from accepting an interrupt to jum ping to an interrupt processing program is 20 states. C General-Purpose Interrupt Processing (SP - 1 ) « -P C H (SP - , TM P90C840A/841A Table 3.3(1) lists the possible interrupt sources. T ab le3 .3(l) Interrupt , /UP) ^ 0 ^ 7 2 4 ^ DQ25731 flbb TOSHIBA TM P90C840A/841A FFOOH+V + O : Number of -
OCR Scan
CYM1841A CYM1841C
Abstract: ¬ O Q E fl'lû ? 343 TMP90C840A/841A TOSHIBA 3.4.4 STOP Mode Figure 3.4 (4) is a , TMP90C840A/841A TOSHIBA It is necessary to leave INTO at â'1â' until the second bus cycle of the , '" â'" â'" â'" â'" â'" â'" â'" â'" o o TMP90C840A/841A TOSHIBA 3.5 , function as RD and WR pins, respectively. MCU90-34 10C 1?B4C Q026V11 674 1 TM P90C840A/841A , (Data Read) Figure3.5(1) PortO MCU90-35 â I GDSflTTE 7 0 0 TMP90C840A/841A TOSHIBA Unisonic Technologies
Original
4N70K 4N70KL-TF3-T 4N70KG-TF3-T QW-R502-841
Abstract: 821 (Note 2) 824A (Note 2) 841A (Note 2) 842A (Note 2 ) 843A (Note 2) TABLE 4. CROSS OF EQUIVALENT , 651 652 821A 822A 823A 824A 841A 842A 843A 844A SN74ALSXXXN-1 SN74ALSXXXDW SN74ALSXXXDW-1 861A , 564 574 646 651 652 821A (Note 1) 823A (Note 1) 841A (Note 1) TABLE 5. CROSS OF EQUIVALENT Tl , Crossover Types: BCT 29821 29822 29823 29824 FCT 821A 822A 823A 824A BCT 29841 29842 29843 29844 FCT 841A MERITEK
Original
RTA03-2C 0402x RTA03-4 sn 8002 RTA03-4C RTA02-8D RTA03-8C
Abstract: *504 fc>34 1 TOSHIBA TMP90C840A/841A 3.4.1 RUN Mode Figure 3.4 (2) shows the timing for , -28 ti [ H 7 2 4 cl 0 0 2 0 ^ 5 570 TOSHIBA TMP90C840A/841A 3.4.2 IDLE 1 Mode Figure 3.4 -
OCR Scan
58H/8 MCU90-21
Abstract: (UC/UP) 1 > â  3MÃ" TM P90C840A/841A 002573b of Interrupt Controller 200689 TOSHIBA TOSHIBA Figure 3.3 (8) Block Diagram WTOSS I çp y Interrupt Controller TOSHIBA (UC/UP) b4E D â  TCHTSHI ÃD5S737 EfiM TOSHIBA TM P90C840A/841A The interrupt enable flags provided for all interrupt request channels are assigned to the memory address FFE6H or FFE7H. Setting any of these flags to â'1â' enables an interrupt of the respective channel. These -
OCR Scan
O09P TMS29LF400T TMS29LF400B 8-BIT/262144 16-BIT DQ15/A-1
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