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Part : F82C206J Supplier : Intel Manufacturer : Rochester Electronics Stock : 1,980 Best Price : $9.05 Price Each : $9.05
Part : PT82C206F-LV Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 13,082 Best Price : $7.66 Price Each : $7.66
Part : F82C206 Supplier : Opti Technologies Manufacturer : Bristol Electronics Stock : 6 Best Price : - Price Each : -
Part : F82C206QE Supplier : Opti Technologies Manufacturer : Bristol Electronics Stock : 113 Best Price : - Price Each : -
Part : P82C206-G Supplier : Chips and Technologies Manufacturer : Bristol Electronics Stock : 9 Best Price : $5.60 Price Each : $11.20
Part : P82C206-H1 Supplier : Chips and Technologies Manufacturer : Bristol Electronics Stock : 410 Best Price : $6.0375 Price Each : $10.50
Part : P82C206-H6058J Supplier : Chips and Technologies Manufacturer : Bristol Electronics Stock : 23 Best Price : $9.3750 Price Each : $15.00
Part : P82C206C1 Supplier : OPTI Manufacturer : Bristol Electronics Stock : 15 Best Price : - Price Each : -
Part : P82C206F-1 Supplier : Chips and Technologies Manufacturer : Bristol Electronics Stock : 183 Best Price : - Price Each : -
Part : SAB82C206-N Supplier : Siemens Manufacturer : Bristol Electronics Stock : 120 Best Price : $6.5250 Price Each : $10.8750
Part : UM82C206L Supplier : United Microelectronics Manufacturer : Bristol Electronics Stock : 9 Best Price : $11.25 Price Each : $15.00
Part : PT82C206FLV Supplier : Cirrus Logic Manufacturer : ComSIT Stock : 220 Best Price : - Price Each : -
Part : P82C206FI Supplier : Chiplus Semiconductor Manufacturer : Chip One Exchange Stock : 42 Best Price : - Price Each : -
Part : P82C206H1 Supplier : Chiplus Semiconductor Manufacturer : Chip One Exchange Stock : 41 Best Price : - Price Each : -
Part : P82C206J Supplier : Chips and Technologies Manufacturer : Chip One Exchange Stock : 10 Best Price : - Price Each : -
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82C206 Datasheet

Part Manufacturer Description PDF Type
82C206 Chips and Technologies Integrated Peripherals Controller Original
82C206 Chips and Technologies CS8221: NEW ENHANCED AT/286 CHIPSet Scan
82C206 Chips and Technologies NEAT CHIPset for 12MHz to 16MHz systems Scan
82C206 OPTi Integrated Peripheral Controller Scan
82C206 OPTi OPTi-386WB PC/AT Chipset Scan
82C206 OPTi OPTi-486SXWB PC/AT Chipset Scan
82C206 OPTi PC / AT Chipset Scan

82C206

Catalog Datasheet MFG & Type PDF Document Tags

82C206

Abstract: CS8220 interval counter, a timer, or as a gated rate/pulse generator. 82C206-INTEGRATED PERIPHERALSCONTROLLER , system address bus used to address various registers of the 82C206. It is tied to the external bus (XA , 82C206. In a PC/AT architecture based design this pin should be wire-ored to PC/AT's IOCHRDY signal , 82C206. When low, the 82C206 is essentially disconnectedfrom the system bus. The 82C206 at this time , keyboardinterfacecontroller. Figure 1 illustrates the subsystems containedwithin the 82C206. . A Real Time Clock (RTC
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CS8220 82C206 datasheet chipset 82c206 cs8220 neat 7682, 8-BIT oscillator 82C206F

SAB8259

Abstract: SAB82C206 other register o f various m odules o f the SAB 82C206. W hen low , the SAB 82C206 is essentially , system address bus used to address various registers of the SAB 82C206. It is tied to the external bus (X , cycles to SAB 82C206. In a P C /A T architecture based design this pin should be w ire-ored to PC /A T , 2 illustrates th e subsystems contained w ithin the SAB 82C206. T w o D M A controllers are , channels are provided in the SAB 82C206. These channels are allocated to tw o cascaded controllers (INTC1
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SAB8259 SAB82C206 4311 bcd decoder SAB 8259 Siemens eoi sab8237 PL-CC-84 10CHRDY B2C206 A17-A23 74LS612 ADSTB16

82C206

Abstract: P54A OPTi, Inc. OPTi 2525 Walsh Avenue Santa Clara, CA 95051 (408) 980-8178 Fax: (408) 980-8860 ® Product Alert Date: September 13, 1994 Product: 82C206 84-Pin PLCC Title: OrCAD Library Update NOTE This Product Alert was previously released as P54AWB-V Product Alert PA-0013. A problem has been found in the OrCAD library part generated at OPTi for the 84-pin PCLL version of the 82C206. , 66 65 67 63 64 61 62 INTR 70 OUT1 OUT2 20 19 VDD VDD 32 75 82C206 NEW
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P54A opti opti 82c206 82c206 qfp opti+82c206 PA0013 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15

ks83c206

Abstract: opti 82c206 CPU accesses the 82C206's internal registers. This pin must be pulled up by an external resistor. In , read out the contents of the 82C206's internal registers. During CPU I/O write cycles, they are input pins that allow the CPU to program the contents of the 82C206's internal registers. During DMA cycles , control signal used by the CPU to read the 82C206's internal registers. In an active DMA cycle, it is an , by the CPU to read the 82C206's internal registers. In an active DMA cycle, it is an output control
OPTi
Original
ks83c206 82c206 ipc A1726 82c206 pqfp HC-49/TI 74LS612 8254 cascading KS83C206 100-P

74ls612

Abstract: CHIPset for 80286 Memory Organization 82C215, 82C206 AT/286 CHIPSetâ"¢ (NEAT) Optimized for OS/2 operation Shadow RAM , , the 82C215 Data/ Address Bus Buffer and the 82C206 Integrated Peripherals Controller. Each of these 4 , popular 82C206 Integrated Peripherals Controller completes the chipset. It includes all the AT peripheral
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CS8221 CHIPset for 80286 82C605 chipset 80286 146818 ATS 16Mhz 82C211 82C212 640KB 82C37 82C59

82C206

Abstract: SAB 8259 ta tu s o r o th e r re g is te r o f v a rio u s m o d u le s o f th e S AB 82C206. W h e n lo w , rio u s re g is te rs o f th e SAB 82C206. It is tie d to th e e x te rn a l b u s (X A bus) in a P , cycles) fo r I/O re a d /w rite c y c le s to SAB 82C206. In a P C /A T a rc h ite c tu re based d e sig , SAB 82C206. A real tim e c lo c k (RTC) is in c lu d e d in th e SAB 82C206 fo r m a in ta in in g , e ls are p ro v id e d in th e SAB 82C206. These ch a n n e ls are a llo c a te d to tw o c
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206-N Q67120-P286

386SL

Abstract: 82360SL DS1632 connects directly to pin 14, PWR GOOD, of the 82C206. When PF becomes active low, the 82C206's , of the 82C206's interrupt request pins (IRQ pins) to act as a warning that VCC is out of tolerance or sent to the µp as an interrupt. VCCO from the DS1632 connects directly to the 82C206's VCC pin. VCCO from the DS1632 can provide for the 82C206's normal operating voltage and current requirements , directly to the 82C206 RESET input pin, which resets the 82C206's DMA control registers and interrupt
Dallas Semiconductor
Original
386SL 82360SL DT-26S CHIPS TECHNOLOGIES 82360 DS-VT-200

SAB82C206

Abstract: 82c206f 82C206. W hen low , the SAB 82C206 is essentially disconnected fro m the system bus. The SAB 82C206 at , the system address bus used to address various registers o f the SAB 82C206. It is tied to the , ait-states (as counted by SCLK cycles) fo r I/O re a d /w rite cycles to SAB 82C206. In a PC/AT , illustrates the subsystem s contained w ith in the SAB 82C206. A real tim e clock (RTC) is included in the , t channels are provided in the SAB 82C206. These channels are allocated to tw o cascaded
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D0315 82C206-N

P82C206

Abstract: f82c206 iste rs o f th e 82C206. It is tie d to th e e x te rn a l bus (XA bus) in a PC/AT c o m p a tib le d e , ) fo r I/O re a d /w rite cycle s to 82C206. In a PC/AT a rc h ite c tu re based d e sig n th is p in s , 82C206. W hen low, th e 82C206 is e sse n tia lly d isco n n e cte d fro m th e system bus. T he 82C206 , CHIPS 82C206- IN TEG RATE D PERIPHERALS CO NTRO LLER T he 82C206 is a LSI im p le m e n ta tio n o f , subsystem s c o n taine d w ith in th e 82C206. Two D M A C o n tro lle rs are p ro vid e d and c o n
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P82C206 KZh Series AN8254 chips p82c206 MC146818 NEC iAPX86

yg 2822

Abstract: RAS 0510  PRELIMINARY CS8221 NEW ENHANCED AT (NEATâ"¢) DATA BOOK 82C211 /82C212/82C215/82C206 (IPC , performance 4 chip VLSI implementation (including the 82C206 IPC) of the control logicused on the i IBM , and the 82C206 Integrated Peripherals Controller (IPC). The NEAT CHIPSetâ"¢ supports the local CPU , in the 82C215. The 82C206 integrated Peripherals Controller is an integral part of the NEAT CHIPSetâ"¢. It is described in theâ'ž82C206 Integrated Peripherals Controller data book. System Overview The
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yg 2822 RAS 0510 cs8221 neat Waukesha 6670 82C631 2021G 2-221-B CHIPS/280 CHIPS/250 CHIPS/230 CHIPS/450

chipset 82c206

Abstract: 82C206 Real Time Clock is an active high signal used on the 82C206. Refresh 52 I REFREQ REFRESH REQUEST , /82C212/82C215/82C206 (IPC) CHIPSet1 â  100% IBMâ"¢ PC/AT Compatible New Enhanced CHIPSetâ"¢ for 12MHz , 4 chip VLSI implementation (including the 82C206 IPC) of the control logic used on the IBMâ , Data/Address buffer and the 82C206 Integrated Peripherals Controller (IPC). The NEAT CHIPSetâ , in the 82C215. The 82C206 Integrated Peripherals Controller is an integral part of the NEAT CHIPSet1
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ARCHITECTURE OF 80286 bios chip manufacturer 80286 chipset LIM EMS 4.0 refresh logic iAPX 88 Book 84-PIN P82C211/212/215/206 PLCC-84 F82C211/212/215/206 PFP-100

r2kl

Abstract: tea 1601 t /82C206 (IPC) CHIPSetâ"¢ â  100% IBM'" PC/AT Compatible New En-| hanced CHIPSetâ"¢ for 12MHz to 16MHz ' , implementation (including the 82C206 IPC) of the control logic used on the JBM'" Personal Computer AT. The , and the 82C206 Integrated Peripherals Controller (IPC). The NEAT CHlPSetâ"¢ supports the local CPU , in the 82C215. The 82C206 integrated Peripherals Controller is an integral part of the NEAT CHlPSetâ , 8 bit or 16 bit devices. The X bus refers to. the peripheral bus to which the 82C206 IPC and other
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r2kl tea 1601 t NEC 2561 tea 1601 80286 address decoder block diagram of mri machine 15C7AT CA95134

82C211

Abstract: P82C211 ASRTC ADDRESS STROBE to Real Time Clock is an active high signal used on the 82C206. Refresh 52 1 , CS8221 NEW ENHANCED AT (NEATâ"¢) DATA BOOK 82C211 /82C212/82C215/82C206 (IPC) CHIPSetâ"¢ â  100% IBMâ , NEAT CHIPSet7" is an enhanced, high performance 4 chip VLSI implementation (including the 82C206 IPC , and EMS Memory controller, the 82C215 Data/Address buffer and the 82C206 Integrated Peripherals , bit generation and error detection logic resides in the 82C215. The 82C206 Integrated Peripherals
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P82C211 AT-286 S2-221-B E4000-H 82C21516 xa1s GGD11S7 QDG11S

opti 82c206

Abstract: 82C295 non-cacheable regions · Programmable cache and DRAM read/write cycles Figure 1-1 82C295/82C206-Based , response to a DMA or master hold request. It is connected to the HLDA pin of the 82C206. 8-Bit DMA Transfer , generate the OSC/12 (timer output) clock to the 82C206. The OSC signal is also buffered externally for use , : - 82C295 System Controller, 160-pin PQFP (Plastic Quad Flat Package) - 82C206 Integrated Peripherals , Control OPTi 82C206 IPC Buffer DACKs DRQs IRQs XD[15:0] Keyboard Controller EPROM BIOS Buffer
OPTi
Original
486SLC2 IBM 486slc diagram of interface 8K*8 RAM and rom with 8086 MP Cyrix 387SX AT chipset CX486slc Cyrix 486slc GATEA20 128KB 256KB 82C295/82C206-B CX486SLC

82C206

Abstract: chipset 82c206 CONTROLLER - TIMER / COUNTERS IPC ISA 82C206 PCI m/s PCI m/s POWER MANAGEMENT PCI BUS
STMicroelectronics
Original
PBGA388 PC keyboard CIRCUIT diagram VGA ramdac VGA to tft vga crtc mouse controller 64-BIT 135MH

CS8220

Abstract: 82C201 82C206. 17 o 203MSTR This signal corresponds to MASTER qualified with REFRESH. 18 o CS287 A low signal , the Integrated Peripherals Controller, 82C206, (IPC), the AT DMA cycle can be tuned to match various , , it generates PORTC control signals. For systems that do not use the Real-Time Clock in the 82C206 , latching of the register address by the Real-Time Clock. For systems, which use the 82C206 (which
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82C202A 82C202 8042CS P82C202A 82C201 8220A 80286 schematic T-bZ-33-Zl 82a204 00DD43 T-52-33-21 CS8220A-10/12 384KB

opti 82c206

Abstract: CX486slc /82C206-Based System Block Diagram 386SX or CX486SLC Numerics Coprocessor* Local Bus Peripherals , connected to the HLDA pin of the 82C206. 8-Bit DMA Transfer Address Strobe: The system controller uses this , 14.318MHz oscillator input used to generate the OSC/12 (timer output) clock to the 82C206. The OSC signal is , (Plastic Quad Flat Package) - 82C206 Integrated Peripherals Controller, 84-pin PLCC (Plastic Leaded Chip , Buffer Control OPTi 82C206 IPC Buffer DACKs DRQs IRQs XD[15:0] Keyboard Controller EPROM
OPTi
Original
386sx chipset Cyrix CX486slc diagram of interface 64K RAM with 8086 MP amd 386SX ma6# PC intel MOTHERBOARD CIRCUIT diagram 82C291 80387SX 82C291/82C206-B 1MB-16MB 16K-128K 160-P

Motherboard IBM t21

Abstract: CS8220 the module select function in the 82C206. 17 o 203MSTR This signal corresponds to MASTER qualified , Controller, 82C206, (IPC), the AT DMA cycle can be tuned to match various compatibility and performance goals , generates PORTC control signals. For systems that do not use the Real-Time Clock in the 82C206 Integrated , the register address by the RealTime Clock. For systems, which use the 82C206 (which internally
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Motherboard IBM t21 RIF 206 82c206 schematic PC MOTHERBOARD ibm rev 1.5 ibm at motherboard 80286 000000H 2-202B 68-PIN PLCC-68

PIN DIAGRAM OF 80286

Abstract: 82C206 the Real Time Clock at the SAB 82C206. ASRTC 82 0 Refresh Control REFREQ 52 I Refresh , , the SAB 82C215 data/address buffer and the SAB 82C206 integrated peripheral controller provide a , reset the AT-bus, the SAB 82C206, the 8042 keyboard control ler, and the SAB 82C212 memory controller , patible timer controller of the SAB 82C206 IPC in a PC-AT implementation. Refresh# REF# is an active low , 82C206 to enable the tone signal for the speaker. Timer Out 2 TMROUT2 is an active high input from the
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PIN DIAGRAM OF 80286 SAB 80287 kc 4369 80286 data bus MD 80287 80286 82c206 D0581

opti 82c206

Abstract: 82c283 82C283 and a standard peripheral controller like OPTi's 82C206 or the 82C100 (with Dallas Semiconductor , [16:1] XA0 245 (x2) SA[16:0] SA ROM GA20 A[23:17] 245 LA[23:17] A[9:1] A[23:16] OPTi 82C206 XD[7:0 , indication. Hold request from the 82C206 IPC. Hold acknowledge 1 indicates a CPU HLDA was caused by HRQ, not , between the 82C206 hold request (HRQ) and the 82C283 refresh request, to determine who receives bus , acknowledges by asserting HLDA, then the 82C283 sends HLDA1 to the 82C206 to acknowledge the request. The
OPTi
Original
387SX opti 82c283 vlsi 386sx ADS8 opti 82c100 286SX 386SX/AT DS1287

82c822

Abstract: 82C206 processor solution consists of the Python Chipset and the 82C206 Integrated Peripheral Con­ troller (IPC , CPU warm reset â'¢ Port B and Port 92h Register 2.3 82C206 (IPC) Integrated Peripherals Controller The 82C206 IPC provides two DMA controllers, two interrupt controllers, one timer/counter, and , signal goes to the 82C206 IPC to indicate that the processor is executing an interrupt acknowledge cycle , 1.19MHz output for use in the PC/AT counter/timer subsystem in the 82C206 IPC. 3.1.2.2 Data Bus
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82c822 opti viper la2 -d22 a65 82C546/82C547 512KB 128MB 0G0025

82C206

Abstract: 4116 DRAM 16Kx1 SAB 82C215 data/address buffer and the SAB 82C206 integrated peripheral controller provide a highly , reset the AT-bus, the SAB 82C206, the 8042 keyboard control­ ler, and the SAB 82C212 memory , Time Clock at the SAB 82C206. Refresh Control REFREQ 52 I REF# 58 I/O Siemens , generated by the 8254 com­ patible timer controller of the SAB 82C206 IPC in a PC-AT implementation , 82C206 to enable the tone signal for the speaker. Timer Out 2 TMROUT2 is an active high input from the
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82C558 4116 DRAM 16Kx1 82C556/82C557/82C558 82C557 208-P

82C206

Abstract: 82C283 and a standard peripheral controller like OPTi's 82C206 or the 82C100 (with Dallas Semiconductor , [16:1] XA0 245 (x2) SA[16:0] SA ROM GA20 A[23:17] 245 LA[23:17] A[9:1] A[23:16] OPTi 82C206 XD[7:0 , indication. Hold request from the 82C206 IPC. Hold acknowledge 1 indicates a CPU HLDA was caused by HRQ, not , between the 82C206 hold request (HRQ) and the 82C283 refresh request, to determine who receives bus , acknowledges by asserting HLDA, then the 82C283 sends HLDA1 to the 82C206 to acknowledge the request. The
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0031S7D SAB82C211 T-52-33-55
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