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CAR0812DC GE Critical Power CAR Series, Input: DC, Input Range: 85 - 264V, Vout: 12V, Iout: 70.8A, Efficiency: 93% visit GE Critical Power
CAR2548FP GE Critical Power CAR Series, Input: AC, Input Range: 90 - 264V, Vout: 48V, Iout: 52A, Efficiency: 92% visit GE Critical Power
CAR1612FP GE Critical Power CAR Series, Input: AC, Input Range: 85 - 264V, Vout: 12V, Iout: 134A, Efficiency: 95% visit GE Critical Power
FLT012A0Z GE Critical Power FLT012A0Z/FLT012A0-SZ: Input Filter Module, 75Vdc Input Voltage Maximum; 12A Output Current Maximum visit GE Critical Power
CAR1212FP GE Critical Power CAR Series, Input: AC, Input Range: 85 - 264V, Vout: 12V, Iout: 104A, Efficiency: 89% visit GE Critical Power
CAR2548TN GE Critical Power CAR Series, Input: AC, Input Range: 90 - 264V, Vout: 54V, Iout: 52A, Efficiency: 92% visit GE Critical Power

8255 input output in all mode

Catalog Datasheet MFG & Type PDF Document Tags

8255 interfacing with 8086

Abstract: 8255 interface with 8051 . The 8255 can be programmable in three different modes: · Mode 0: simple unidirectional input/output without handshake · Mode 1: unidirectional input/output with handshake via some pins of port C · Mode 2 , modes. As there are 3 ports in 8255 and each one of them can be programmed as an input or output port , . Change the setting of the dip switch and press the button marked `port A mode 1 input' in the 8255 , be studied. configuration 1 2 3 4 Port A Port B Port C Mode 0, input Mode 0, output
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INTEL SDK-80

Abstract: 8255 programmable peripheral interface applications Module To 8255 In te rfa c e . 10 Mode 0 Interface S o f tw a re , byte oriented Input/ Output interfaces. Through the use of the 8255, the I/O interface design task is , -P C n) 1 =IN P U T 0 = O U T PU T Part C Bits P C 7 - P C 4 Output = 0 Mode Control W ard = , control logic. If a read of Port C is issued when the 8255 is configured in Mode 1, the software will , Mode 1 input and Port B Mode 1 output. Port C Bits 6 & 7 Output = 0 Port A Input = 1 Port A Mode =
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PIA 8255

Abstract: 8255 PIO -48 has two 8255 chips. Each chip has three 8 bit ports which can be programmed as input or output by , all output. Port C may be split into two 4 bit sections each of which may be input or output. The , 3 modes (mode 0-2). In the first mode (mode 0) the 8255 provides simple I/O for 3, 8 bit ports , Input Input Input Sets All of Port B To Output Output Input Input Output Output Input , SYMBOL 8255 82C55 MIN MAX MIN LIMITS Input Voltage High Input Voltage Low Output
Blue Chip Technology
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PIA 8255 8255 PIO pio 8255 8255 interfacing with 8086 8255 keyboard interfacing 8255 PIA pin diagram PIO-48

PIO-24

Abstract: pc dio-48 several different input output conditions. Up to 4 interrupt sources, from the pair of 8255's, may be , x 82C55 Power: 325mA @ 5v Weight: 0.15kg; 0.35lb Size: 10 X 14cm Mode 0:Simple input/output Mode 1: Strobed input/output with interrupts Mode 2: Strobed bi-directional bus input/output with , PC DIO 24 PC DIO 24 FEATURES DESCRIPTION n 24 TTL compatible digital input/output lines , : 10 x 13.5cm PC I/O HARDWARE 37D PINOUT "24 TTL compatible digital input/output lines." A
Brainboxes
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PIO-24 DIO24 DIO48D DI-406 DI-824 DI-516 pc dio-48 metrabyte PIO-12 keithley pio-24 pio24 0100H-03FFH 0300H-0303H DIO48

DM5806

Abstract: 8255 PPI in the S2 DIP switch discussion. The DM5806 operating modes are: Mode 0 - Basic input/output. Lets , port. Mode 1 - Strobed input/output. Lets you transfer I/O data from Port A or Port B in conjunction , mode 1 Group B Port C Upper 0 = output 1 = input Group A 8255 Port I/O Flow Direction and , 8255 in Mode 1, the lines of Port C function as control lines, some as outputs and some as inputs , Program Port A digital output lines BA + 0 8255 PPI Port B Read Port B digital input lines
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8255 PPI 8255 PPI INTEL 8259 Interrupt Controller 8254 TIMER Control word 8255 PPI 8255 interface using c language DM5806/DM6806 DM6806

PXI-6533

Abstract: 8255 PPI INTEL user-defined input pattern occurs. In change detection mode, the PXI-6533 monitors the input lines and , 32 digital I/O lines individually for input or output or as four 8-bit ports. The ports can be , 24 mA when set logic low or high, respectively. In wired-OR mode, outputs are tri-stated when set , each handshaking mode with programmable delays and polarities as indicated in Table 1 , the use of FIFO buffering, 8255 emulation mode offers much higher data transfer rates than with an
National Instruments
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DAQDIO 8255 PPI Chip Peripheral interface 8255 intel 430FX TBX-68 PPI 82C55 430FX

intel 8255

Abstract: 8255 pin diagram REGISTER AND ALL PORTS ARE SET TO THE INPUT MODE. INPUT FOR PORT A. INPUT FOR PORT B. INPUT FOR PORT C , CFI2550B is compatible with Intel 8255. It is also compatible in I/Os except for the fact that each bidirec , Logic Corporation 1989,1990 238 CFI2550B PIN DESCRIPTION: INPUT 8255 CFI2550B DI WRN RDN CSN Al, AO RST PAI PBI PCI OUTPUT DO PAO PBO PCO PAOE PBOE PCOE DATA INPUT. A "LOW" ON THIS , STANDARD 8255 The following diagram shows how to make a compatible standard 8255 using input and
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intel 8255 8255 pin diagram intel 8255 pin diagram 8255 a pin diagram 8255 8255 input output in all mode CFI25S0B

8255 pin diagram

Abstract: 100-pin SCSI female connector /192 TTL digital I/O lines · Emulates mode 0 of 8255 PPI · Buffered circuits for higher driving capacity than 8255 · Multiple-source interrupt handling · Interrupt output pin for simultaneously , -1753E. The card emulates mode 0 of the 8255 PPI chip, but the buffered circuits offer a higher driving , , B2, C2, A3, B3 and C3. Users can configure each port as input or output via software. Easy to , of Input/Output Lines Industrial users are needing more and more digital I/O lines to transmit data
Advantech
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PCI-1753 PCL-10268 ADAM-3968 100-pin SCSI female connector 100 pin scsi ppi 8255 data sheet PPI 8255 interface PCI-1753/1753E PCI-1753E ADAM-3968/50

8255 application note

Abstract: 8255 pin diagram guarantee a high, stable output state. 2. Terminated Input. If the driver is in a power-off condition, or , a 0V differential input voltage to the receiver, the receiver output will remain in a high state , receiver offers ±100 mV threshold sensitivity, in addition to common mode noise protection. Features â , Input Voltage (RIN+, R,NJ -0.3V to (Vcc +0.3V) Output Voltage (ROUt) -0.3V to (Vcc +0.3V) Maximum , output voltage for any of the following conditions: 1. Open Input Pins. The DS90C402 is a dual receiver
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DS90C401 DS90C402M DS10000B-2 8255 application note 8255 application M06A 8255 pin configuration TIA/EIA-644 DS100006

RADIO SHACK PARTS CROSS REF

Abstract: CIO-AD08 enters HOLD also. The SSH16 remains in HOLD mode while the CIOA D ^ samples channles 1, 2, 3 .N. All , industry standard architecture around which almost all software is de signed to operate. In addition to , CIO-AD16 & AD16/F High Speed 16 Channel 12 Bit Analog Input, 2 Channel 12 Bit Analog Output with 32 , CONVERTER 12 BIT (1/4095) 674 = 50KHz 16 SINGLE ENDED OR 8 DIFFERENTIAL A/D INPUT SWITCH 8255 DIGITAL , features, all at a lower cost. Installed in any IBM PC/XT/AT/PS30 or compatible computer the CIO-AD16 turns
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RADIO SHACK PARTS CROSS REF CIO-AD08 context plus fire alarm control panel DAS-16 PIO-96 DAs 08 IEEE-488 C488-2M PD7210

intel 8251 USART

Abstract: intel IC 8255 Computer Hardware Reference Manual or the "8255 Applica tion Note." Mode 0 is a basic input/output , operating mode, the user may also specify the direction of data flow, input or output from the 8255's. At , are set to the low output state. Interrupt Mechanism. When the 8255 is pro grammed to operate in mode , ) Mode 0 Output 8255 #2 Port 4 (A) Mode 0 Input Port 5 (B) Mode 0 Input Port 6 (C) Mode 0 Input The , unidirectional input/output, and bidirectional ports indicated in Table I. Therefore, the I/O interface may be
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intel 8251 USART intel IC 8255 SBC 8251 intel 8251 Fluke 8375 ic 8255 intel AP-26 PL/M-80 ICE-80 AP-16 AP-15

ADC-7109

Abstract: Peripheral interface 8255 with ADC "OUTPUT" may be used as a byte identification flag (in the handshake mode only). With the SEND input , pin serves as a load strobe used in handshake mode. PIN FUNCTION DESCRIPTION 21 MODE Input Lowâ , device enters the handshake mode when the MODE input is held high after new data has entered the output , will be delayed until the data is stable. While in the handshake mode, the MODE Input will be ignored , ) shows the sequence of the output cycle with the SEND input held high. The handshake mode is entered
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ADC-7109 Peripheral interface 8255 with ADC ADC 7109 intel 8055 ADC7109 8255 intel microprocessor 02048-1194/TEL 339-3000/TLX174388/FAX 339-3000/TLX 174388/FAX

100 pin scsi

Abstract: PCL-10268 TTL digital I/O lines · Emulates mode 0 of 8255 PPI · Buffered circuits for higher driving capacity than 8255 · Multiple-source interrupt handling · Interrupt output pin for simultaneously triggering , emulates mode 0 of the 8255 PPI chip, but the buffered circuits offer a higher driving capability than , , A3, B3 and C3. Users can configure each port as input or output via software. Easy to Install , of Input/Output Lines Industrial users are needing more and more digital I/O lines to transmit data
ELFA
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SCSI 2 100pin connector advantech PCI 1753 PCLD-785B PB20 8255 parallel port ADAM-3968s

PCI-DIO-32HS

Abstract: 8255 Chip defined input pattern occurs. In change detection mode, the 6533 monitors the input lines and captures , configure the 32 digital I/O lines individually for input or output or as four 8-bit ports. The ports can , . You can customize each handshaking mode with programmable delays and polarities as indicated in Table , wider data path, and the use of 8255 6.67 4 4 FIFO buffering, 8255 emulation Emulation mode , channels. 32 input/output 4 dedicated output and control 4 dedicated
National Instruments
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PCI-DIO-32HS AT-DIO-32HS 8255 Chip 8255 intel 8255 operating modes R6850-D1 PCI-DIO NT/95 NT/95/3 440FX

8255 PIO

Abstract: amstrad . 01271014.doc Input Connections Page 9 a Input Mode When all the signals to be measured have a , use the differential input mode. In this mode the input signals are subtracted by the circuitry on , negative connection to pin 1 (input 0) and so on in pairs. In the differential mode only 8 input signal , , 0=Output, 0=Mode 0, 0=Output, 0=Output, 00=Mode 0, 1X=Mode 2. 0=Inactive, 1=Input. 1=Input , this module. The 8255 can operate in one of 3 modes (mode 0-2). In the first mode (mode 0 ) the 8255
Blue Chip Technology
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ADC-42 amstrad microprocessor 8255 application amstrad 4000 ADC 8 bits 0-10v 8255 RAM keyboard sensing using adc 378-37F 380-38F

d8255c

Abstract: i8255 Reset_Board() { wr_to_8255(D8255_CC, D82_BCO); /* put 8255 in output mode */ wr_to_8255(D8255_PA, D8x_DLE , ports, which can be switched between input and output. A fourth internal register controls the , the technical accuracy of the content provided in all Analog Devicesí Engineer-to-Engineer Notes , ) { /* switch 8255 to input */ wr_to_8255(D8255_CC, D82_BCI); /* first access */ wr_to_8255(D8255_PA, D8x_DLE , PPORT back to output */ wr_to_8255(D8255_CC, D82_BCO); wr_to_8255(D8255_PA, D8x_DLE); data = (rh
Analog Devices
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ADSP-2181 ADSP2181 ADSP-2183 d8255c i8255 memory interface 8255 C2000HS 0x400504 0x3B0001 EE-158 ADSP-218 ADDS-2181-EZ-

sd 7402

Abstract: SP200 (5) Receivers 1µA Shutdown Mode WakeUp Feature in Shutdown Mode Tri­State Receiver Outputs Ideal , power supply drain to 1µA. A WakeUp function keeps the receivers active in the shutdown mode (SP207HB , Power-Off Output Resistance 300 Output Short Circuit Current RS-232 INPUT (RECEIVER) Voltage Range ­15 , keeps the receivers active in the shutdown mode, unless disabled by the EN pin. TGoddard/SP207H , will commit the output of the receiver to a high state. In the "power off" state, the output
Sipex
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SP207H SP211H SP200 SP211HB SP207 sd 7402 SP211 SP207H/SP211H

SP8528

Abstract: SP8528AN preserve the dynamic performance of the device. In single ended mode, the analog input signal should be , component, the output signal will be degraded. In full differential mode, the high and low side board , . VCC GND Internal VCC REFL 12 REFL VREF DAC Csample P +IN INPUT SWITCHES , input to GND . -0.3 to VCC +0.3V Digital output to GND , 4 20 150 80 3 70 4.5 3 30 150 80 For all FFT's (Full Differential Mode) If
Sipex
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SP8528 SP8528JN SP8528AS SP8528AN SP8528BN SP8528BS SP8528DS/01 SP8528JS

P8544

Abstract: pin diagram of IC 7402 sample mode and places the DOUT (Data Output) pin in a high impedance state. SP8542/8544DS/01 FEATURES Conversion is initiated by falling edge on CS in slave mode at which point the selected input , with SPI, QSPI and MICRO WIRE serial communication protocols. Output Data Format data. In this mode , . In slave mode operation, CS is brought high between each conversion so that all conversions are , -AGND-Analog Ground Pin 5-VSS Digital Ground Pin 6-SCLK-Serial Clock Input Pin 7-DOUT Digital Data Output Pin 8
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P8544 pin diagram of IC 7402 IC 7402 pin diagram LTvq 8 pin IC chip 4953 ADC+2921 P8542/S SP8542 SP8544 SP8542/8544DS/ SP8542/8544

RS 7402 pin output

Abstract: WakeUp function keeps the receivers active in the shutdown mode (SP207HB and SP211HB only). +5V INPUT 9 , . Charge Pump - Phase 4 SHUTDOWN MODE The SP207HB, SP211H and SP211HB all feature a control input which , all the receivers in an enabled state when the device is in the shutdown mode. With only the receivers , Shutdown Mode WakeUp Feature in Shutdown Mode Tri­State Receiver Outputs Ideal for V.34 and High Speed RS , Power-Off Output Resistance 300 Output Short Circuit Current RS-232 INPUT (RECEIVER) Voltage Range ­15 Logic
Sipex
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RS 7402 pin output 400KOHM SP207HBET SP211HBCA SP211HBCT SP211HBEA SP211HBET
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