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74ls112 pin diagram

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74ls112 pin diagram

Abstract: 74LS112 Specification Flip-Flops 74LS112, S112 LOGIC DIAGRAM FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS , Signetics Logic Products 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product , HIGH-to-LOW transition of CP. TYPE TYPICAL fHAX TYPICAL SUPPLY CURRENT (TOTAL) 74LS112 45MHz 4mA 74S112 , -2.0mA lIL, and a 74LS unit load (LSul) is 20//A l,H and -0.4mA lIL. PIN CONFIGURATION LOGIC SYMBOL , otherwise noted.) PARAMETER TEST CONDITIONS1 74LS112 74S112 Min Typ2 Max Min Typ2 Max UNIT
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N74S112N N74LS112N N74LS112D N74S112D 74ls112 pin diagram 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LSH2 74LS 125MH 1N916

74ls112 pin diagram

Abstract: 74ls112 pin configuration Flip-Flops 74LS112, S112 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE §D Asynchronous set , are initiated by the HIGH-to-LOW transition of CP. TYPE 74LS112 74S112 TYPICAL i MAX 45MHz 125MHz , In. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) ®,[I «,E · > iE * o iG E 0,11 , Product Specification Flip-Flops 74LS112, S112 DC ELECTRICAL CHARACTERISTICS PARAMETER (Over recommended operating free-air temperature range unless otherwise noted.) 74LS112 TEST CONDITIONS1 Min Typ2
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1N3064

74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112, S112 LOGIC DIAGRAM FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd CP J K Q Q , Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , the HIGH-to-LOW transition of CP. TYPE TYPICAL fHAX TYPICAL SUPPLY CURRENT (TOTAL) 74LS112 45MHz 4mA , 50nA l,H and -2.0mA l,L, and a 74LS unit load (LSul) is 20,uA l,H and -0.4mA l,L. PIN CONFIGURATION , Logic Products Product Specification Flip-Flops 74LS112, S112 DC ELECTRICAL CHARACTERISTICS (Over
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S112

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H/74H106 4 â'" 0 â'"15 â'" Q 1-0 CP 6-0 CP 16â'" K _ CD Q 0-14 « 0 D62 54S/74S112, 54LS/74LS112 4 10 3â'" 1 2 Sd J 0 -5 1-i J S° 0 CP 13-0 CP K _ Co Q oâ'"6 3£ K ^ Cd 0 Vcc = Pin 5 GND = Pin 13 oâ'"10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 10 0 â'" 2 11 J So 0 CP CP K Co Q , - K Q Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D64 54S/74S114, 54LS/74LS114 4 J
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7472 PIN DIAGRAM TTL 74107 74LS74 7473 pin diagram 7476 CI 7473 54H/74H78 54LS/74LS112 54S/74S113 54LS/74LS113 54H/74H71 54H/74H101
Abstract: GD54/74LS112 DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH SET AND RESET Features Pin C o n fig u ra tio n â'¢ Negative edge-triggering â'¢ Diode clamped inputs â'¢ Independent input/output terminals for each flip-flop. â'¢ Direct set and reset inputs â'¢ Q and Q outputs Vcc , pulse. Block Diagram (Each Flip Flop) CLOCK INPUT 4 -8 8 z 2Q CK K This device , /74LS112 Absolute Maximum Ratings â'¢ S u p p ly v o lta g e , V cc . -
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GD54/74LS112

74LS112P

Abstract: 74LS112D 112 /54S/74S112 0//oû'7 \/54LS/74LS112 b/zooL DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP , Level L = LOW Voltage Level ORDERING CODE: See Section 9 CONNECTION DIAGRAM PINOUT A cp, [7 Ki (T , vcc ÃFlCpi ï7|CD2 13] CPs ÏU k2 Tt] J2 ÏÃ"]Sd2 T]o2 LOGIC SYMBOL PKGS PIN OUT COMMERCIAL GRADE , '"9 1-0 CP 13â'"O CP 2â'" K _ Cd 0 K Q Cd 0-7 15 Vcc = Pin 16 GND = Pin 8 INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions PIN NAMES DESCRIPTION 54/74S (U.L.) HIGH/LOW 54/74LS (U.L.) HIGH
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74S112PC 74LS112PC 74S112DC 74LS112DC 54S112DM 54LS112DM 74LS112P 74LS112D 74s112p

TTL 74ls74

Abstract: 74ls74 CP 3-0 K Co Q »1 13 â'"0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J SC Q CP KCoQ 7 2 â'" D SD Q -5 â'" O 3 â'" CP 11 â'" CP Cd 0 0-6 Cd O 15 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 14 GND = Pin 7 111 F < o tu z z o , 0 1 -0 CP 5-0 CP 3 â'" Kc, 0 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 D58 54
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TTL 74ls74 7476 JK TTL 7474 ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM 54S/74S109 54LS/74LS109 54H/74H73 54LS/74LS73 54LS/74LS107 54H/74H76

8 pin dip j k flipflop ic

Abstract: 74LS112P 00b37fl7 S | T-lk-07-0 7 112 CO NN ECTIO N DIAGRAM PINOUT A 54S/74S112 54LS/74LS112 , - ORDERING CODE: See Section 9 PIN PKGS Plastic DIP (P) C eram ic DIP (D) Flatpak (F) O UT A A A . C O M M , 54S112DM, 54LS112DM 54S112FM, 54LS112FM Vcc = Pin 16 G N D = Pin 8 6B 4L INPUT LO AD IN G /FAN -O U T: See Section 3 fo r U.L. definitions PIN NAMES J1, J2, K1, «2 CP1, CP2 C d i . CD2 S01, SD2_ Q i , 02 , } GEE D | b'SDUSS 0Db37flfi 7 | T 'LO G IC DIAGRAM (one half shown) y t 0 7 o ? CP DC CH
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8 pin dip j k flipflop ic
Abstract: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION â'" The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs are enabled and data w ill be , 2â'" ORDERING CODE: See Section 9 PIN 10 1 112 LOGIC DIAGRAM (one half shown) CP , . definitions PIN NAMES J1, J2, K l, K2 CP1. CP2 C di , CD2 S d i , Sd 2 Q i , Q 2, Q i, Q 2 -
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4LS/74LS112 74S112FC 74LS112FC

d146

Abstract: RS latch < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H/74H106 4 â'" 0 â'"15 â'" Q 1-0 CP 6-0 CP 16â'" K _ CD Q 0-14 « 0 D62 54S/74S112, 54LS/74LS112 4 10 3â'" 1 2 Sd J 0 -5 1-i J S° 0 CP 13-0 CP K _ Co Q oâ'"6 3£ K ^ Cd 0 Vcc = Pin 5 GND = Pin 13 oâ'"10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 10 0 â'" 2 11 J So 0 CP CP K Co Q , - K Q Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D64 54S/74S114, 54LS/74LS114 4 J
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d146 RS latch 74LS78 7475 D latch d147 74LS114 54LS/74LS76 54LS/74LS78 93L14 54LS/74LS279 54LS/74LS196 54LS/74LS197

7472 PIN DIAGRAM

Abstract: 74574 D54 54/7470 13 Vcc = Pin 14 GND = Pin 7 T 13 Vcc = Pin 14 GND = Pin 7 19-olâ'"^ So CP KCo ~~7 Vcc = Pin 14 GND = Pin 7 111 O D 111 O z o (9 111 > H < (9 ui Z o (0 111 u z < z o 3 , J O â'" 6 CP K O 0-8 Vcc = Pin 14 GND = Pin 7 D53a 54/7472 54H/74H72 13 Vcc = Pin 14 GND = Pin 7 D53b 54H/74H102 1ÌE0 J S° o â'" 8 CP KC0 0 0-6 T 2 Vcc = Pin 14 GND = Pin 7 ÌED So J Q â'" 8 CP K O 0â'"6 Cd Vcc = Pin 14 GND = Pin 7 13-48 FAIRCHILD DIGITAL TTL TTL
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74574 TTL 7472 7473 dual JK 7472 ttl O9111 7472 ci 74H71

74ls112 pin diagram

Abstract: tpLH^tpHL V q q (Op r .)= 2 V ^ 6 V Pin and Function Compatible with 74LS112 ' ABSOLUTE MAXIMUM , â'L "L _r H H TOGGLE NO CHANGE X : LOGIC DIAGRAM NO CHANGE D o n 't c a r e
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TC74HC112P/F 74HC112P/F TC74HC112 TC74H C112P/F

74HC112 pin diagram

Abstract: 74ls112 function table (OPR) = 2 to 6V a PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 DESCRIPTION The M54/74HC112 is a high , excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal , FUNCTION Q H L H CLEAR PRESET OH H L Qn On NO CHANGE TOGGLE NO CHANGE LOGIC DIAGRAM (1/2 , Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC V qq or
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74HC112 pin diagram 74HC112 M54HC112 M74HC112 54/74LS112 M54HC112/M74HC112

74ls112 pin diagram

Abstract: M54HC112 VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 B1R (Plastic Package) F1R , . PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection , Care PIN DESCRIPTION IEC LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 13 1CK , Reset inputs 8 16 GND V CC Ground (0V) Positive Supply Voltage LOGIC DIAGRAM (1/2 Package , mA mA IO DC Output Source Sink Current Per Output Pin ± 25 mA DC VCC or Ground
STMicroelectronics
Original
M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R P027A M54/M74HC112

74HC112 pin diagram

Abstract: 74hc112 RANGE Vcc (OPR) = 2 to 6V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 DESCRIPTION The M54/74HC112 , M74HC112 C1 M74HC112 B1N M74HC112 M1 M74HC112 F1 PIN CONNECTIONS (top view) 1PR NC IQ 75 D' D , an On NO CHANGE X: DON'T CARE I i LOGIC DIAGRAM (1/2 Package) ABSOLUTE MAXIMUM RATINGS Symbol
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M54HC112F1 IC 74HC112 74HC74 54HC 74HC K50V-

IC 74HC112

Abstract: 74ls112 function table VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 B1R (Plastic Package) F1R , . PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection , Care PIN DESCRIPTION IEC LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 13 1CK , Reset inputs 8 16 GND V CC Ground (0V) Positive Supply Voltage LOGIC DIAGRAM (1/2 Package , mA mA IO DC Output Source Sink Current Per Output Pin ± 25 mA DC VCC or Ground
STMicroelectronics
Original
74LS112 JK EDGE TRIGGERED FLIP FLOP JK flip flop IC diagram Toggle flip flop IC

IC 74HC112

Abstract: H74HC112 (opr) = 2V to 6V Pin and Function compatible with 54/74LS112 TRUTH TABLE INPUTS OUTPUT preset , Chip Carrier ORDERING NUMBERS: M54HC112 F1 M74HC112 B1 M74HC112 F1 M74HC112 C1 PIN CONNECTIONS (top , H74HC112 LOGIC DIAGRAM (1/2 Package) j clock- _ oâ'" â'¢ o c> - * . E> -O-9 PR£SET _ £> .  , DC Output Source Sink Current Per Output Pin ± 25 mA ice or 'gnd DC Vcc or Ground Current ± 50 mA
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74LS112 J-K flip flop clock inputs H11L

74ls112 function table

Abstract: Range- -Vcc (opr.) =2 V ~ 6V · Pin and Function Compatible with 74LS112 · · · · · 'C C 1K 1J 1M , Handbook. 1997 08-07 - 1/6 TOSHIBA TC74HC112AP/AF/AFN SYSTEM DIAGRAM H> [>- Q
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TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2
Abstract: tPLH = tPHL â  WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 M1R C1R (Micro Package) (Chip Carrier) ORD ER COOES , voltage. M74HC112M1R M74HC112C1R PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT , TOGGLE H H H X X _r Qn Qn NO CHANGE X: Donâ'™t Care PIN DESCRIPTION PIN , (0V) 16 Vcc Positive Supply Voltage 6, 7 > > LC1 390 LOGIC DIAGRAM (1/2 Package -
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Abstract:   WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2 to 6V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 , DESCRIPTION PIN CONNECTIONS (top view) The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH , j r X: DONâ'™T CARE LOGIC DIAGRAM (1/2 Package) s > > j- o - £> + 3 - , mA >0 DC Output Source Sink Current Per Output Pin ± 25 mA !CC or 'GND Pd Tstg -
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S-10216
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