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74hc74 pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

74HC74

Abstract: 74hc74 pin diagram 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 4 - 27 August 2012 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge , voltages in excess of VCC. 2. Features and benefits Input levels: For 74HC74: CMOS level For 74HCT74 , leads (300 mil) Version SOT27-1 Type number NXP Semiconductors 74HC74; 74HCT74 Dual D-type , ; 14 terminals; body 2.5 3 0.85 mm 4. Functional diagram 1SD SD D CP FF Q 4 10 1SD 2SD 2 12 3 11
NXP Semiconductors
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74HC74N 74HCT74N 74HC74DB 74HCT74DB HCT74 74hc74 pin diagram 74HC74 application CI 74hc74 Current 74HCT74 JESD22-A114F JESD22-A115-A 74HC74D 74HCT74D
Abstract: diagram © NXP B.V. 2013. All rights reserved. 2 of 20 74HC74-Q100; 74HCT74-Q100 NXP , 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 2 â'" 6 September 2013 Product data sheet 1. General description The 74HC74-Q100; 74HCT74 , levels:  For 74HC74-Q100: CMOS level  For 74HCT74-Q100: TTL level  Symmetrical output , )  Multiple package options 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type NXP Semiconductors
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74HC74-Q100 AEC-Q100 MIL-STD-883 JESD22-A115
Abstract: 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 1 â'" 7 August 2012 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are , levels:  For 74HC74-Q100: CMOS level  For 74HCT74-Q100: TTL level  Symmetrical output , )  Multiple package options 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type , diagram 4 2 3 1SD 1D 1CP SD Q D Q 4 10 3 1SD 2SD 2 2 12 3 11 SD NXP Semiconductors
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74HC74

Abstract: 74HC74-Q100 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 1 - 7 August 2012 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual , 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC74-Q100: CMOS level For 74HCT74 , ) Multiple package options NXP Semiconductors 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with , terminals; body 2.5 3 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Type number 4. Functional diagram 1SD
NXP Semiconductors
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74HC74 application note TTL 74hc74 74HC74BQ

HC74G

Abstract: 74HC74 application , 2007 February, 2007 - Rev. 0 1 Publication Order Number: 74HC74/D 74HC74 PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 1 14 VCC RESET 1 DATA 1 2 13 RESET 2 CLOCK 1 3 , 74HC74 Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The 74HC74 is , Q2 Q2 10 PIN 14 = VCC PIN 7 = GND H L L H H* H* H L L H No Change No Change No , to GND) ­ 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA mA Iout DC
ON Semiconductor
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HC74G 74HC74DG 74HC74DR2G 74HC74D-T 74HC74DR2 LS74 SOIC-14 TSSOP-14 74HC74/D

HC74G

Abstract: 74hc74 : 74HC74/D 74HC74 PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 RESET 1 1 14 VCC DATA 1 2 , RESET Figure 5. EXPANDED LOGIC DIAGRAM http://onsemi.com 5 74HC74 PACKAGE DIMENSIONS SOICâ , 74HC74 Dual D Flipâ'Flop with Set and Reset Highâ'Performance Siliconâ'Gate CMOS The 74HC74 , X X X H L X X X Q Q SET 2 10 PIN 14 = VCC PIN 7 = GND H L L H H* H* H , + 0.5 V Iin DC Input Current, per Pin ±20 mA mA Iout DC Output Current, per
ON Semiconductor
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74HC74

Abstract: 74HC74 application note ; positive-edge trigger 74HC74; 74HCT74 PINNING PIN SYMBOL DESCRIPTION 1 1RD asynchronous , INTEGRATED CIRCUITS DATA SHEET 74HC74; 74HCT74 Dual D-type flip-flop with set and reset , 74HC74; 74HCT74 FEATURES GENERAL DESCRIPTION · Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL , total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. For 74HC74 the condition is VI
Philips Semiconductors
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74HCT74 DATASHEET 74HC74 datasheet MNA423 74HC74P 74HC74 pin configuration EIA/JESD22-A114-A EIA/JESD22-A115-A SCA75

74HC74

Abstract: 74ls74 timing setup hold GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description , characteristic of CMOS â'¢ Diode protection on all inputs Pin Configuration 1CLR [~T~ u m] vcc 1 D [~2 , Package Logic Diagram S 4 2 ID Ã" PR 1 Q 3 1 CLK CLK FF1 Q CLR ? 10 6 1 CLR 9 , diagram Function Table INPUTS OUTPUTS PR CLR CLK nD nQ nQ L H X X H L H L X X L H L L X X H H , transition 4-89 This Material Copyrighted By Its Respective Manufacturer GD54/74HC74, GD54/74HCT74
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GD74HCT74 74ls74 timing setup hold 74LS74 PINOUT 74HC GD54/74HC74 54/74LS74 GD54HCT74

74HC74

Abstract: 74hct74 GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description , immunity characteristic of CMOS â'¢ Diode protection on all inputs Pin Configuration ICLR[~T u h]vcc , Logic Diagram 5 4 2 iPB ID h PB D Q CLK F F1 Q CLR 9 IQ 3 1 CLK IQ 6 'CCS 9 10 , diagram Function Table INPUTS OUTPUTS PR CLR CLK nD nQ nQ L H X X H L H L X X L H L L X X H H , transition 3-23 4DSÃ7S7 QQ042Ã7 ISO â  GD54/74HC74, GD54/74HCT74 Absolute Maximum Ratings SYMBOL
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000M2AA GQ142C1Q 00042T1 402A757 DQ042T2

74HC74

Abstract: of 74HC74 ic M74HC74 M1 M74HC74 F1 PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC74 is a high speed CMOS DUAL D , CARE October 1988 1/5 139 M54/74HC74 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol , PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 M1 Micro Package 1 B1N Plastic Package F1 Ceramic Frit , DC Output Source Sink Current Per Output Pin DC Vcc or Ground Current Power Dissipation Storage , " '/#» MiBB8>[?[LïCW®MCS Æ 7 SGS-THOMSON M54/74HC74 DC SPECIFICATIONS TA = 25°C 54HC and
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M54HC74 of 74HC74 ic pin DIAGRAM OF IC 74HC74 54HC74 74ls74 ic chip IC 74hc74 M54/74HC74 S-7003

of 74HC74 ic

Abstract: 74HC74 PROPAGATION DELAYS tPLH = tpHL â  WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2V to 6V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 DESCRIPTION The M54/74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH , PIN CONNECTIONS (top view) 1CLR [7 1D [7 1 CK [J 1 PR 1 a 10 [s GND [T 3 [I a ia u u ICE , October 1988 1/5 139 This Material Copyrighted By Its Respective Manufacturer I M54/74HC74 I LOGIC DIAGRAM f ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vcc Supply Voltage -0.5 to 7 V V| DC
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GIJ diode 54HC
Abstract: Connection 1/5 139 I M54/74HC74 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol , tPLH = tpHL WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 , NUMBERS: M54HC74 F1 M74HC74 C1 M74HC74 B1N M74HC74 M1 M74HC74 F1 PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH PRESETANDCLEARfabricated in silicon , Pin ± 25 mA â o icc or Ignd ± 50 mW - 6 5 to 150 Storage Temperature Tstg -
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ic 74 hc 10

Abstract: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These , operation over wide temperature ranges to meet in­ dustry and military specifications. Pin , Table Logic Diagram OUTPUTS INPUTS PR CLR CLK nD nQ nQ L H L H L L X , Logic diagram H L X t Qn+1 H H = = = = = t r L H L H Qn+1 H L HIGH , CLK transition 4 -8 9 GD54/74HC74, GD54/74HCT74 Absolute Maximum Ratings PARAMETER
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ic 74 hc 10
Abstract: OPERATING VOLTAGE RANGE Vcc (OPR) = 2V to 6V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 FI , M74HC74 C1 M74HC74 M1 M74HC74 B1N M74HC74 F1 PIN CONNECTIONS (top view) DESCRIPTION Thè M54/74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH PRESETANDCLEARfabricated in silicon gate C2MOS , 1/5 139 * M54/74HC74 ® ® 7^2^237 003^005 21b â S6TH S G S-THOMSON LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value - 0.5 to 7 Unit DC Input -
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74hc74an

Abstract: CI 74hc74 . Technical Data File Number 1476 High-Speed CMOS Logic CD54/74HC74 CD54/74HCT74 T-HU'O^-DB HARRIS SEMICOND SECTOR 5~Vee « PIN 14 «NO « PIN 7 92CS-369S5BI FUNCTIONAL DIAGRAM 27E D B 4302271 DD17Slb M , pin compatible with the standard 54LS/74LS logic family. The CD54HC74 and CD54HCT74 are supplied in 14 , . 1 â'" Logic Diagram H = High Level (Steady State) L = Low Level (Steady State) X = Don't Care â , Technical Data_ T-46-07-08 CD54/74HC74 CD54/74HCT74 MAXIMUM RATINGS, Absolute-Maximum Values: DC
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CD74HC74 CD74HCT74 74hc74an 74HCT74 truth table 74hc74c CD54/74HC74 DD17S RCA-CD54/74HC74 54HCT/74HCT

74HC74

Abstract: of 74HC74 ic . Fig. 1 - Logic Diagram 109 Technical Data CD54/74HC74 CD54/74HCT74 MAXIMUM RATINGS , Technical Data File Number 1476 CD54/74HC74 CD54/74HCT74 High-Speed CMOS Logic Dual D , QMO » P!W 7 9ÎCS-36965m FUNCTIONAL DIAGRAM TheRCA-CD54/74HC74andCD 54 , level at the appropriate input. The 54HCT/74HCT logic family is functionally as well as pin compatible , - - 2Q ZQ 92CS 3 6 9 6 4 110 Technical Data CD54/74HC74 CD54/74HCT74 ST A TIC ELE C
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CS-36965 54/74HCT74 54HCT 74HCT COS4/74HC74 54/74HC

74hc74an

Abstract: Current 74HCT74 Technical Data File Number » E l 3fl7SDfll 00114Tb 7 | ~ D T-4fc-07- , 5V, CL = 15 pF, 7* = 25°C A R ^ - 0 F /F -2 > -* 0 s Y Vrf. a H H 14 «NO « PIN T 9ZCS- 3 6965R I CLOCX - >CP SET - - FUNCTIONAL DIAGRAM The RCA-CD54/74HC74andCD54/74HCT74 utilize silicongate , input. The 54HCT/74HCT logic fam ily is functionally as well as pin compatible with the standard 54LS , - 369 6 6 Fig. 1 - Logic Diagram NOTÉS: QO = the level of Q before the indicated input
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00114T 3A750A1

75HC04

Abstract: Multivibrator 74HC74 designed in a 1.4µm CMOS process. As illustrated in the functional block diagram, Figure 2, the HI5710 is , mode, controlled by the TESTMODE input pin, where the output data bits are held at known fixed logic , connected The operation of the part is depicted in the timing diagram of Figure 3. There is a 3 cycle , . Evaluation Board Block Diagram CLOCK CLK OUT 1/16 MM 2.5V REF 2.0V +2 JP1 4.0V VRT , +5VA +5VD Application Note 9511 Functional Block Diagram + S/H AMP VIN 39 x8 12
Harris Semiconductor
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AN9511 REF03 74HC541 74HC221 74HC04 75HC04 Multivibrator 74HC74 Multivibrator 74HC00 AN9102 spst push button switch HA5020 CA158A 74HC00

Multivibrator 74HC74

Abstract: 75HC04 . As illustrated in the functional block diagram, Figure 2, the HI5710 is a 2-step A/D converter , input pin, where the output data bits are held at known fixed logic levels to facilitate in-circuit , the part is depicted in the timing diagram of Figure 3. There is a 3 cycle clock delay from the analog input sampling point to the corresponding digital output data. Evaluation Board Block Diagram , +5VA +5VD Application Note 9511 Functional Block Diagram + S/H AMP VIN 39 x8 12
Intersil
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74HC74 schematic application AN9214 AN890 AN9214.2 spst push button ISO9000

Multivibrator 74HC00

Abstract: 75HC04 designed in a 1.4µm CMOS process. As illustrated in the functional block diagram, Figure 2, the HI5710 is , mode, controlled by the TESTMODE input pin, where the output data bits are held at known fixed logic , connected The operation of the part is depicted in the timing diagram of Figure 3. There is a 3 cycle , . Evaluation Board Block Diagram CLOCK CLK OUT 1/16 MM 2.5V REF 2.0V +2 JP1 4.0V VRT , +5VA +5VD Application Note 9511 Functional Block Diagram + S/H AMP VIN 39 x8 12
Harris Semiconductor
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74hc741 74HC00 harris AN8906
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