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SN74LS93J-00 Texas Instruments LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, CDIP14 visit Texas Instruments
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74LS93 P Datasheet

Part Manufacturer Description PDF Type
74LS93PC Fairchild Semiconductor Divide by Sixteen Counter Scan

74LS93 P

Catalog Datasheet MFG & Type PDF Document Tags

74LS93 P

Abstract: IC 74LS90 N 5 4 L S /7 4 L S 9 2 and SN 54U S/74LS93 are high-speed 4-bit ripple type counters partitioned , 46-06 (Plastic) SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER LOW POWER SCHOTTKY LOGIC SYM BOL LS90 · LOW PO W ER C O N SU M PTIO N . . . T Y P IC A L L Y 46 mW · HIGH C O U N T R A T E S . . . T Y P IC A L L Y 4 2 MHz · C H O IC E O F CO U N TIN G M O D ES . . . B C D . B I-Q U IN A R Y . D 1V ID E-BY-TW ELV E, B IN A R Y · IN P U T C L A M P D
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74LS93 P IC 74LS90 of IC 74LS90 pin diagram of ic 74LS93 ic 74ls92 of IC 74LS93 S/74LS93 SN54/74LS93

74LS90

Abstract: 74LS93 pin diagram SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters , PINS 4, 13 FAST AND LS TTL DATA 5-1 SN54/74LS90 · SN54/74LS92 · SN54/74LS93 LOGIC DIAGRAM , (Connection Diagram) as the Dual In-Line Package. SN54/74LS90 · SN54/74LS92 · SN54/74LS93 FUNCTIONAL , SN54/74LS90 · SN54/74LS92 · SN54/74LS93 LS90 MODE SELECTION RESET / SET INPUTS MR1 MR2 MS1 MS2 H
Motorola
Original
74LS93 pin diagram circuit diagram of 74ls92 TTL 74ls90 74LS93 logic symbol TTL 74LS93 74LS90 pin diagram
Abstract: GD54/74LS93 4-BIT BINARY COUNTER DIVIDE-BY-TWO AND DIVIDE-BY-EIGHT Description Pin Configuration This is an asynchronous 4-bit binary (hexadecimal) counter function with direct reset inputs. This , GD54/74LS93 Absolute Maximum Ratings â'¢ Supply voltage, Vcc , maintaining full fan-out capability. GD54/74LS93 Switching Characteristics, V c c = 5V, T a = 25°C MIN , CL- 1 5 p F B 70 21 *PHL 70 46 14 Qd 18 46 tp H L 16 12 Qa -
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GD54/74LS93
Abstract: (M MOTOROLA. ) SN54/74LS90 SN54/74LS92 SN54/74LS93 DECADE COUNTER; DIVIDE-BY-TWELVE , fan-out plus the C P i input of the device. d. To insure proper operation the rise (tr) and fall time (If , â'¢ SN54/74LS92 â'¢ SN54/74LS93 CONNECTION DIAGRAM DIP (TOP VIEW) LOGIC DIAGRAM LS90 cp , Package. CONNECTION DIAGRAM DIP (TOP VIEW) LOGIC DIAGRAM LS92 c p iE ¡ 3 CPo N e ll à , z C P ,® (?) MRi = d r VccE _ VJ © Qo I] 02 I] 03 NC = NO INTERNAL -
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54/74LS

74LS90

Abstract: pin diagram of ic 74ls90 /74LS92 · SN54/74LS93 FUNCTIONAL DESCRIPTION T h e LS90, LS92, and L S 9 3 a re 4 -b it rip p le typ e D , n te rs p artitio n e d into tw o s e ction s. E a ch c o u n te r has a div id e -b y -tw o s e , e c lo c k inp u ts. Each se ction can be used s e p a ra te ly o r tie d to g e th e r (Q to C P , rs h ave a 2 -in p u t g ate d M a ste r R ese t (C lear), and th e L S 9 0 also h as a 2 -in p u t g ate d M a ste r S e t (P re se t 9). · Low P o w e r C o n su m p tio n . . . T y p ica lly 4 5 m W ·
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pin diagram of ic 74ls90 IC 74LS93 IC - 74LS93

pin diagram of ic 74ls90

Abstract: 74LS93 P Case 646-05 (Plastic) SN54LS/74LS90 SN54LS/74LS92 SN54LS/74LS93 D ECAD E COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER LOW PO W ER S C H O TTK Y L O G IC S Y M B O L LS90 · LO W P O W E R C O N S U M P T IO N . . . T Y P IC A L L Y 4 5 m W · H IG H C O U N T R A T E S . . . T Y P IC A L L Y , - T W E L V E , B IN A R Y · IN P U T C L A M P D IO D E S LIM IT H IG H S P E E D T E R M IN A T IO , =p in 5 G N D = Pin 10 NC = Pins 2, 3, 4 , 13 LS93 Notes: a. 1 TTL Unit Load (U .L) = 4 0 jt/A H
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74LS93A kcd5 motorola 74ls90 of 74ls90 IC decade counter IC 74LS90 internal diagram LS93J SN54LS/74LS93

74LS93A

Abstract: pin diagram of ic 74ls90 54LS/74LS93 LO G IC D IA G R A M LS90 MS C O N N EC TIO N D IA G R A M D IP (TO P V IE W , (Ä ) M O TO RO LA D E S C R I P T I O N - T h e S N 5 4 L S / 7 4 L S 9 0 , S N 5 4 L S / 7 4 L S , - Case 646-05 (Pfastic) SN54LS/74LS90 SN54LS/74LS92 SN54LS/74LS93 D EC A D E CO U N TER; DIVID , 9 0 · LO W P O W E R C O N S U M P T IO N . . . T Y P IC A L L Y 4 5 m W · H IG H C O U N T R A T E S . . . T Y P IC A L L Y 4 2 M H z · C H O IC E O F C O U N T IN G M O D E S . . . B C D . B I Q U
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ic 74LS90 pin diagram

7493 4 bit binary counter

Abstract: LM 7493 Counters 7493, LS93 Product Specification 4-Bit Binary Ripple Counter TYPE 7493 74LS93 , 1LSul 6LSul 4LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) c p iH j3 c P o 14 o CP0 & & r ctr M R i[ T m r j n c CT [T m ] 7 ] NC Qo , Typ2 3.4 0 .2 74LS93 UNIT Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max V V V V V , 5.5V 7.0V 5.5V 2.4V All inputs '93 MR inputs CP0, C P i inputs 1 .0 0 .1 0 .2 mA mA mA MA
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7493 4 bit binary counter LM 7493 7493 binary counter diagram 7493 logic diagram 7493 flip-flop counter 4 bit counter 7493 N7493N N74LS93N N74LS93D 1N916 1N3064

pin diagram of ic 7493

Abstract: ic 7493 pin diagram P rod ucts DESCRIPTION The '93 is a 4-bit, ripple-type Binary Counter. The device consists o f , counting modes. In a 4-bit ripple counter the output Q 0 must be connected externally to input C P ^ TYPE 7493 74LS93 TYPICAL f MAX 40MHz 42MHz TYPICAL SUPPLY CURRENT (TOTAL) 28mA 9mA ORDERING CODE , 0 5 '3 0 S 1 4 -C C P 0 1- C CP, MR Q0 Q1 °2 °3 VccE nc[T nc[T WI I I I 2 3 12 9 8 11 LSQ S790S Vcc = P in 5 GND - Pin 10 December 4, 1985 5 -1 4 9 853-0574 81501
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pin diagram of ic 7493 ic 7493 pin diagram ic 7493 truth table circuit diagram of ic 7493 pin configuration of 7493 logic diagram of ic 7493

ic 7493 truth table

Abstract: logic diagram of ic 7493 - Counters 7493, LS93 4-Bit Binary Ripple Counter Product Specification TYPE 7493 74LS93 TYPICAL , /IEC) c p iU m cpo HR, [ T m r 2 GT NCU V ccOE n c |T n c (T 3] NC m °3 ÎÔ]OND H o , input C P i. Simultaneous frequency divisions of 2, 4 and 8 are available at the Q-|, Q 2 and Qa outputs , noted.) 7493 Typ2 3.4 0 .2 74LS93 UNIT Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max V , grounded. 5. The maximum limit for the 54LS93 only is 80 /jA for £ P 0 and CP-i inputs. AC ELECTRICAL
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INTERNAL DIAGRAM OF IC 7493 IC 7493 4bit Binary Counter IC 7493 configuration ic 7493 7493 asynchronous counter definition of 7493 ic

74LS160

Abstract: Synchronous 74163 Synchronous Synchronous Synchronous Up/D own U p/D own Up/Down U p/D own Up/Down Up/Down U p/D own U p/D own Up/Down U p/D own 93L16 93S16 54/74160 54LS/74LS160 54/74161 54LS/74LS161 54/74162 54LS/74LS162 54 , Pin 10 NC = 2, 3, 4, 13 Vcc = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 54/7493A, 54LS/74LS93 , - CEP 1 0 - CET 2 - CP 9 3 4 5 6 11 15 1 10 9 PE Po P i P2
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93S05 74LS160 Synchronous 74163 74192 74LS190 pins 74LS193 74LS191 pins 54LS/74LS163 54LS/74LS168 54LS/74LS169 54LS/74LS192 54LS/74LS193 74LS190

74LS93P

Abstract: 74LS93PC 93 CONNECTION DIAGRAM PINOUT A ^ 6,V^4/7493A [/54LS/74LS93 DIVIDE-BY-SIXTEEN COUNTER DESCRIPTION â'" The â'™93 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby-eight. HIGH signals on the Master Reset (MR) inputs , C Vcc = +5.0 V ±10%, T a = -55° C to + 125°C PKG TYPE Plastic DIP (P) 7493APC , ) Asynchronous Master Reset Inputs (Active HIGH) + 2 Section Output* p PIN NAMES -^8 Section Outputs
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7493ADC 74LS93P 74LS93DC 5493ADM 54LS93DM 7493AFC

TTL 74293

Abstract: 7490A FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL 14â'"0 Ko 15â'"O Ki 16â'"O K2 17â'"O k3 D114 9344 1» 18 4 5 23 22 21 20 Mi Mo Yi Yo Xo Xi X2 X3 So S2 S2 S3 S4 Ss TTTTTT 11 10 9 8 7 6 Vcc = Pin 24 GND = Pin 12 NC = Pin 1, 2, 3, 13 D115 93S43 7 8 5 4 3 1 19 18 17 16 X â'"1 *o X1 X2 X3 X4 ko ki k2 k3 23- Y-1 22- YO 21- Y1 Cn , 2x8 â'" 40 46 160 D124 3I,6A,9A 8 Asynchronous 54LS/74LS93 2x8 _ ~L 50 46 45 D124 3I,6A,9A 9
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93S62 93L10 TTL 74293 7490A 74290 7493A 74196 TTL 93H87/74H87 54LS/74LS290 54/7490A 54LS/74LS90 54LS/74LS93

TTL 74LS93

Abstract: LC74HC93  A/O.^2 3 \ 5 4077 â Ff C MOS IC LC74HC93â'" 4-Bit Binary Counter â'¢ C MOS îRiÃCOr;^ JE^»f*Å'iBia(2^6V), X £ tt^ jfrïp T ^ * . â'¢ LS -TTL ( 74LS93) i I*)â'" tf v EK » W -«Mfef 4 - V ^-hra-t^O 0 LS -TTL / it* Vqc ma* / # Vin max r;/" VouT -".-vV 'V?- : iout i ^ / ioc/^am// / â  Ik Pd mf/'* Sèj^ê Tst^/ Tgé^f t= lOsec // unit V Vcc+O.5 V VsS-0^5â'"Vcc+0.5 V ±25 mA , ¿ti^fcÅ' // VouT fcjfÉ/SWfi/t ;P:Tç>pg o~vcc VCC -40â'"H 85 0^500 unit V V V *C ne tf vK®^
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T370-05 DIP14 4077Y0

IC AND GATE 7408 specification sheet

Abstract: 74LS96 Sheet Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E , 0 0 Allow s M A X 5000 E P L D designs to be created with workstation C A E tools and transferred to M A X + P L U S for com pilation; com piled designs can b e retu rned to the w o rk s ta tio n for d , X + P L U S . Altera-provided Library M ap ping Files convert basic gate and many co m m o n T T L functions from M ento r Graph ics, Valid Logic, and V iew logic C A E tools to e qu iv alent M A X + P L U S
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IC AND GATE 7408 specification sheet 74LS96 74LS183 SN 74168 7486 XOR GATE IC 74LS192

74LS93A

Abstract: 7493a binary counter 93 /54/7493A 54LS/74LS93 à/òs , Plastic DIP (P) A 7493APC, 74LS93PC 9A Ceramic DIP (D) A 7493ADC, 74LS93DC 5493ADM, 54LS93DM 6A Flatpak
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7493a binary counter 74LS93 pinout 7493a counter 74LS93 pin configuration CI 7493 7493A count 74LS93FC 5493AFM 54LS93FM

74LS80

Abstract: 74LS198 4flE ]> 77MLjbc iO 0001L3M 4bO « P C H TEK-044-9004 °J RICOH CORP/ ELECTRONIC , . I/O cell delay t im e . 0.8ns(Typ.) 3.0 ns (Typ.) * T y p . , n m 4-65 m G a te A rray 5 G V 4Ô ^ ® 7 7 4 4 ^ 0 00Glb3S CORP/ 3T7 P , ns ns MA E D 77MMbqP OOlbBb 233 RICOH « P C H CORP/ G a te A rray 5 G V , D G 0 4-67 Gate Array 5GV ^AE ]> 77MMbc iQ 0 D 01b 3 7 17T P C H RICOH CORP
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RSC-15 M4017C M4028C 74LS179 74LS198 74LS80 74LS150 74LS94 OAI32 NOR03 NAND08 D410L AOI22 AOI24

FZH115B

Abstract: fzh261 Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P Hex buffer 30V O/P Quad 2 , 7492 74LS83 74LS85 74LS86 74LS90 7495 74LS95 74HC85 74HC86 74LS92 74LS93 74HC93 , 0.67 0.49 0.44 2.59 2.32 74LS75 74LS76 74LS83 74LS85 74LS86 74LS90 74LS92 74LS93
Electro Value
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FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 16-DIL

M54451P

Abstract: M54820P - D4 1- s 01 * ro 0 "0 D3 D IG IT O U T P U TS B -D z àgi- Di(LSD) 19J- c Ü |-*b , . anode LED display, completes the S] S2 S 3 S t S$ S6 S7 Sß S E L E C T IO N IN P U T S PRESET , measurement fre quency o f up to 2.5MHz. The in p u t signal however, is a T T L level rectangular wave, the , . Therefore, a highly stable Table 2 Preset values P reset s e le c tio n in p u ts ( n o te 2} P ie s , .2 5 H z source such as a quartz oscillator must be used. For example, when the in p u t frequency
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M54820P M54280P M54451P M54820 M54451 M5482 m53290 19J-- 54820P 135MH

M54451P

Abstract: M53290P ^24^27 oaisam MITSUBISHI T4b â  M I T 3 M IT SU BISH I b i p o l a r d i g i t a l , P R E S E T S E L E C T IO N 2â'"412 A MITSUBISHI ELECTRIC IN P U T S b3E â  b S M T Û E ? P 0 1 S 2h S Tfl2 â  M I T 3 MITSUBISHI M IT SU BISH I BIPO LAR DIGITAL ICs , N OF O P ER A T IO N Table 2 Preset values The following is an operational description of the , z 1kHz- Vi 6 P R E C A U T IO N S FOR USE 1. The dynamic display system may generate noise
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M53290P 2SC1210 7 segment common anode M54812L 625MH 40MH/ 20MH/ 135MH/
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