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74LS76 logic diagram

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logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 FLIP-FLOP LOGIC DIAGRAM MODE SELECT- TRUTH TABLE OPERATING MODE ®D Asynchronous Set Asynchronous , 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K , . The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup , levels as shown in the Truth Table. LOGIC SYMBOL 2 7 4- J SD Q -15 9 , . d. The 74LS76 is edge triggered. Data m ust be stable one setup tim e p rio r to the negative edge o
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logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC 54LS/74LS76 74H76 N7476N N74H76N N74LS76N N74H76F

pin diagram of 7476

Abstract: 7476 J-K Flip-Flop Flip-Flops 7476, LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products , HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 E ®D 1OE *01 GE
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pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 PIN DIAGRAM 7476 1N916 1N3064

ci 7476

Abstract: 7476 PIN DIAGRAM Signetics Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K , and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , ¶]qj »02 E T]j2 LOGIC SYMBOL LS76 «' «o, » r â'"IS »â'" Ja *®> Cj Roj Qj|O-10 K. no, o, ~T 76 -is «- o* >-1« 12â'"I Ki Roj Qa|0-1C LOGIC SYMBOL (IEE/IEC) 76 LS76 ij CI n 15
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ci 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 PIN DIAGRAM input and output 7476 ttl LS 7476

7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table 54/7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK , signotics This Material Copyrighted By Its Respective Manufacturer LOGIC DIAGRAM MODE SELECTâ'"TRUTH , . The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup , the output states are unpredictabfe if Sd and Rd go HIGH simultaneously. d. The 74LS76 is edge
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S5476F 74ls76 jk flip-flop logic symbol and truth table 7476 pin configuration Jk 74ls76 pin out 74Ls76 truth table Jk 7476 N7476F N74LS76F S54H76F S54LS76F S5476W

pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 81501 Signetics Logic Products Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products , HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , . PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP, U 33*1 D o , 1J
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TTL 7476 7476 signetics TTL 7476 logic diagram 7476 signetics

PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 , LS76 LOGIC DIAGRAM S 0 - y xC " Q K - -J CP LD0280GS FUNCTION TABLE INPUTS , Sjgnetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products , HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , l|H and -0 .4 m A lIL. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP
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J-K Flip-Flop 7476 TTL 74ls76 74LS76 logic diagram Flip-Flop 7476 Diagram of 7476 Pin Configuration of 7476

jk flip flop 7476

Abstract: 7476 PIN DIAGRAM Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , Signetics Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K , and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , ' 3302 "02 u T]j2 LOGIC SYMBOL 'LS76 â'" 15 »â'" J, «' "to, O'P-" ~T 3 7$ Kl Ro, % ~7 LOGIC
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74LS76 ttl LS76 flip-flop 74ls76

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram Dissipation mW (Typ) Logic/Connection Diagram X X X X X X X cn 05 O ro ro o , Width-ns (Typ) Enable/Clock to Q Delay-ns (Typ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram 9314 D EV IC E NO . 4xD 4xD 4xD 4x(RS) 4xD 1 4xD i- 4xD 4xD , ro - Item Dual JK 54LS/74LS78 c_ Dual JK Dual JK Dual JK Dual JK 54LS/74LS76 , C D Packag (s) C O C D FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE
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logic ic 74LS76 pin diagram 74LS107 ic 74109 74109 dual JK 74LS109 IC 74196 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279

CI 7474

Abstract: CI 7473 h-ul N o Clock to Output Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s , to G Delay-ns (Typ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , /74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8
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CI 7474 CI 7473 7474 D latch CI 74LS76 CI 74107 fairchild 9024 54S/74S109 54LS/74LS109 54H/74H74 54S/74S74 54LS/74LS74 54H/74H73

d146

Abstract: RS latch ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Dual JK 54S/74S114 J,K X X X 125 5.0 , (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 9 4-Bit RS Latch 9314 4x(RiSi) L , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 ¿ 10 i 4â'" O â'"2 11^ 0 9â'" CP Lo CP 1 â'" 0 0-3 8_ K _ Co Q _TL Ul O O ul (9 Z 5 (9 > H , 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7
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d146 RS latch 74LS78 7475 D latch d147 74LS114 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113 54LS/74LS113

7476 truth table

Abstract: 7476 logic diagram NATIONA L SEMICOND -CLOGIO 02E D | b S O U S E 76 GGbBVSO t , | 3 T-YL- 0 7 -0 7 CONNECTION DIAGRAM PINOUT A 54/7476 54H/74H76 54LS/74LS76 DUAL JK FLIP-FLOP (With Separate Sets, Clears , both Q and Q HIGH LOGIC SYMBOL The 'LS76 is a dual JK, negative edge-triggered flip-flop also , /74LS (U.L.) HIGH/LOW 0.5/0.25 2.0/0.5 1.5/0.5 1.5/0.5 10/5.0 (2.5) LÖGIC DIAGRAMS (one half shown , SEHICOND {LOGIC} OSE D | b S O U S E 0Db3?E5 0 | 76 SYMBOL PARAMETER 54/74 Min Icc Power Supply
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74LS76P 7476PC 54/74H 54/74LS CLS76

CI 74LS90

Abstract: ci 74193 Rate MHz (Typ) Clock to Q Output Delay-ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram , Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Dual JK 54S/74S114 J,K , ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 9 4-Bit RS , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , 5 Dual JK 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20
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74LS92 CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 S4/74293 54LS/74LS293 S4/7493A 54LS/74LS93 93L10

TTL 74ls74

Abstract: 74ls74 ) Clock to Output Delay-ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram «T «T o> IS O IS a , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K â'ž 0 Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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TTL 74ls74 74ls74 7476 JK TTL 7474 ttl 7474 14 PIN 7474 PIN DIAGRAM 54LS/74LS73 54H/74H103 74H71 54H/74H101 54H/74H72 54H/74H102

ci 7475

Abstract: D147 Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Dual JK 54S/74S114 J,K , ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 9 4-Bit RS , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D145 9370, 9374 DIGITAL -TTL 0146 9314, 93L14 D147 54/74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , 5 Dual JK 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X 60 12 20
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ci 7475 74L576 TTL 7475 fairchild 9314 pin diagram 7475 74279 93L08 54S/74S175 54LS/74LS175 54S/74S174 54LS/74LS174 93L38

7475 D latch

Abstract: D146 to Output Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Dual JK , Delay-ns (Typ) Data to Q Delay ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 9 4 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q , D60 4L,6B,9B 5 Dual JK 54LS/74LS109 J,K S X X 50 15 20 D60 4L,6B,9B 6 Dual JK 54LS/74LS76 J,K "L X X
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7475 data latch CI 74109 Fairchild 902 1L20 TTL 74109 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256

74LS76P

Abstract: 74LS76D 76 CO NNECTIO N DIAGRAM PINOUT A /54/7476 0 / / o / c ^ ^S4H/74H76 Gf / ci 7 ^ 54LS/74LS76£ v / 6 / 6 DUAL JK FLIP-FLOP (With Separate Sets, Clears and Clocks) DESCRIPTION - The '76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip-flop. Inputs to the master section are controlled by the clo ck pulse. The clock pulse , both Q and Q HIGH LOGIC SYMBOL The 'LS76 is a dual JK, negative edge-triggered flip -flo p also
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74LS76D IC 7476 pinout 74LS76 pinout IC 74LS76 74LS76 IC logic diagram of ic 7476

74HC76

Abstract: DIODE A7N 6V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS76 DESCRIPTION The M54/74HC76 is a high speed CMOS , of LSTTL combined with true CMOS low power consumption. Depending on with the logic level at the J , PRESET are independent of the clock and are accomplished by a logic low on the corresponding input. All , October 1988 1/5 149 This Material Copyrighted By Its Respective Manufacturer M54/74HC76 LOGIC DIAGRAM (1/2 Package) >â  D> * >':D- rC> Jfît>ÃOî J O E> r'OO ° kf r £H>a * ABSOLUTE
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M54HC76 M74HC76 74HC76 DIODE A7N M74HC76B1N 54HC 74HC 54/74LS76

74Ls76 truth table

Abstract: TC74HC76AP R -.£>- L - £ > > - j - £>>-1_s 0 < t > -K H < F Logic Diagram , with the logic level applied to the J and K inputs, the outputs change state on the negative going tran , logic level on the corresponding input. All inputs are equipped with protection circuits against static , Compatible with 74LS76 2P R 20 3 to 2Q 3 l1 2C Ü R » [ 3. ( T O P V IE W ) 2J Pin Assignm , X X Q L H H 0 H Clear Preset No Change L H L H X ûn L H. H IEC Logic
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TC74HC76AP TC74HC76AP/AF TC74HCT76A TC74HC/HCT

74ls76 jk flip-flop logic symbol and truth table

Abstract: 7476PC 76 ^54/7476 O/Zô/b, ^54H/74H76 l/54LS/74LS76 Gf/otù, DUAL JK FLIP-FLOP (With Separate Sets, Clears and Clocks) DESCRIPTION â'"The '76 and 'H76 are dual JK master/slave flip-flops with separate Direct Set, Direct Clear and Clock Pulse inputs for each flip-flop. In puts to the master section are , Table on the HIGH-to-LOW clock transitions. ORDERING CODE: See Section 9 CONNECTION DIAGRAM PIN OUT A , 5476FM, 54H76FM 54LS76FM 4L LOGIC SYMBOL 4 â'" j 80 q â'"ris îh j s° q â'"11 1â'"0 cp 6 â'"o cp
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74LS76PC 74LS76 dual flip-flop CD 76 13 CP 74LS76DC 7476 master slave 5476DM

74LS76 IC

Abstract: TC74HC76AP accordance with the logic level applied to the J and K inputs,the outputs change state on the negative going , logic level on the corresponding input. All inputs are equipped with protection circuits against static , Vcc (opr) = 2V ~6V · Pin and Function Compatible with 74LS76 . TRUTH TABLE 2CK 2 PR 2C LR » , ) SYMBOL TEST CONDITION _ _ TC74HC76AP/AF-3 229 SYSTEM DIAGRAM (1/2 package) TC74HC76AP
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TC74HC76A AF4 equivalent TC74HC76AP/AF-4
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