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Part Manufacturer Description Datasheet BUY
SN74LS73ADE4 Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70 visit Texas Instruments
SN74LS73ADR Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70 visit Texas Instruments Buy
SN74LS73ADG4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SO-14 visit Texas Instruments
SN74LS73AD Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70 visit Texas Instruments
SN74LS73ADRG4 Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70 visit Texas Instruments
SN74LS73ANE4 Texas Instruments Dual J-K Flip-Flops with Clear 14-PDIP 0 to 70 visit Texas Instruments

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Part : SN74LS73AD Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : $0.9749 Price Each : $1.3109
Part : SN74LS73AD Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : €0.7937 Price Each : €1.1045
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Part : SN74LS73AN Supplier : Texas Instruments Manufacturer : Avnet Stock : 17 Best Price : $0.8641 Price Each : $1.7246
Part : SN74LS73AN Supplier : Texas Instruments Manufacturer : Avnet Stock : 25 Best Price : €0.7369 Price Each : €1.0254
Part : SN74LS73ANE4 Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : $0.8156 Price Each : $0.9434
Part : SN74LS73ADR Supplier : Texas Instruments Manufacturer : Texas Instruments Stock : 5,393 Best Price : $1.75 Price Each : $1.75
Part : SN74LS73AN Supplier : Texas Instruments Manufacturer : Texas Instruments Stock : 2,580 Best Price : $1.90 Price Each : $1.90
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Part : SN74LS73AD Supplier : Rochester Electronics LLC Manufacturer : Rochester Electronics Stock : - Best Price : - Price Each : -
Part : SN74LS73AD Supplier : Texas Instruments Manufacturer : Rochester Electronics Stock : 15,611 Best Price : $1.03 Price Each : $1.27
Part : SN74LS73ANE4 Supplier : Texas Instruments Manufacturer : RS Components Stock : 50 Best Price : £0.7330 Price Each : £0.9770
Part : SN74LS73ANE4 Supplier : Texas Instruments Manufacturer : RS Components Stock : 110 Best Price : £1.34 Price Each : £1.34
Part : SN74LS73ANE4 Supplier : Texas Instruments Manufacturer : RS Components Stock : 153 Best Price : £1.34 Price Each : £1.34
Part : SN74LS73AD Supplier : Texas Instruments Manufacturer : TME Electronic Components Stock : 98 Best Price : $1.4049 Price Each : $2.3474
Part : SN74LS73AN Supplier : Texas Instruments Manufacturer : TME Electronic Components Stock : 140 Best Price : $1.20 Price Each : $1.93
Part : 74LS73N Supplier : Signetics Manufacturer : Chip One Exchange Stock : 50 Best Price : - Price Each : -
Part : DM74LS73AN Supplier : Fairchild Semiconductor Manufacturer : Chip One Exchange Stock : 552 Best Price : - Price Each : -
Part : SN74LS73AN Supplier : Motorola Manufacturer : Chip One Exchange Stock : 14 Best Price : - Price Each : -
Part : SN74LS73ADR Supplier : Texas Instruments Manufacturer : Chip1Stop Stock : 2,020 Best Price : $0.8567 Price Each : $1.4307
Part : SN74LS73AN Supplier : Texas Instruments Manufacturer : element14 Asia-Pacific Stock : 529 Best Price : $1.01 Price Each : $2.3920
Part : SN74LS73AN Supplier : Texas Instruments Manufacturer : Farnell element14 Stock : 854 Best Price : £0.7360 Price Each : £1.70
Part : NTE74LS73 Supplier : NTE Electronics Manufacturer : Master Electronics Stock : 40 Best Price : $1.73 Price Each : $2.60
Part : 74LS73N Supplier : Signetics Manufacturer : New Advantage Stock : 13 Best Price : - Price Each : -
Part : SW74LS73AD Supplier : Motorola Manufacturer : New Advantage Stock : 504 Best Price : - Price Each : -
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74LS73 Datasheet

Part Manufacturer Description PDF Type
74LS73 Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Original
74LS73 Hitachi Semiconductor Dual J-K Flip-Flops(with Clear) Original
74LS73 Motorola DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP Original
74LS73 Texas Instruments DUAL J-K FLIP-FLOPS WITH CLEAR Original
74LS73 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan
74LS73 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan
74LS73 Signetics Dual J-K Flip-Flop Scan
74LS73 Signetics Dual J-K Flip-Flop Scan
74LS73 Signetics Integrated Circuits Catalogue 1978/79 Scan
74LS73A Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Original
74LS73A Hitachi Semiconductor Dual J-K Flip-Flops(with Clear) Original
74LS73A Texas Instruments DUAL J-K FLIP-FLOPS WITH CLEAR Original
74LS73DC Fairchild Semiconductor Dual JK Flip-Flop Scan
74LS73FC Fairchild Semiconductor Dual JK Flip-Flop Scan
74LS73PC Fairchild Semiconductor Dual JK Flip-Flop Scan

74LS73

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of 7473

Abstract: pin diagram of ttl 7473 the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop. The , CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5 , Clock is HIGH for conventional operation. 2. The 74LS73 is edge triggered. Data must be stable one , 1.0 40 80 74LS73 Min 2.7 80 -1.6 -3.2 -3.2 10 -57 40 Typ2 3.4 0.35 0.25 -20 Max 0.5
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N7473N N74LS73N pin diagram of 7473 pin diagram of ttl 7473 7473 JK flip flop 7473 pin diagram 7473 7473 ttl CD05640S 1N916 1N3064

pin diagram of 7473

Abstract: 74LS73 while the C lock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop , and HIGH. asynchronous LOW, it over inputs, forcing the Q output TYPE 7473 74LS73 TYPICAL f max 20MHz , Clock is HIGH for conventional operation. 2. The 74LS73 is edge triggered. Data must be stable one , recommended operating free-air temperature range unless otherwise noted.) 7473 PARAMETER VCc = 74LS73
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OCR Scan
N74LS73 ttl 7473 74LS73 TTL p 7473 n ok2t Flip-Flops 7473
Abstract: while the C lock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered , f MAX TYPICAL SUPPLY CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA , stable while the Clock is HIGH tor conventional operation. The 74LS73 is edge triggered. Data must be , operating free-air temperature range unless otherwise noted.) 74LS73 7473 UNIT T e a l (JUNUIIIUNS -
OCR Scan

7473 pin diagram

Abstract: 74LS73 the Q output H IG H . TYPE 7473 74LS73 TYPICAL fMAX 20MHz 45MHz TYPICAL SUPPLY CURRENT (TOTAL , operation. 2. The 74LS73 is edge triggered. Data must be stable one set-up time prior to the negative edge , v oe = MIN, V|H - MIN, V|L " MAX, Iq h 74LS73 UNIT Max Min 2.7 0.4 Typ2 3.4 Typ2 3.4
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OCR Scan
TTL 74ls73 7473 dual JK

74LS73

Abstract: pin diagram of 7473 54/7473 54H/74H73 54LS/74LS73 LOGIC SYMBOL DESCRIPTION The "73" is a dual Flip-Flop with individual JK, Clock and direct Reset inputs. The 7473 and 74H73 are positive pulse triggered 'flipflops. JK information is loaded into the master while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW , conventional operation. The 74LS73 is a negative edge triggered flip-flop. The J and K inputs must be stable , conventional operation. d. The 74LS73 is edge triggered. Data must be stable one setup time prior to the
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OCR Scan
N74H73N N7473F N74H73F N74LS73F S5473F 74LS73 dual JK 54LS/74LS73

IC 7473

Abstract: pin diagram for IC 7473 the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop. The J , . asynchronous LOW, it over inputs, forcing the (5 output TYPE 7473 74LS73 TYPICAL f , AX 20MHz 45MHz , c k is HIGH fo r conventional operation. The 74LS73 is edge triggered. Data m ust be stable one , recommended operating free-air temperature range unless otherwise noted.) 7473 74LS73 UNIT Min Typ2 3.4 0.2
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OCR Scan
IC 7473 pin diagram for IC 7473 circuit diagram for IC 7473 pin DIAGRAM OF IC 7473 IC 74LS73 ic 7473 pin diagram

ic 7473 jk flipflop

Abstract: IC 7473 while the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop , TYPICAL SUPPLY CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA TYPE ORDERING , Clock is HIGH for conventional operation. The 74LS73 is edge triggered. Data must be stable one set-up , temperature range unless otherwise noted.) 74LS73 7473 PARAMETER UNIT T b S I ( J U N U I 1IU N S
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OCR Scan
ic 7473 jk flipflop

7473 pin diagram

Abstract: TTL 7473 the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop. The , CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V +5% , Clock is HIGH for conventional operation. 2. The 74LS73 is edge triggered. Data must be stable one , .) PARAMETER TEST CONDITIONS1 7473 74LS73 UNIT Min Typ2 Max Min Typ2 Max Voh HIGH-level output
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OCR Scan
Flip-Flop 7473 7473 equivalent 7473 signetics TTL 74LS LS73 CD0S640S

74LS183

Abstract: 74LS275 CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151
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OCR Scan
74LS152 74LS183 74LS248 74LS258 74LS275 74LS356 74ls series 74LS396 7447 74LS153 74LS155 74LS157 74LS158 74LS160A

74ls73

Abstract: 74LS73 dual JK -68-7473 1J 1à IQ ONO 2K 2Q 2d 07X» x -T®! (7473) 7 D ,
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OCR Scan
74 HCL 4 7473 HCT 74ls731 HC 165

TTL 74ls74

Abstract: 7474 14 PIN o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J
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OCR Scan
TTL 74ls74 7474 14 PIN 7476 ttl ttl 74ls109 TTL 74ls76 7474 16 PIN 54S/74S109 54LS/74LS109 54H/74H74 54S/74S74 54LS/74LS74 54H/74H103

74LS73

Abstract: INPUTS ä - ! - O (Each Flip-Flop) 54/74LS73 INPUTS CLEAR CLOCK J K OUTPUTS a a a 0
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OCR Scan
54/74H 54/74LS73 54/74LS

pin DIAGRAM OF IC 74HC73

Abstract: IC 74LS73 SGS -THOMSON M54HC73 _M74HC73 DUAL J-K FLIP FLOP WITH CLEAR â  HIGH SPEED 'MAX = 60 MHz (TYP.) at VCC= 5V â  LOW POWER DISSIPATION ICC = 2 nA (MAX.) at TA = 25°C â  HIGH NOISE IMMUNITY Vnih = Vnil = 28"/o VCC (MIN.) â  OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS â  SYMMETRICAL OUTPUT IMPEDANCE |OH| = |OL = 4 mA (MIN.) â  BALANCED PROPAGATION DELAYS tPLH = tPHL â  WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2V to 6V â  PIN AND FUNCTION COMPATIBLE WITH 54/74LS73 DESCRIPTION The M54/74HC73
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pin DIAGRAM OF IC 74HC73 74hc73 ic 74LS73 CMOS pin diagram for IC 74hc73 diode yz 040 54HC

pin DIAGRAM OF IC 74HC73

Abstract: IC 74LS73 OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS73 C1R (Chip
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OCR Scan
Toggle flip flop IC 73F1R 73B1R M74HC73M 74HC73C1R M54/M

CI 7474

Abstract: CI 7473 o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J
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OCR Scan
CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 54H/74H76 54LS/74LS76 54S/74S114 54LS/74LS 54LS/74LS78 93L14

TTL 74ls74

Abstract: 74ls74 o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J
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OCR Scan
7476 JK TTL 7474 ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 74H71 54H/74H101 54H/74H72 54H/74H102 54S/74S113 54LS/74LS113

pin diagram for IC 7473

Abstract: 74LS73D 7473PC, 74H73PC 74LS73PC 7473DC, 74H73DC 74LS73DC 7473FC, 74H73FC 74LS73FC 5473DM, 54H73DM 54LS73DM , ' NATIONAL SENICOND {LOGIO DEE D | b S D l l S E OOfc.3712 7 | 73 54/7473 54H/74H73 54LS/74LS73 DUAL JK FLIP-FLOP (W ith S ep arate Clears and Clocks) D ESC R IP TIO N - The '73 and 'H73 dual J K master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling
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OCR Scan
74LS73D fan out 74ls73 CLS73

7473 JK flip flop

Abstract: IC 74LS73 ) OUT COMMERCIAL GRADE V cc = +5.0 V ±5%, Ta = 0°C to +70° C 7473PC, 74H73PC 74LS73PC 7473DC, 74H73DC 74LS73DC 7473FC, 74H73FC 74LS73FC 5473DM, 54H73DM 54LS73DM 5473FM, 54H73FM 54LS73FM MILITARY GRADE Vcc = , 73 CO NNECTIO N DIAGRAM PINOUT A 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP (With Separate Clears and Clocks) D E S C R IP TIO N - The '73 and 'H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled
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OCR Scan
JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 d flip flop JK flip flop IC diagram 74LS73 JK master slave jk flip flop I/54LS/74LS73

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram 54/7473, 54H/74H73, 54LS/74LS73 *54/74107, ` 54LS/74LS107 14 - J 1 - 0 CP 3- K Q -1 2 2- J 5 -0 CP
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OCR Scan
logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74109 dual JK IC 74196 7476 Connection diagram 54LS/74LS77 54LS/74LS75 54LS/74LS197 54LS/74LS196 54LS/74LS279

TC74HC73A

Abstract: with 74LS73 (U) ( !) (3) (2 ) (7) (5) (10) (6) ^ ^ «> 2Q ^ (9) 2 0 1 CK CLR 1K Vcc 2 CK CLR 2J 1C 2
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OCR Scan
TC74HC73A TC74HC73AP/AF TC74HC/HCT

FZH115B

Abstract: fzh261 74HC42 74LS47 74LS51 74LS53 74LS54 74HC51 7472 7473 74LS73 74HC73 7474 7475 , 74LS670 74LS73 74LS74 1+ £0.75 £1.19 £0.60 £1.19 £0.73 £1.37 £0.44 £0.89 £0.54 £0.58 £0.77
Electro Value
Original
FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 74INTEGRATED 16-DIL

4027B

Abstract: 4013B 73 CO NNECTIO N DIAGRAM PINOUT A 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP (With Separate Clears and Clocks) D E S C R IP TIO N - The '73 and 'H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled by the clock pulse. The clo ck pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of op eration is as follow s: 1) isolate slave from
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OCR Scan
HCT74 HC112 HC113 HC174 HCT574 LS107 4027B 4013B hc374 HC-377 flip-flop HC76 M54/74 HC107 HC109
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