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Part Manufacturer Description Datasheet BUY
SN74LS374DWG4 Texas Instruments Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SOIC 0 to 70 visit Texas Instruments
SN74LS374FN Texas Instruments LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC20 visit Texas Instruments
SN74LS374DWRG4 Texas Instruments Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SOIC 0 to 70 visit Texas Instruments
SN74LS374DWR Texas Instruments Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SOIC 0 to 70 visit Texas Instruments Buy
SN74LS374N-10 Texas Instruments IC LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, Bus Driver/Transceiver visit Texas Instruments
SN74LS374DW Texas Instruments Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-SOIC 0 to 70 visit Texas Instruments

74LS374 function

Catalog Datasheet MFG & Type PDF Document Tags

74LS374 function

Abstract: GD54/74LS374 OCTAL D TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Feature â'¢ â'¢ â'¢ â'¢ â , 7 18 20 3 [ 20 3Q 3D 4D r | 9 | | l o| 4Q Function Table OUTPUT , CONTROL INPUTS W 4 y T " G G D 42 L1 TM4 TYUPICAL OF ALL OUTPUTS GDS4/74LS374 , 2-117 â  405Û757 00042b2 fiflO â  GD54/74LS374 Switching Characteristics, V CC = , CONTROL INPUT 1 74LS374 1D 1Q 2D 2Q 3D 30 4D 40 5D 5Q > DATA BUS2
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74LS374 function GD54/74LS374 LS374 GGD42

74LS374 function

Abstract: 74LS374 pin configuration GD54/74LS374 OCTAL D TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Feature â'¢ D-Type-Flops in a , Package Suffix-J : Ceramic Dual In Line Package Function Table OUTPUT CLOCK D OUTPUT CONTROL (CK) Q L , 4-241 This Material Copyrighted By Its Respective Manufacturer GD54/74LS374 7V 7V 7 V Absolute , Respective Manufacturer GD54/74LS374 Switching Characteristics, VCc = 5V, TA = 25°C PARAMETER* FROM , < CLOCK INPUT 1 74LS374 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q 7D 7Q 8D 8Q CK O 8D /a 70 6Q 6D
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74LS374 pin configuration 54LS 74LS 74ls374 parallel port 74ls374 equivalent

LOGIC OF 74LS373

Abstract: 74LS373 PIN CONFIGURATION AND SPECIFICATIONS 74LS373, 74LS374, S373, S374 MODE SELECT - FUNCTION TABLE '374 INPUTS OPERATING MODES Ü I Load and , and 3-State buffer operation I 74S374 NOTE: NOTE: hi.- 74LS373, 74LS374, S373, S374 Latches , -State Outputs 105mA 27mA 116mA 74S373 Product 74LS374 ORDERING CODE DESCRIPTION The '373 is an octal , 74LS373, 74LS374, S373, S374 The data on the D inputs are transferred to the latch outputs when the , 02 03 o4 05 06 07 LD02520S MODE SELECT - FUNCTION TABLE 373 INPUTS OPERATING
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LOGIC OF 74LS373 74LS373 PIN CONFIGURATION AND SPECIFICATIONS latch 74ls 373 LS 373 SQL-20 N74LS373N N74S373N N74LS374N N74S374N N74LS373D

74LS373 PIN CONFIGURATION AND SPECIFICATIONS

Abstract: 74LS374 pin configuration 74LS373, 74LS374, S373, S374 MODE SELECT â'" FUNCTION TABLE '374 OPERATING MODES INPUTS INTERNAL , (E) and Output Enable ( OE) control gates. 74LS373, 74LS374, S373, S3 74 Latches/Flip-Flops '373 , 105mA 74LS374 19ns 27mA 74S374 8ns 116mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , 74LS373, 74LS374, S373, S374 The data on the D inputs are transferred to the latch outputs when the Latch , '" FUNCTION TABLE '373 OPERATING MODES INPUTS INTERNAL REGISTER OUTPUTS OE E Dâ'ž Q0-Q7 Enable and read
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74LS374 74LS373 74ls373 74LS373 pin configuration 74L5374 pin configuration 74LS373 74L5373 74LS373 40 pin SOL-20 N74S373D N74LS374D N74S374D CD06830S 1N916
Abstract: GD54/74LS374 OCTAL D TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Feature â'¢ â'¢ â'¢ â'¢ â , Package Suffix-J : C eram ic Dual In Line P ackage Function Table OUTPUT CONTROL CLOCK (CK , OUTPUTS 4-241 GD54/74LS374 Absolute Maximum Ratings â'¢ â'¢ â'¢ Supply voltage, Vcc , ort-circu it should not excee d one second. 4 -2 4 2 mA mA 40 mA GD54/74LS374 Switching , Example 8-BIT SHIFT REGISTER OUTPUT CONTROL INPUT 1 74LS374 1D 4* 1Q 2D 4* 2Q -
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74L5373

Abstract: 74L5374 , o»E 3«. onoG» 3» CD06B40S 74LS373, 74LS374, S373, S374 Latches/Flip-Flops '373 Octal , TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS373 19ris 24mA 74S373 10ns 105mA 74LS374 , Product Specification Latches/Flip-Flops 74LS373, 74LS374, S373, S374 The data on the D inputs are , '" FUNCTION TABLE '373 OPERATING MODES INPUTS INTERNAL REGISTER OUTPUTS OE E Dn Q0-Q7 Enable and read , Manufacturer Signetics Logic Products Product Specification Latches/Flip-Flops 74LS373, 74LS374, S373, S374
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745373 S0701 C006830S 1N3064

UM9092A

Abstract: UM9092 LED LI/RX2 LED LI/RX3 LED LI/RX4 LED LI/RX5 LED OC CLK LI/RX6 LED 74LS374 LED_LATCH , POL6 LED POL7 LED 74LS374 LED_LATCH TP LINK/CARRIER SENSE LED Q0 Q1 Q2 Q3 Q4 Q5 Q6 , LED OC CLK PARTITION6 LED 74LS374 2 3 4 5 6 7 8 9 1 3 PARTITION7 LED , CLK 62.5% 74LS374 2 5 6 9 12 15 16 19 12.5% 25% 37.5% 50% AUI1 PARTITION LED , AUI2 JABBER LED 1 2 1K AUI2 LPBK LED 74LS374 LED_LATCH TRAFFIC LED D0 D1 D2
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RJ45A LANF7236 74LS164 DM9081 UM9092A UM9092 TP-LINK DPS05R09

74LS374 function

Abstract: 74LS374 NATIONAL SEIIICOND -CLOGIO 31E D b S D lia 2 0071=157 G T-46-07-11 K74CF374 OCTAL D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS PRELIMINARY 2/12/88 Functional Description The K74CF374 incorporates ferroelectric memory cells with the 74LS374 to produce a logic device functionally compatible with the 74LS374 that retains the output state of the device during power loss. Upon power up, the K74CF374 , both bipolar and CMOS based logic circuits. E in JM K74CF374 (Top View) FUNCTION TABLE (Each
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SD1122

74ls373 parallel port

Abstract: d92 02 /74LS374 D87 54LS/74LS256 3 4 7 8 13 14 17 18 Do Di 02 D3 D4 Ds De D7 11 - CP 1 â'"0 OE , 12 Vcc = Pin 16 GND = Pin 8 13-53 FAIRCHILD DIGITAL TTL REGISTERS (Cont'd) I Item I Function , 17 Parallel-in/Parallel-out 54LS(2)/74LS374 8 â'" 8S _r 55 20 135 D86 9Z 18 Parallel-in/Parallel-out , 1 Lr) 20 21 â'" 80 D152 4L,6B,9B 14 8-Bit D Flip-Flop(3S) 54LS(2)/74LS374 8xD â'" K-T) 10 23 23 135
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74ls373 parallel port d92 02 74175 ttl pin diagram 74ls175 pin diagram 74198 74198 ttl 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373

74c906

Abstract: COP404N function select Clock output to latch D outputs and high order address bits Address out/data in flag 8 , ., 74LS374. The timing of D port data is then the same for COP404 and COP440. After DCK has risen to a "1" , of 0.4V. the 74LS374 may sink 10 times as much current as the COP44Q. At an output "1" level of 2.4V, the 74LS374 may source 10 times as much current as the COP440. On the other hand, the output "1" level of 74LS374 latch does not go to Vqc without an external pull-up resistor. In order to better
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74c906 COP404N microbus COP400 N48A COP440/COP340 74C906 C0P44O

SP74SC374F

Abstract: SP74SC374N , high noise immunityâ'"while maintaining full function and pin compatibility with the 74LS374. Speeds , SP74SC374_* ^ OCTAL EDGE TRIGGERED D FLIP-FLOP WITH 3-STATE OUTPUTS FEATURES â  Designed for driving high-capacitance or low-impedance loads in bus-oriented systems â  3-state outputs for bus interfacing â  Pin compatible with 74LS374 â  SPI CMOS technology â  Full TTL interface , level (either VCc °r GND). FUNCTION TABLE Note 1: Derate at 12mW/°C over +45 to +85° C RECOMMENDED
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SP74SC374F SP74SC374N

74LS374N

Abstract: 74LS373N Product Specification Latches/Flip-Flops 74LS373, 74LS374, S373, S374 MODE SELECT - FUNCTION , Signetics 74LS373, 74LS374, S373, S374 Latches/Flip-Flops '373 Octal Transparent Latch With 3 , Products Product Specification Latches/Flip-Flops 74LS373, 74LS374, S373, S374 T h e d ata on , DIAGRAM, '374 LD02S20S Vcc " Pin 20 GND = Pin 10 MODE SELECT - FUNCTION TABLE 373 IN PU TS O P , Signetics Logic Products Product Specification Latches/Flip-Flops 74LS373, 74LS374, S373, S374
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74LS374N 74LS373N pin diagram of IC 74LS373 74ls373 buffer ic LD02S 74LS374D

74ls373 buffer ic

Abstract: 54LS374DMQB was set up. The eight flip-flops of the DM54/74LS374 are edge-trig gered D-type flip flops. On the , even while the outputs are off. Function Tables DM54/74LS373 Output Control L L L H Enable G H H L X D H L X X Output H L Qo z Output Control L L L H DM54/74LS374 Clock T t L X D H L X X Output H L , DM54/74LS374 Posltlve-Edge-Triggered Flip-Flops OUTPUT CONTROL (1) (3) (*> IÌU (7) - .
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54LS374 54LS374DMQB IC 74ls373 features of IC 74LS373 IC 74ls374 ls373 54LS374DM LS373 DM54LS373/DM74LS373 54LS374/DM54LS374/DM74LS374 DM54LS373J DM54LS373W

Signetics 2650

Abstract: SIGNETICS 2656 MNEMONIC PIN NO. TYPE NAME AND FUNCTION DB0-DB7 38-40 1-5 I/O 8-bit Bidirectional Data Bus: All data , RAM can be disabled by a mask option. Function Select A 1X8 Function Select array of mask-programmable contacts determine the function of each of the multi-purpose I/O pins (X0-X7). Two modes exist: 1. CE - , continues to function as a read/write element even if all multi-purpose I/O pins are programmed as chip , Array (PGA), and the Function Select Array. On receipt of a card deck, Signetics will translate the card
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128X8 74LS240 1A08-1A0F Signetics 2650 SIGNETICS 2656 2kx8 rom 2655 ppi ADR0-ADR14 74LS259/93L34 0000-07FF 82S181 0800-0BFF 1400-14FF

SP74HCT374N

Abstract: 74LS374 -state outputs for bus interfacing â  Pin compatible with 74LS374 â  SPI CMOS technology â  Full TTL , margin, low power consumption, high noise immunityâ'"while maintaining full function and pin compatibility with the 74LS374. Speeds are comparable to the low power Schottky device family. The SP74HCT374 , appropriate logic voltage level (either Vcc or GND). FUNCTION TABLE Output Enable Clock O Output L ! H H L
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SP74HCT374N SP74HCT374J

54LS374

Abstract: H122 level of the data that was set up. The eight flip-flops of the DM54/74LS374 are edge-triggered D-type , were set up at the D inputs. Function Tables DM54/74LS373 bSGliaa QQTQQit. 5 T-46-07-11 A buffered , outputs are off. DM54/74LS374 Output Control Enable G D Output Output Control Clock D Output L H H H , Diagrams DM54/74LS373 Transparent Latches output ID_ control as DM54/74LS374 Posltlve-Edge-Trlggered
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DM74LS373N DM74LS373WM H122 J20A DMS4LS373J 54LS374FMQB 54LS37

74c906

Abstract: 2 input and gate 24v ¡ MICROêUS FUNCTION SELECT â'"M * I î î Il H RESISTER R REGISTER I QRt6ISTE" il . I F" è BUFFER »BUFFI , MICROBUS function select Clock output to latch D outputs and high order address bits Address out/data in , , e.g., 74LS374. The timing of D port data is then the same for COP404 and COP440. After DCK has risen , 4, at an output "0" level of 0.4V, the 74LS374 may sink 10 times as much current as the COP440. At an output "1" level of 2.4V, the 74LS374 may source 10 times as much current as the COP440. On the
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MM2716 2 input and gate 24v 0M74LS using top223 for pc power supply Dual Port V-RAM cop44c COP44C 0M74LS374 DM74LS373 TL/DO/6916-4

74LS334

Abstract: DM54LS373J the DM54/74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q , Package Number J20A, M20B, N20A or W20A Function Tables DM54/74LS373 Output Enable Control G , established. DM54/74LS374 Output Clock D Output H Control L H L L L L , Transparent Latches DM54/74LS374 Positive-Edge-Triggered Flip-Flops DS006431-3 DS006431-4 3
Fairchild Semiconductor
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DM74LS374N 74LS334 dm54ls374j DM74LS373/DM74LS374 DM54/74LS374 DM54LS374J DM74LS374WM DM54LS374W

ci 74174

Abstract: D flip-flop 74175 pin Pin 16 GND = Pin 8 13-62 FAIRCHILD DIGITAL TTL REGISTERS (Cont'd) I Item I Function DEVICE NO. No , Parallel-in/Parallel-out 54LS(2)/74LS374 8 â'" 8S _r 55 20 135 D86 9Z 18 Parallel-in/Parallel-out 54LS(2 , 21 â'" 80 D152 4L,6B,9B 14 8-Bit D Flip-Flop(3S) 54LS(2)/74LS374 8xD â'" K-T) 10 23 23 135 D86 9Z
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ci 74174 D flip-flop 74175 pin 7475 D flip-flop 9374 74116 74174 93L14 54LS/74LS279 54LS/74LS75 93L08 54LS/74LS77 54S/74S175

DM74LS374N

Abstract: 74ls373 datasheet states that were set up at the D inputs Function Tables DM54 74LS373 DM54 74LS374 Output , be latched at the level of the data that was set up The eight flip-flops of the DM54 74LS374 are , established u Logic Diagrams DM54 74LS373 Transparent Latches DM54 74LS374 Positive-Edge-Triggered
National Semiconductor
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DM54LS373 DM54LS374 DM74LS374 74ls373 datasheet 74LS374 DATASHEET 74LS374 74LS373 74ls373 datasheet 74LS374 texas C1995 RRD-B30M105
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