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74LS191 pins

Catalog Datasheet MFG & Type PDF Document Tags

74LS191 pins

Abstract: 74190 TYPE 74190 74191 74LS191 TYPICAL fMAX 25MHz 25MHz 25MHz TYPICAL SUPPLY CURRENT (TOTAL) 65mA 65mA , PINS DESCRIPTION Input Inputs Outputs 74 3ul 1ul 10ui 74S 3LSui 1LSul 10LSul CE Other All NOTE , 74191/74LS191. The TC output will remain HIGH until a state change occurs, either by counting or p , MA mA mA 74LS191 UNIT VOH HIGH-level output voltage Vc c " MIN, V|H = MIN, V|U = MIN, l0
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74LS191 pins 74190 counter 74190 ttl 74190 signetics 74190 74191 state diagram LS191 N74190N N74191N N74LS191N N74LS191D SOL-16

ci 74190

Abstract: counter 74190 Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74190 25MHz 65mA 74191 25MHz 65mA 74LS191 , * Specifications, see the Si9netics Military Products INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION , the count-up mode for 74191 /74LS191. The TC output will remain HIGH until a state change occurs , CONDITIONS1 74190, 191 74LS191 UNIT Min Typ2 Max Min Typ2 Max V0h HIGH-level output voltage Vcc =
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ci 74190 ci 74191 74191 counter ttl 74191 74190 equivalent 74LS 1N916 1N3064

74LS191 pins

Abstract: 74190 74LS191 25MHz 20mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V±5%; Ta = 0°C to +70°C Plastic DIP N74190N, N74191N, N74LS191N Plastic SOL-16 N74LS191 D PINS DESCRIPTION 74 74S CE Input 3ul , count-up mode for 74191 /74LS191. The TC output will remain HIGH until a state change occurs, either by , CONDITIONS1 74190, 191 74LS191 UNIT Min Typ2 Max Min Typ2 Max Voh HIGH-level output voltage Vcc =
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74ls191 function table 74190 counter pin diagram of 74LS191 74190 application Binary counter simple Signetics CD06110S WFM570S N3064

74LS160

Abstract: Synchronous 74163 74LS190 54/74191 74LS191 16 Presettable 1/ 16 Presettable 10 Presettable 10 Presettable 16 Presettable , Pin 10 NC = 2, 3, 4, 13 Vcc = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 54/7493A, 54LS/74LS93 , = Pins 4, 6, 7, 13 Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D127 9310, 93L10
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93S16 93S05 74LS160 Synchronous 74163 74192 74LS190 pins 74LS193 Fairchild 74190 93L16 54LS/74LS160 54LS/74LS161 54LS/74LS162 54LS/74LS163

74LS190 pins

Abstract: 74LS192 PIN diagram CPi MR Oo Qi 02 03 12 13 9 5 4 8 VCC = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 S4/7493A, 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10 , ,9B 19 Up/Down 54/74191 16 A s 25 20 325 D130 4L,7B,9B 20 Up/Down 74LS191 16 A s 40 20 90 D130 7B,9B
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74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins 74LS161 74160 54/7490A 54LS/74LS90 74LS92 S4/74293 54LS/74LS293 54LS/74LS196

pin diagram of ic 74190

Abstract: ic 74190 TYPE 74190 74191 74LS191 TYPICAL f MAX 25MHz 25MHz 25MHz TYPICAL SUPPLY CURRENT (TOTAL) 65mA 65mA , PINS CË Other All NOTE: W h e r e a 7 4 u n it lo a d (u l) is u n d e r s to o d to b e 4 0 /j A l|H , in the count-up mode for 74191/74LS191. The TC output will remain HIGH until a state change occurs , 35 120 0.1 0.3 0.5 0.4 -1 .5 Max V V V V mA mA mA ma 74LS191 UNIT VoH HIGH-levef output
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pin diagram of ic 74190 ic 74190 pin diagram of ic 74191 logic diagram of ic 74191 f ic 74190 and pin diagram of IC 74190 WF06600S

pin diagram of ic 74190

Abstract: 74LS191n TYPE 74190 74191 74LS191 T Y P IC A L tMAx 25M H z 25M H z 25M H z T Y P IC A L S U PP LY C U R R E , Signetics Military Products Data Manual. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS CE O ther A ll , re range unless otherw ise noted.) 7 41 90, 191 1t o I 1 /U N U IIIU N & ' 74LS191 U N IT Min 2.7
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74LS191n 74191n 74190N 74191 logic diagram pin diagram of ic 74ls191 4190N 74191N

74LS167

Abstract: F199 transistor Number Comprexityt Cell2 Propagation Delay Max. Number of Signal Pins Output Options Supply ^Voltage , supply and ground pins, 6: Two speed versions, standard and high speed (H-version), available. PACKAGE , between the input and output pins of the circuit. This assures that the computerized layout for the , 74LS183 22 26 F190 74LS190 71 85 F191 74LS191 68 82 F192 74LS192 62 74 F193 74LS193 58 74 F194
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74LS167 74S168 74LS382 74LS396 F199 transistor 74LS514 74LS76A transistor b1100 B-2000 RIT-135 B-240 B-350 B-600 B4100

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Function 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A 74LS196 74LS197 74LS240 74LS241 74LS244 74LS251 , ., latches, flip-flops, and pins) w ithin Altera EPLD s. Together, these features make it easy to im plem ent , specific chip assignments for flip-flops and pins in the source design files. After partitioning, the
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74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions HP400 IC-24 QIC-24

sn 74373

Abstract: SN 74114 74LS175 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A 74LS196A 74LS197 74LS240 74LS241 , (e.g., latches, flip-flops, and pins) within Altera EPLDs. Together, these features make it easy to , control the d esig n 's partitioning b y entering specific chip a ssig nm ents for flip-flops and pins in
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sn 74373 SN 74114 logic diagram of ic 74112 IC 7486 xor 7486 xor IC sn 74377

Frequency-To-Voltage Conversion

Abstract: VREF. The relationship of the allowable operating voltage ranges on important pins is show in Figure 13 , by reversing the connections to pins 14 and 15. Figure 17 shows a digital conditioning circuit which , "16" Logic "1" 1.6MHz , Clock ° TTL Data , o 74LS191 Load U/D RC D 2M£i Cj ° \1 14 CK
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Frequency-To-Voltage Conversion VFC100 AN-130 15VDC

Burr-Brown Application Note

Abstract: INA101 important pins is show in Figure 13. Note that the integrator amplifier output cannot swing more than 0.2V , (active high) input pulses can be accepted by reversing the connections to pins 14 and 15. Figure 17 , /D RC Load +15VDC 0.1µF 4 74LS191 C C1 0.1µF R2 2M 0 to 10V Input
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Burr-Brown Application Note INA101 VFC100AG VFC100BG OPA111 HCPL-2731

pin diagram of IC 4013 n

Abstract: INA101 is VIN = (N/M) 20V. The relationship of the allowable operating voltage ranges on important pins , accepted by reversing the connections to pins 14 and 15. Figure 17 shows a digital conditioning circuit , Load +15VDC 0.1µF 4 74LS191 C C1 0.1µF R2 2M 0 to 10V Input Data TTL
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pin diagram of IC 4013 n Voltage-to-Frequency Interface

circuit diagram TA 4013

Abstract: 4013 divider important pins is show in Figure 13. Note that the integrator amplifier output cannot swing more than 0.2V , (active high) input pulses can be accepted by reversing the connections to pins 14 and 15. Figure 17 , /D RC Load +15VDC 0.1µF 4 74LS191 C C1 0.1µF R2 2M 0 to 10V Input
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circuit diagram TA 4013 4013 divider 547h

547G

Abstract: INA101 important pins is show in Figure 13. Note that the integrator amplifier output cannot swing more than 0.2V , (active high) input pulses can be accepted by reversing the connections to pins 14 and 15. Figure 17 , /D RC Load +15VDC 0.1µF 4 74LS191 C C1 0.1µF R2 2M 0 to 10V Input
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547G 1nF mylar capacitor

VFC100

Abstract: allowable operating voltage ranges on important pins is show in Figure 13. Note that the integrator , can be accepted by reversing the connections to pins 14 and 15. Figure 17 shows a digital , "¦ 14 RC Load +15VDC 0.1µF 4 U/D 74LS191 C C1 0.1µF R2 2Mâ"¦ 0 to 10V
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C350AVB

Abstract: full adder using Multiplexer IC 74150 Cell2 Propagation Delay 4 4 4 4 4 4 ns ns ns ns ns ns Max. Number o f Signal Pins 54 74 80 68 68 52 72 , ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns Max.3 Number o f Signal Pins , = 2, 2-input NAND gate. The values in parenthesis show the maximum number o f signal pins when no , Com plexity1 Cell2 Propagation Delay Max3 Number.of Signal Pins I/O Options Supply4 Voltage Operating5 , Fujitsu. 3: Including 7 RAM Test Pins or 5 ROM Test Pins. PACKAGE OPTIONS Tech nology Dual In-line
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C350AVB full adder using Multiplexer IC 74150 74ls69 MB652xxx T2D 7N IC 74ls147 pin details 37MT7 54L98 54L99 74H101 74H102 74H103

74LS382

Abstract: C1602A Complexly1 Cell2 Propagation Delay Max. Number off Signal Pins I/O Opt Iona Supply3 Voltage Operating4 Temp , Technology Dirrice Name Part Number Complexity1 Cell2 Propagation Delay Max.3 Number of Signal Pins I/O , values In parenthosis show the maximum number of signal pins when no high driving capabfllty (Iql " ss , Signal Pins I/O Optlont Supply3 Voltalo Operating Temp. Ranga C-20000UH MB 600xxx 20160 gates 1.0 ns , F190 74LS190 106 F191H 74LS191 73 F192 74LS192 92 F193 74LS193 82 F194 74LS194A 78 F195 74LS195A
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74LS381 C1602A 74LS08 fan-in 74ls517 74LS556 74LS86 full adder C-15006UM 74LS107 74H108 74LS109A 74LS112A 74LS113

INA101

Abstract: VFC100AG important pins is show in Figure 13. Note that the integrator amplifier output cannot swing more than 0.2V , (active high) input pulses can be accepted by reversing the connections to pins 14 and 15. Figure 17 , /D RC Load +15VDC 0.1µF 4 74LS191 C C1 0.1µF R2 2M 0 to 10V Input , -Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package
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OPTICAL COUPLER

VFC100AG

Abstract: on important pins is show in Figure 13. Note that the integrator amplifier output cannot swing more , pulses can be accepted by reversing the connections to pins 14 and 15. Figure 17 shows a digital , . ® VFC100 14 Data "16" Logic "1" 1.6MHz Clock TTL C Data 74LS191 Load U/D RC R2 2M ±1% Range R1 7 , CDIP CDIP CDIP Package Drawing J J J Pins Package Eco Plan (2) Qty 16 16 16 TBD TBD TBD Lead
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