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Part Manufacturer Description PDF & SAMPLES
SN74LS156N3 Texas Instruments Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs 16-PDIP 0 to 70
SN74LS156D Texas Instruments Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs 16-SOIC 0 to 70
SN74LS156NE4 Texas Instruments Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs 16-PDIP 0 to 70
SN74LS156DRE4 Texas Instruments Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs 16-SOIC 0 to 70
SN74LS156DG4 Texas Instruments Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs 16-SOIC 0 to 70
SN74LS156DRG4 Texas Instruments Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs 16-SOIC 0 to 70

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74LS156 Datasheet

Part Manufacturer Description PDF Type
74LS156 Fairchild Semiconductor Dual 2-Line to 4-Line Decoders/Demultiplexers Original
74LS156 Hitachi Semiconductor Dual 2-line-to-4-Line Decoders / Demultiplexers(with open collector outputs) Original
74LS156 Motorola DUAL 1-OF-4 DECODER-DEMULTIPLEXER Original
74LS156 Texas Instruments DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS Original
74LS156 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan
74LS156 National Semiconductor DUAL 1-OF-4 DECODER/DEMULTIPLEXER Scan
74LS156 Raytheon Dual 2-line-To-4-line Decoders/Demultiplexers Scan
74LS156 Signetics Dual 2-Line to 4-Line Decoder / Demultiplexer Scan
74LS156 Signetics Dual 2-Line To 4-Line Decoder/Demultiplexer (Open Collector) Scan
74LS156DC Fairchild Semiconductor DUAL 1-OF-4 DECODER / DEMULTIPLEXER Scan
74LS156DC National Semiconductor DUAL 1-OF-4 DECODER/DEMULTIPLEXER Scan
74LS156FC Fairchild Semiconductor DUAL 1-OF-4 DECODER / DEMULTIPLEXER Scan
74LS156FC National Semiconductor DUAL 1-OF-4 DECODER/DEMULTIPLEXER Scan
74LS156PC Fairchild Semiconductor DUAL 1-OF-4 DECODER / DEMULTIPLEXER Scan
74LS156PC National Semiconductor DUAL 1-OF-4 DECODER/DEMULTIPLEXER Scan

74LS156

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: SN54/74LS155 SN54/74LS156 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder "a" has an Enable gate with one active HIGH and , TTL DATA 5-1 E A0 DECODER b 1 2 3 10 11 12 SN54/74LS155 · SN54/74LS156 LOGIC , 5-3 SN54/74LS156 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit Motorola
Original
LS156 LS155 truth table for 4 to 16 decoder truth table for 1 to 16 decoder 2 to 4 decoder for ttl circuit SN54LSXXXJ SN54-74LS155 SN54/74LS156 LS156-OPEN-COLLECTOR 751B-03
Abstract: Type SN74LS156N SN74LS156N 74LS156 74LS156 74LS156 74LS156 74LS156 74LS156 59629750801Q2A SNJ54LS Texas Instruments
Original
SN54155 SN54156 SN54LS155A SN54LS156 SN74155 SN74156
Abstract: 74LS156 SN74LS156NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS156 SN74LS156NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS156 SN74LS156NSRE4 ACTIVE , 74LS156 SN74LS156NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS156 SN74LS156NSRG4 ACTIVE SO NS 16 2000 Green Texas Instruments
Original
SN74LS155A SN74LS156 SDLS057 SN54155A SN74155A ISO/TS16949
Abstract: (M) MOTOROLA DUAL 1-0F-4 DECODER/ DEMULTIPLEXER The SN54/74LS155 and SN54/74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs , established by an external resistor. SN54/74LS155 SN54/74LS156 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER , /74LS156 LOGIC DIAGRAM Vcc = PIN 16 GND = PIN 8 O = PIN NUMBERS Ea Ea A1 Oil© ©I I© EbEb @i i© ©I ©J , /74LS156 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit Vcc Supply Voltage 54 4.5 5.0 5.5 V -
OCR Scan
SN74LSXXXD SN74LSXXXN truth table for 1 to 4 decoder
Abstract: SN74LS155 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The SN54 / 74LS156 is a high speed Dual 1-of-4 Decoder/Demultiplexer. This device has two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder "a" has an Enable gate with one active HIGH and one active LOW input. Decoder "b" , June, 2006 - Rev. 7 1 SN74LS155 SN54/74LS156 LOGIC DIAGRAM 1 Ea Ea 2 13 A0 A1 3 , Level X = Don't Care http://onsemi.com 2 SN74LS155 SN54/74LS156 GUARANTEED OPERATING RANGES ON Semiconductor
Original
SN74LS155d SN74LS155/D
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 ¿Mil PL Po Pi P2 P3 5- Ã/D RC 4-0 CE 14- CP TC Qo Qi Ã2 03 0â'" 13 -12 3 2 6 7 Vcc = Pin 16 GND = Pin 8 1 2 3 1 1 1 15 14 13 A 1 1 E Ao Ai E Ao Ai DECODER a DECODER b Oo Ol O2 O3 , D132 4L,6B,9B 16 Dual 1 -of-4 54LS/74LS156 2 2+2 4+4 5.5 33 26 31 5.0 D132 4L,6B,9B 17 1 -of-8 -
OCR Scan
93L01 93L11 D133 TTL 9334 ttl 74155 74LS42 54LS/74LS156 93L34 54LS/74LS259 54LS/74LS42 54LS/74LS145
Abstract: MOTOROLA SN54LS/74LS155 SN54LS/74LS156 D E S C R IP T IO N - T h e S N 5 4 L S /7 4 L S 1 55 and S N 5 4 L S /7 4 L S 1 56 are high speed Dual 1-of-4 D ecoder/D em ultiplexers. These devices have tw o decoders w ith comm on 2-bit Address inputs and separate gated Enable inputs. Decoder " a " has , Pin Numbers MOTOROLA SCHOTTKY TTL DEVICES SN54LS/74LS155 · SN54LS/74LS156 F U N C T IO N A L , Fig. 1 Fig. 2 MOTOROLA SCHOTTKY TTL DEVICES 5-123 SN54LS/74LS156 GUARANTEED OPERATING -
OCR Scan
SN54LS/74LS156
Abstract: DECODERS/DEMULTIPLEXERS N) O O C = open collector 3 S = 3-state Unit Load (UL) = 4 0 MA HIGH/1 6mA LO W co o o 'j ¿ 00 o 00 ó 00 C D O l c 0 } -I o O c c u o t* . c 0) o C O ro O c 0) -I o P » . 54/74155 c 0) o -& 54S/74S139 It c 0) -I o o C O Item c 0) -L Function o Ó 00 c 0 ) -I o -& 93L21 CO (O o 54LS/74LS156 54/74156 54LS/74LS155 54LS , D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 1 2 15 14 13 13 3 1415 E A0 A, Ao Ao -
OCR Scan
IC 74150 pin diagram 7442 ic pin diagram ic 74155 ic 74190 IC 7443 74ls152 54S/74S138 54LS/74LS138 93S137
Abstract: SN54/74LS155 SN54/74LS156 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder "a" has an Enable gate with one active HIGH and , SN54/74LS156 LOGIC DIAGRAM Ea Ea 1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 7 A0 2 , Figure 1 t PLH 1.3 V 1.3 V Figure 2 FAST AND LS TTL DATA 5-264 SN54/74LS156 Motorola
Original
demultiplexer truth table LS TTL family characteristics SN54/74LS15 5 inputs OR gate truth table DATA SHEET OF 74LS155
Abstract: ESD > 3500 Volts SN54/74LS155 SN54/74LS156 DUAL 1-0F-4 DECODER/ DEMULTIPLEXER , SN54/74LS156 LOGIC DIAGRAM V , SN54/74LS156 G U ARANTEED OPERATING RANGES S ym bol vcc Supply Voltage Parameter 54 74 54 74 54, 74 -
OCR Scan
74 ls 155 demultiplexer 54/74LS
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 ¿Mil PL Po Pi P2 P3 5- Ã/D RC 4-0 CE 14- CP TC Qo Qi Ã2 03 0â'" 13 -12 3 2 6 7 Vcc = Pin 16 GND = Pin 8 1 2 3 1 1 1 15 14 13 A 1 1 E Ao Ai E Ao Ai DECODER a DECODER b Oo Ol O2 O3 , D132 4L,6B,9B 16 Dual 1 -of-4 54LS/74LS156 2 2+2 4+4 5.5 33 26 31 5.0 D132 4L,6B,9B 17 1 -of-8 -
OCR Scan
D131I pin diagram of 74LS191 TTL 7452 74190 74155 74LS151 Logic DIAGRAM 74151 93S138 54/74151A 54S/74S251 54LS/74LS152
Abstract: PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74156 20ns 25mA 74LS156 31ns 6.1mA ORDERING CODE PACKAGES , CONDITIONS1 74156 74LS156 UNIT Min Typ2 Max Min Typ2 Max Ioh HIGH-level output current Vcc = MIN, V -
OCR Scan
N74156N N74LS156N N74LS156D 1N916 1N3064 74156 74ls gate symbols 74LS156 SIGNETICS 74156 demultiplexer signetics demultiplexer 74ls 74LS156 equivalent WF07570S
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 ¿Mil PL Po Pi P2 P3 5- Ã/D RC 4-0 CE 14- CP TC Qo Qi Ã2 03 0â'" 13 -12 3 2 6 7 Vcc = Pin 16 GND = Pin 8 1 2 3 1 1 1 15 14 13 A 1 1 E Ao Ai E Ao Ai DECODER a DECODER b Oo Ol O2 O3 Oo Oi O2 O3 TTTT 4 5 6 7 tÌÌÌ 12 11 10 9 Vcc = Pin 16 GND = Pin 8 TTTT hTT 7 6 5 4 9 10 11 -
OCR Scan
74LS138 7443 ttl ttl 74191 7443 TTL 74ls138 74LS139
Abstract: FAST AND LS TTL DATA SN54/74LS155 · SN54/74LS156 FU N C T IO N A L D E S C R IP T IO N - The , " \ 13 V _ Fig. 1 \ Fig. 2 u ^ 7. FAST AND LS TTL DATA SN54/74LS156 -
OCR Scan
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 ¿Mil PL Po Pi P2 P3 5- Ã/D RC 4-0 CE 14- CP TC Qo Qi Ã2 03 0â'" 13 -12 3 2 6 7 Vcc = Pin 16 GND = Pin 8 1 2 3 1 1 1 15 14 13 A 1 1 E Ao Ai E Ao Ai DECODER a DECODER b Oo Ol O2 O3 , D132 4L,6B,9B 16 Dual 1 -of-4 54LS/74LS156 2 2+2 4+4 5.5 33 26 31 5.0 D132 4L,6B,9B 17 1 -of-8 -
OCR Scan
74191 8 bit D132 7442 logic diagram D flip-flop 74175 pin 74155 PIN DIAGRAM D134 54LS/74LS298 93L08 54LS/74LS256 54S/74S174 54LS/74LS174
Abstract: PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74156 20ns 25mA 74LS156 31ns 6.1mA ORDERING CODE PACKAGES , unless otherwise noted.) PARAMETER TEST CONDITIONS1 74156 74LS156 UNIT Min Typ2 Max Min Typ2 -
OCR Scan
74156 demultiplexer TTL 74156 Signetics 3 x 8 decoder decoder 74156 74LS 5.1 decoder circuits WFQ75
Abstract: O T A L ) CURRENT 74156 74LS156 20ns 31ns 25mA 6.1mA ORDERING CODE C O M M E R C IA , 74LS156 UNIT >O H HIGH-level output current V cc - MIN, V|h - MIN, V|L = MAX, Voh = 5.5V Vc c = -
OCR Scan
pin configuration IC 74156 IC 74156 WFD7570S WF06450S
Abstract: = 0°C to +70° C 74156PC, 74LS156PC 74156DC, 74LS156DC 74156FC,74LS156FC MILITARY GRADE Vcc = , 156 " IC r- i c n (, n '/ is v., ' ^ 54/74156 54LS/74LS156 DUAL 1-OF-4 DECODER/DEMULTIPLEXER (With Open-Collector Outputs) DESCRIPTIONâ'"The '156 contains two decoders with common Address (Ao, A-i) inputs and separate enable gates. Decoder "a" has an enable gate with one active HIGH and one active LOW input, while decoder "b" has two active LOW inputs. If the enable functions are -
OCR Scan
54156DM 54LS156DM 54156FM 54LS156FM 74 LS 00 Logic Gates EA45 ic address decoder logic diagram of dual 2 to 4 decoder
Abstract: are HIGH. TYPE 74156 74LS156 TYPICAL PROPAGATION DELAY 20ns 31ns TYPICAL SUPPLY CURRENT , temperature range unless otherwise noted.) 74156 PARAMETER 1t o 1 U U N U I1IUNS ' Min 'OH 74LS156 UNIT -
OCR Scan
C005970S WF07580S
Abstract: requirements of each decod er are not met, all outputs of that decod er are HIGH. TYPE 74156 74LS156 , 40 6.1 -0 .4 10 Min 74LS156 UNIT Typ2 Max 100 0.5 0.4 -1 .5 mA ·o h HIGH-level output current -
OCR Scan
demultiplexer 3 16 ttl F07590S
Abstract: 74LS156 . FN P A C K A G E ( T O P V IE W ) IO O « ·- * - 2 > Ü IO , voltage, V q c High-level o u tp u t voltage, V q Low -level o u tp u t current, I o h SN 74LS156 M IN , SN 74LS156 M IN 2 0.7 0.8 -1 .5 100 0 .2 5 0 .3 5 0.1 20 -0 .4 0.4 0.5 0.1 20 -0 .4 6.1 10 TYPt MAX , O G IC SN 54LS156 T E S T C O N D IT IO N S M IN SN 74LS156 TYP 25 MAX 40 ns U N IT Y 2 2 3 -
OCR Scan
74LS155A ic 74155 decoder IC TTL 74155 sn7415 SN541SS N54156 LS155A 54LS155A
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 ¿Mil PL Po Pi P2 P3 5- Ã/D RC 4-0 CE 14- CP TC Qo Qi Ã2 03 0â'" 13 -12 3 2 6 7 Vcc = Pin 16 GND = Pin 8 1 2 3 1 1 1 15 14 13 A 1 1 E Ao Ai E Ao Ai DECODER a DECODER b Oo Ol O2 O3 , 54/74156 2 2+2 4+4 5.5 23 20 125 10 D132 4L,6B,9B 16 Dual 1 -of-4 54LS/74LS156 2 2+2 4+4 -
OCR Scan
pin diagram decoder 74154 74155 decoder TTL 7448 74LS247 74LS42 cmos 7SEG COM ANODE 54LS/ 9317B 9317C 54LS/74LS47 54LS/74LS48
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