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Part Manufacturer Description Datasheet BUY
SN74LS138NP3 Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, PLASTIC, MS-001BB, DIP-16 visit Texas Instruments
SN74LS138DE4 Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16 visit Texas Instruments
SN74LS138NSRG4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SO 0 to 70 visit Texas Instruments
SN74LS138DRE4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments
SN74LS138DRG4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments
SN74LS138DG4 Texas Instruments 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 visit Texas Instruments

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74LS138 Datasheet

Part Manufacturer Description PDF Type
74LS138 Fairchild Semiconductor Decoder/Demultiplexer Original
74LS138 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan
74LS138 Raytheon Decoders / Demultiplexers Scan
74LS138 Signetics Decoders/Demultiplexers Scan
74LS138 Signetics Decoder/Demultiplexer Scan
74LS138 Signetics Integrated Circuits Catalogue 1978/79 Scan
74LS138C N/A TTL Data Book 1980 Scan
74LS138DC Fairchild Semiconductor 1 of 8 Decoder / Demultiplexer Scan
74LS138FC Fairchild Semiconductor 1 of 8 Decoder / Demultiplexer Scan
74LS138M N/A TTL Data Book 1980 Scan
74LS138PC Fairchild Semiconductor 1 of 8 Decoder / Demultiplexer Scan

74LS138

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138 , Decoders/Demultiplexers 74LS138, S138 LOGIC DIAGRAM *2 A1 *© *1 *2 63 LD01M0S ( ) - Pin number , 5-231 Signetics Logic Products Product Specification Decoders/Demultiplexers 74LS138, S138 , recommended operating free-air temperature range unless otherwise noted.) 74LS138 PARAMETER Min V OH
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pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 N74S13BN N74LS138N N74LS138D N74S138D 1N916 1N3064

CI 74LS138

Abstract: 74LS138 pin configuration HIGH or active LOW state. 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , DIAGRAM 74LS138, S138 *2 A, AO Ã', 12 EJ LD01MOS ( ) « Pin number Vcc ~ P«n 16 GND - Pin 6 5 , 74LS138, S138 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless otherwise noted , unless o therwise noted.) PARAMETER TEST CONDITIONS1 74LS138 74S138 UNIT Min Typ2 Max Min , Specification Decoders/Demultiplexers AC WAVEFORMS 74LS138, S138 jfz y:_ t»«phl«j l-'plh-j Win \vM n
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CI 74LS138 TTL 74ls138 74 LS 138 DECODER intel 3205 74l5138 of 74LS138 3 to 8 decoder N74S138N

FUNCTIONAL APPLICATION OF 74LS138

Abstract: 74LS138 3 to 8 decoder Pin Am25LS138 â'¢ Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer DISTINCTIVE , inputs. The Am54LS/74LS138 is a standard performance version of the Am25LS138. See appropriate , 3-30 This Material Copyrighted By Its Respective Manufacturer Am25 LS/54 LS/74LS138 ELECTRICAL , . (Note 4) 2.0 6.3 ELECTRICAL CHARACTERISTICS Am54LS/74LS138 The Following Conditions Apply Unless , Respective Manufacturer Am25 LS/54 LS/74LS138 SWITCHING CHARACTERISTICS (TA = +25°C, Vcc = 5.0V) _
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FUNCTIONAL APPLICATION OF 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to 8 decoder notes pin for 74LS138 LOGIC DESCRIPTION OF 74LS138 74ls138 3-8 25LS138 54LS/74LS138 MIL-STD-883 LS/74LS138 54LS/74LS

LOGIC OF 74LS138

Abstract: 74LS138 pin configuration Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138 , Decoders/Demultiplexers 74LS138, S138 LOGIC DIAGRAM A2 A0 Ei E2 E3 L C O IS fe O S ( } = Pin , Decoders/Demultiplexers 74LS138, S138 ABSOLUTE MAXIMUM RATINGS PARAMETER Vcc V|N l|N VOUT Ta Supply , otherwise noted.) 74LS138 Min Typ2 3.4 0.35 0.25 0.5 0.4 -1 .5 V, = 5.5V -1 .2 1.0 0.1 20 -0 .4 -2 -2 0 6.3
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74LS138 3 to pin configuration

LOGIC OF 74LS138

Abstract: pin for 74LS138 Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , state. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS138 20ns 6.3mA 74S138 7ns , Decoders/Demultiplexers 74LS138, S138 LOGIC DIAGRAM a2 a, aq e, e2 e3 LD01à ( ) = Pin number Vcc - P , Decoders/Demultiplexers 74LS138, S138 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range , /Demultiplexers 74LS138, S138 AC WAVEFORMS V.N \iV»« r*'PHL"j U'PLH-j VOUT l-»PHL-| i-'PLHâ'"j VOUT \V
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74LS138 pins 74l513 74LS LD01

block diagram of 74LS138 3 to 8 decoder

Abstract: 74LS138 3 to 8 decoder notes TSL230 and a 74LS138 3 line to 8 line decoder tied to some LED's, we can construct a UV monitor. This , pins to a 74LS138 to display the suggesed SPF on the 8 LED's. Block Diagram: Display TSL230 , battery 16 6 7 9 10 11 12 13 14 15 74LS138 3 +5 1 7 +5 2
Microchip Technology
Original
NJM78L05A block diagram of 74LS138 3 to 8 decoder 12C508 74LS138 DATASHEET block diagram of 74LS138 1 line to 16 line application note PIC12C508 74LS138 data sheet PIC12C508 DS40160A/5

74ls138 truth table

Abstract: 74LS138 (g) MOTOROLA 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address , Effects SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER LOW POWER SCHOTTKY ranimniinfmninm VCC Oo , AND LS TTL DATA SN54/74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder , Figure a 031 FAST AND LS TTL DATA 5-131 SN54/74LS138 GUARANTEED OPERATING RANGES S ym bol V
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74ls138 truth table connection for 74LS138 demultiplexer 3 to 8 truth table 74ls138 demultiplexer Truth table of 1 to 16 demultiplexer SN5474LS138 SN54/74LS138 751B-03 SN54LSXXXJ SN74LSXXXN SN74LSXXXD

M02S7S7

Abstract: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration â'¢ Designed Specifically for High Speed Memory Decoders and Data Transmission Systems â'¢ Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception â'¢ Schottky Clamped for High Performance DATA OUTPUTS Vcc , . ~ 6 5 ° C to 1 5 0 ° C 2-78 M02S7S7 00DM2E3 03G GD54/74LS138 Application Example , 2-79 405Û757 0004224 T77 â  GD54/74LS138 Switching Characteristics, Vcc = 5V , T a = 25Â
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GD54/74LS138 Q004225
Abstract: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration â'¢ â'¢ â'¢ Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception Schottky Clamped for High Performance DATA O , . - 6 5 ° C to 1 5 0 ° C 4 -9 8 GD54/74LS138 Application Example 4-LINE TO 16 , shorted at a tim e, and duration should n ot e xcee d o ne second. 4-9 9 GD54/74LS138 Switching -
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74LS138

Abstract: 74LS138 3 to 8 decoder Pin SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 , O3 14 O2 15 O1 O0 FAST AND LS TTL DATA 5-1 SN54/74LS138 FUNCTIONAL , a FAST AND LS TTL DATA 5-2 SN54/74LS138 GUARANTEED OPERATING RANGES Symbol Parameter
Motorola
Original
motorola 74ls138 74LS138 1 to 8 decoder notes demultiplexer 74LS138

intel 8085 microprocessor

Abstract: 8085 memory organization a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual Chip , from the 74LS138 decoder. The display system can be shortened by removing HDSP-211X displays from the , Character Interface to 6808 Microprocessor 2 74LS04 74LS138 DECODER G-1 G-2A G-2B Y4 C Y5 B Y6 A Y7 11 10 9 , the addition of a 74LS138 decoder. The 74LS138 is used to generate individual Chip Enables for each of , 6 11 10 9 7 74LS138 DECODER A B C Y4 G-2B Y5 G-2A Y6 G-1 Y7 74LS273 LATCH 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2
Hewlett-Packard
Original
intel 8085 microprocessor 8085 memory organization 8085 microprocessor 74LS373 Decoder latch used for 8085 8085 clock circuit

8085 microprocessor

Abstract: intel 8085 microprocessor addition of a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual , 8 7 4 3 11 4 6 4 5 3 2 1 D6 D5 D4 D3 D2 D1 74LS04 2 74LS138 , be connected to an unused output from the 74LS138 decoder. The display system can be shortened by , Interface 8085 UDCLOAD Subroutine Temporary Storage The 74LS138 is used to generate individual Chip , addition of a 74LS138 decoder. Figure 2 shows how the six lower order microprocessor address lines are
Avago Technologies
Original
8085 microprocessor Datasheet 8085 microprocesor ic 74ls138 information intel 8085 interfacing of ram with 8085 8085 hardware reset HDSP-211 5988-5632EN

block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature â'¢ Designed Specifically for High Speed Memory Decoders and Data Transmission Systems â'¢ Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception â'¢ Schottky Clamped for High Performance Description This , to 150°C 4-98 This Material Copyrighted By Its Respective Manufacturer GD54/74LS138 Application , . 4-99 This Material Copyrighted By Its Respective Manufacturer GD54/74LS138 Switching Characteristics
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74LS138 3 to 8 74LS138 application note 16-LINE 54LS decorder 3 line to 8 line FUNCTION OF 74LS138

74LS00

Abstract: 74LS00 TTL such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s. Read , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW
Hewlett-Packard
Original
HCTL1100 CS1100 RD1100 WR1100 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s 74LS00 DATA M-015 HCTL-1100/8051 OE1100 6000H

3 to 8 line decoder using 8051

Abstract: 74LS00 chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW SIGNAL
Avago Technologies
Original
HCTL-1100 M-015 HCTL-1100s 74LS00 application 8051 reset circuit m015 hctl microcontroller 8051s interfaces 5964-3776E
Abstract: Am25LS138 â'¢ Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M â'¢ Inverting and non-inverting enable inputs , mA 10 mA Max. Units Am54LS/74LS138 The Follow ing Conditions A p p ly Unless , to +5.0m/s DC Input Current 3-31 Am25LS/54LS/74LS138 SWITCHING C H A RA C TERISTIC S (TA = , H H H H H H H L Am25LS/54 LS/74LS138 APPLICATION G2B G2A H - H IG -
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54/74LS 25LS/54

sn74ls138n

Abstract: LS138 texas -1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 , -1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRG4 ACTIVE SO NS 16
Texas Instruments
Original
LS138 texas SNJ54LS 138FK 7600501EA SNJ54LS138J 7600501FA SNJ54LS138W
Abstract: SN74LS138N SN74LS138N 74LS138 74LS138 74LS138 74LS138 74LS138 74LS138 S138A S138A S138A SN74S138AN Texas Instruments
Original
SNJ54S 7604101EA SNJ54S138J 7604101FA SNJ54S138W JM38510/

74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 , /74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with , O0 O31 Figure a FAST AND LS TTL DATA 5-231 SN54/74LS138 GUARANTEED OPERATING RANGES
Motorola
Original
LS138 Motorola 74LS138 decoder pin diagram demultiplexer 74LS138 LS04

and gate 74LS138

Abstract: SP74HCT138N pin compatibility with the 74LS138. Speeds are comparable to the low power Schottky device family , SP74HCT138 m SPI DECODER/DEMULTIPLEXER FEATURES â  Designed for high performance memory decoders in microprocessor systems â  3 to 8 line decoders include 3 enable inputs â  Pin compatible with 74LS138 â  SPI CMOS technology â  Full TTL interface capability â  High noise immunity â  Low quiescent power dissipation GENERAL DESCRIPTION The SP74HCT138 is manufactured in the SPI CMOS
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SP74HCT138N SP74HCT138J and gate 74LS138 74LS138 pin SP74HCT

64LS138

Abstract: conditions SN 64LS138 SN 74LS138 MIN Supply voltage M AX M IN NOM MAX 4 .5 5 5.5 , - 1 .5 Vj|_ = M AX, V|j_ = M AX V c c = MAX, SN 74LS138 3.4 I| = - 1 8 mA V c c = M , 'PHL 'PHL UNIT SN 74LS138 MIN 32 ns 14 26 ns 13 38 ns SN 5 4S138 , S
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54S138 SN54S138 SN74S138A

8085 microprocessor hex code

Abstract: code lock using 8085 microprocessor ddition of a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual C , connected to an unused o u tp u t from the 74LS138 decoder. The display system can be shortened by removing , ith the addition of a 74LS138 decoder. The 74LS138 is used to generate individual C hip Enables fo r
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8085 microprocessor hex code code lock using 8085 microprocessor 8085 hex code 40 pin 8085 74LS007 LS 74LS138 HDSP211X
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